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whitespace: Delete all trailing white spaces

main
Istvan Csomortani 2019-06-05 16:37:34 +03:00 committed by István Csomortáni
parent 3bf120123b
commit 70b7d69ff8
60 changed files with 542 additions and 542 deletions
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10
library/altera/jesd204_phy/jesd204_phy_glue_hw.tcl
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@ -191,7 +191,7 @@ proc glue_add_if_port_conduit {num ifname port phy_port dir width} {
set phy_dir "Input" set phy_dir "Input"
set phy_sig "in" set phy_sig "in"
} }
for {set i 0} {$i < $num} {incr i} { for {set i 0} {$i < $num} {incr i} {
set base [expr $sig_offset + $width * $i] set base [expr $sig_offset + $width * $i]
@ -214,7 +214,7 @@ proc glue_add_const_conduit {port width} {
set ifname phy_${port} set ifname phy_${port}
add_interface $ifname conduit end add_interface $ifname conduit end
add_interface_port $ifname $ifname $port Output $width add_interface_port $ifname $ifname $port Output $width
set_port_property $ifname fragment_list [format "const_out(%d:%d)" \ set_port_property $ifname fragment_list [format "const_out(%d:%d)" \
[expr $const_offset + $width - 1] $const_offset] [expr $const_offset + $width - 1] $const_offset]
@ -248,7 +248,7 @@ proc jesd204_phy_glue_elab {} {
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1 glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1 glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1
glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32 glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32
if {[get_parameter TX_OR_RX_N]} { if {[get_parameter TX_OR_RX_N]} {
glue_add_if $num_of_lanes tx_clkout clock source glue_add_if $num_of_lanes tx_clkout clock source
glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1 glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1
@ -288,10 +288,10 @@ proc jesd204_phy_glue_elab {} {
glue_add_if $num_of_lanes rx_coreclkin clock sink true glue_add_if $num_of_lanes rx_coreclkin clock sink true
glue_add_if_port $num_of_lanes rx_coreclkin rx_coreclkin clk Input 1 true glue_add_if_port $num_of_lanes rx_coreclkin rx_coreclkin clk Input 1 true
glue_add_if $num_of_lanes rx_clkout clock source glue_add_if $num_of_lanes rx_clkout clock source
glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1 glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1
if {$soft_pcs} { if {$soft_pcs} {
for {set i 0} {$i < $num_of_lanes} {incr i} { for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface rx_raw_data_${i} conduit start add_interface rx_raw_data_${i} conduit start

2
library/axi_ad5766/axi_ad5766.v
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@ -350,7 +350,7 @@ module axi_ad5766 #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY), .FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE), .SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE), .DEV_PACKAGE (DEV_PACKAGE),
.CONFIG (0), .CONFIG (0),
.CLK_EDGE_SEL (0), .CLK_EDGE_SEL (0),
.DRP_DISABLE (6'h00), .DRP_DISABLE (6'h00),

62
library/axi_ad9162/axi_ad9162_channel.v
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@ -44,15 +44,15 @@ module axi_ad9162_channel #(
parameter DATAPATH_DISABLE = 0) ( parameter DATAPATH_DISABLE = 0) (
// dac interface // dac interface
input dac_clk, input dac_clk,
input dac_rst, input dac_rst,
output dac_enable, output dac_enable,
output [255:0] dac_data, output [255:0] dac_data,
input [255:0] dma_data, input [255:0] dma_data,
// processor interface // processor interface
input dac_data_sync, input dac_data_sync,
input dac_dds_format, input dac_dds_format,
@ -68,9 +68,9 @@ module axi_ad9162_channel #(
input [ 13:0] up_raddr, input [ 13:0] up_raddr,
output [ 31:0] up_rdata, output [ 31:0] up_rdata,
output up_rack); output up_rack);
// internal registers // internal registers
reg [255:0] dac_data_int = 'd0; reg [255:0] dac_data_int = 'd0;
reg dac_enable_int = 'd0; reg dac_enable_int = 'd0;
reg [255:0] dac_data_d = 'd0; reg [255:0] dac_data_d = 'd0;
@ -109,9 +109,9 @@ module axi_ad9162_channel #(
reg [ 15:0] dac_dds_incr_0 = 'd0; reg [ 15:0] dac_dds_incr_0 = 'd0;
reg [ 15:0] dac_dds_incr_1 = 'd0; reg [ 15:0] dac_dds_incr_1 = 'd0;
reg [255:0] dac_dds_data = 'd0; reg [255:0] dac_dds_data = 'd0;
// internal signals // internal signals
wire [ 15:0] dac_dds_scale_1_s; wire [ 15:0] dac_dds_scale_1_s;
wire [ 15:0] dac_dds_init_1_s; wire [ 15:0] dac_dds_init_1_s;
wire [ 15:0] dac_dds_incr_1_s; wire [ 15:0] dac_dds_incr_1_s;
@ -148,7 +148,7 @@ module axi_ad9162_channel #(
dac_data_int[ 31: 16] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 47: 32] : dac_data_d[ 31: 16]; dac_data_int[ 31: 16] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 47: 32] : dac_data_d[ 31: 16];
dac_data_int[ 15: 0] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 15: 0] : dac_data_d[ 15: 0]; dac_data_int[ 15: 0] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 15: 0] : dac_data_d[ 15: 0];
end end
// dac pattern data // dac pattern data
genvar n; genvar n;
@ -158,9 +158,9 @@ module axi_ad9162_channel #(
assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s; assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
end end
endgenerate endgenerate
// dac data select // dac data select
assign dac_enable = dac_enable_int; assign dac_enable = dac_enable_int;
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
@ -172,9 +172,9 @@ module axi_ad9162_channel #(
default: dac_data_d <= dac_dds_data; default: dac_data_d <= dac_dds_data;
endcase endcase
end end
// dds // dds
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_data_sync == 1'b0) begin if (dac_data_sync == 1'b0) begin
dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0; dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
@ -286,7 +286,7 @@ module axi_ad9162_channel #(
dac_dds_data <= 256'd0; dac_dds_data <= 256'd0;
end end
end end
assign dac_dds_data_s[255:240] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[239:224] : dac_dds_data_i_s[255:240]; assign dac_dds_data_s[255:240] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[239:224] : dac_dds_data_i_s[255:240];
assign dac_dds_data_s[239:224] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[255:240] : dac_dds_data_i_s[239:224]; assign dac_dds_data_s[239:224] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[255:240] : dac_dds_data_i_s[239:224];
assign dac_dds_data_s[223:208] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[207:192] : dac_dds_data_i_s[223:208]; assign dac_dds_data_s[223:208] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[207:192] : dac_dds_data_i_s[223:208];
@ -303,7 +303,7 @@ module axi_ad9162_channel #(
assign dac_dds_data_s[ 47: 32] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 63: 48] : dac_dds_data_i_s[ 47: 32]; assign dac_dds_data_s[ 47: 32] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 63: 48] : dac_dds_data_i_s[ 47: 32];
assign dac_dds_data_s[ 31: 16] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 15: 0] : dac_dds_data_i_s[ 31: 16]; assign dac_dds_data_s[ 31: 16] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 15: 0] : dac_dds_data_i_s[ 31: 16];
assign dac_dds_data_s[ 15: 0] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 31: 16] : dac_dds_data_i_s[ 15: 0]; assign dac_dds_data_s[ 15: 0] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 31: 16] : dac_dds_data_i_s[ 15: 0];
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -317,7 +317,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_00_1), .dds_phase_1 (dac_dds_phase_00_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[15:0])); .dds_data (dac_dds_data_i_s[15:0]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -331,7 +331,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_01_1), .dds_phase_1 (dac_dds_phase_01_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[31:16])); .dds_data (dac_dds_data_i_s[31:16]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -345,7 +345,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_02_1), .dds_phase_1 (dac_dds_phase_02_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[47:32])); .dds_data (dac_dds_data_i_s[47:32]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -359,7 +359,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_03_1), .dds_phase_1 (dac_dds_phase_03_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[63:48])); .dds_data (dac_dds_data_i_s[63:48]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -373,7 +373,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_04_1), .dds_phase_1 (dac_dds_phase_04_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[79:64])); .dds_data (dac_dds_data_i_s[79:64]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -387,7 +387,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_05_1), .dds_phase_1 (dac_dds_phase_05_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[95:80])); .dds_data (dac_dds_data_i_s[95:80]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -401,7 +401,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_06_1), .dds_phase_1 (dac_dds_phase_06_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[111:96])); .dds_data (dac_dds_data_i_s[111:96]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -415,7 +415,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_07_1), .dds_phase_1 (dac_dds_phase_07_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[127:112])); .dds_data (dac_dds_data_i_s[127:112]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -429,7 +429,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_08_1), .dds_phase_1 (dac_dds_phase_08_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[143:128])); .dds_data (dac_dds_data_i_s[143:128]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -443,7 +443,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_09_1), .dds_phase_1 (dac_dds_phase_09_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[159:144])); .dds_data (dac_dds_data_i_s[159:144]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -457,7 +457,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_10_1), .dds_phase_1 (dac_dds_phase_10_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[175:160])); .dds_data (dac_dds_data_i_s[175:160]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -471,7 +471,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_11_1), .dds_phase_1 (dac_dds_phase_11_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[191:176])); .dds_data (dac_dds_data_i_s[191:176]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -485,7 +485,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_12_1), .dds_phase_1 (dac_dds_phase_12_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[207:192])); .dds_data (dac_dds_data_i_s[207:192]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -499,7 +499,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_13_1), .dds_phase_1 (dac_dds_phase_13_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[223:208])); .dds_data (dac_dds_data_i_s[223:208]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -513,7 +513,7 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_14_1), .dds_phase_1 (dac_dds_phase_14_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[239:224])); .dds_data (dac_dds_data_i_s[239:224]));
ad_dds_2 #( ad_dds_2 #(
.DISABLE (DATAPATH_DISABLE), .DISABLE (DATAPATH_DISABLE),
.DDS_TYPE (DAC_DDS_TYPE), .DDS_TYPE (DAC_DDS_TYPE),
@ -527,9 +527,9 @@ module axi_ad9162_channel #(
.dds_phase_1 (dac_dds_phase_15_1), .dds_phase_1 (dac_dds_phase_15_1),
.dds_scale_1 (dac_dds_scale_2_s), .dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_i_s[255:240])); .dds_data (dac_dds_data_i_s[255:240]));
// single channel processor // single channel processor
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk), .dac_clk (dac_clk),
.dac_rst (dac_rst), .dac_rst (dac_rst),

2
library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
View File

@ -78,7 +78,7 @@ module axi_ad9361_alt_lvds_rx (
// internal signals // internal signals
wire [27:0] rx_data_s; wire [27:0] rx_data_s;
// instantiations // instantiations
assign rx_frame[3] = rx_data_s[24]; assign rx_frame[3] = rx_data_s[24];

2
library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
View File

@ -86,7 +86,7 @@ module axi_ad9361_alt_lvds_tx (
wire core_clk; wire core_clk;
wire [27:0] tx_data_s; wire [27:0] tx_data_s;
// instantiations // instantiations
assign tx_clk_out_n = 1'd0; assign tx_clk_out_n = 1'd0;

10
library/axi_ad9361/altera/axi_ad9361_lvds_if.v
View File

@ -202,7 +202,7 @@ module axi_ad9361_lvds_if #(
end end
// r1mode // r1mode
always @(negedge clk) begin always @(negedge clk) begin
adc_r1_mode_n <= adc_r1_mode; adc_r1_mode_n <= adc_r1_mode;
end end
@ -212,7 +212,7 @@ module axi_ad9361_lvds_if #(
end end
// frame check // frame check
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_r1_mode == 1'd1) begin if (rx_r1_mode == 1'd1) begin
rx_frame_d <= rx_frame_s; rx_frame_d <= rx_frame_s;
@ -222,7 +222,7 @@ module axi_ad9361_lvds_if #(
end end
// data hold // data hold
always @(posedge l_clk) begin always @(posedge l_clk) begin
rx_data_3 <= rx_data_3_s; rx_data_3 <= rx_data_3_s;
rx_data_2 <= rx_data_2_s; rx_data_2 <= rx_data_2_s;
@ -230,7 +230,7 @@ module axi_ad9361_lvds_if #(
end end
// delineation // delineation
always @(posedge l_clk) begin always @(posedge l_clk) begin
case ({rx_r1_mode, rx_frame_s}) case ({rx_r1_mode, rx_frame_s})
5'b01111: begin 5'b01111: begin
@ -313,7 +313,7 @@ module axi_ad9361_lvds_if #(
end end
// adc-status // adc-status
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_frame_d == rx_frame_s) begin if (rx_frame_d == rx_frame_s) begin
adc_status_p <= locked_s; adc_status_p <= locked_s;

4
library/axi_ad9361/altera/axi_ad9361_lvds_if_10.v
View File

@ -83,7 +83,7 @@ module axi_ad9361_lvds_if_10 (
input tx_txnrx, input tx_txnrx,
// locked (status) // locked (status)
output locked, output locked,
// delay interface // delay interface
@ -106,7 +106,7 @@ module axi_ad9361_lvds_if_10 (
wire alt_lvds_clk; wire alt_lvds_clk;
wire alt_lvds_loaden; wire alt_lvds_loaden;
wire [ 7:0] alt_lvds_phase; wire [ 7:0] alt_lvds_phase;
// pll reset // pll reset
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin

4
library/axi_ad9361/altera/axi_ad9361_lvds_if_c5.v
View File

@ -83,7 +83,7 @@ module axi_ad9361_lvds_if_c5 (
input tx_txnrx, input tx_txnrx,
// locked (status) // locked (status)
output locked, output locked,
// delay interface // delay interface
@ -110,7 +110,7 @@ module axi_ad9361_lvds_if_c5 (
wire rx_locked_s; wire rx_locked_s;
wire tx_core_clk; wire tx_core_clk;
wire tx_locked_s; wire tx_locked_s;
// pll reset // pll reset
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin

8
library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
View File

@ -168,7 +168,7 @@ module axi_ad9361_cmos_if #(
assign up_drp_locked = 1'd1; assign up_drp_locked = 1'd1;
// r1mode // r1mode
always @(negedge clk) begin always @(negedge clk) begin
adc_r1_mode_n <= adc_r1_mode; adc_r1_mode_n <= adc_r1_mode;
end end
@ -178,7 +178,7 @@ module axi_ad9361_cmos_if #(
end end
// adc-status // adc-status
assign delay_locked = locked_s; assign delay_locked = locked_s;
always @(posedge l_clk) begin always @(posedge l_clk) begin
@ -187,7 +187,7 @@ module axi_ad9361_cmos_if #(
end end
// frame check // frame check
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_r1_mode == 1'd1) begin if (rx_r1_mode == 1'd1) begin
rx_frame <= rx_frame_s; rx_frame <= rx_frame_s;
@ -197,7 +197,7 @@ module axi_ad9361_cmos_if #(
end end
// data hold // data hold
always @(posedge l_clk) begin always @(posedge l_clk) begin
rx_data_1 <= rx_data_1_s; rx_data_1 <= rx_data_1_s;
end end

14
library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
View File

@ -183,7 +183,7 @@ module axi_ad9361_lvds_if #(
assign up_drp_locked = 1'd1; assign up_drp_locked = 1'd1;
// r1mode // r1mode
always @(negedge clk) begin always @(negedge clk) begin
adc_r1_mode_n <= adc_r1_mode; adc_r1_mode_n <= adc_r1_mode;
end end
@ -193,7 +193,7 @@ module axi_ad9361_lvds_if #(
end end
// adc-status // adc-status
assign delay_locked = locked_s; assign delay_locked = locked_s;
always @(posedge l_clk) begin always @(posedge l_clk) begin
@ -202,7 +202,7 @@ module axi_ad9361_lvds_if #(
end end
// altera-equivalence // altera-equivalence
always @(posedge l_clk) begin always @(posedge l_clk) begin
rx_valid <= ~rx_valid; rx_valid <= ~rx_valid;
rx_frame <= rx_frame_s; rx_frame <= rx_frame_s;
@ -211,7 +211,7 @@ module axi_ad9361_lvds_if #(
end end
// frame check // frame check
assign rx_frame_d_s = {rx_frame_s, rx_frame}; assign rx_frame_d_s = {rx_frame_s, rx_frame};
always @(posedge l_clk) begin always @(posedge l_clk) begin
@ -225,7 +225,7 @@ module axi_ad9361_lvds_if #(
end end
// data hold // data hold
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_valid == 1'd1) begin if (rx_valid == 1'd1) begin
rx_data_1_2d <= rx_data_1_s; rx_data_1_2d <= rx_data_1_s;
@ -235,7 +235,7 @@ module axi_ad9361_lvds_if #(
end end
// delineation // delineation
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_valid == 1'b1) begin if (rx_valid == 1'b1) begin
case ({rx_r1_mode, rx_frame_s, rx_frame}) case ({rx_r1_mode, rx_frame_s, rx_frame})
@ -323,7 +323,7 @@ module axi_ad9361_lvds_if #(
end end
// adc-status // adc-status
always @(posedge l_clk) begin always @(posedge l_clk) begin
if (rx_valid == 1'b1) begin if (rx_valid == 1'b1) begin
if (rx_frame_d == rx_frame_d_s) begin if (rx_frame_d == rx_frame_d_s) begin

12
library/axi_ad9371/axi_ad9371_tx.v
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@ -52,7 +52,7 @@ module axi_ad9371_tx #(
output dac_rst, output dac_rst,
input dac_clk, input dac_clk,
output [127:0] dac_data, output [127:0] dac_data,
// master/slave // master/slave
input dac_sync_in, input dac_sync_in,
@ -88,7 +88,7 @@ module axi_ad9371_tx #(
output reg up_rack); output reg up_rack);
// internal registers // internal registers
@ -132,7 +132,7 @@ module axi_ad9371_tx #(
// dac channel // dac channel
assign dac_valid_i0 = 1'b1; assign dac_valid_i0 = 1'b1;
axi_ad9371_tx_channel #( axi_ad9371_tx_channel #(
.CHANNEL_ID (0), .CHANNEL_ID (0),
.Q_OR_I_N (0), .Q_OR_I_N (0),
@ -162,7 +162,7 @@ module axi_ad9371_tx #(
.up_rack (up_rack_s[0])); .up_rack (up_rack_s[0]));
// dac channel // dac channel
assign dac_valid_q0 = 1'b1; assign dac_valid_q0 = 1'b1;
axi_ad9371_tx_channel #( axi_ad9371_tx_channel #(
@ -194,7 +194,7 @@ module axi_ad9371_tx #(
.up_rack (up_rack_s[1])); .up_rack (up_rack_s[1]));
// dac channel // dac channel
assign dac_valid_i1 = 1'b1; assign dac_valid_i1 = 1'b1;
axi_ad9371_tx_channel #( axi_ad9371_tx_channel #(
@ -226,7 +226,7 @@ module axi_ad9371_tx #(
.up_rack (up_rack_s[2])); .up_rack (up_rack_s[2]));
// dac channel // dac channel
assign dac_valid_q1 = 1'b1; assign dac_valid_q1 = 1'b1;
axi_ad9371_tx_channel #( axi_ad9371_tx_channel #(

2
library/axi_ad9434/axi_ad9434.v
View File

@ -38,7 +38,7 @@
module axi_ad9434 #( module axi_ad9434 #(
parameter ID = 0, parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0, parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0, parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,

2
library/axi_ad9467/axi_ad9467_pnmon.v
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@ -50,7 +50,7 @@ module axi_ad9467_pnmon (
input [ 3:0] adc_pnseq_sel); input [ 3:0] adc_pnseq_sel);
// internal registers // internal registers
reg adc_valid_in = 'd0; reg adc_valid_in = 'd0;
reg [31:0] adc_pn_data_in = 'd0; reg [31:0] adc_pn_data_in = 'd0;
reg [31:0] adc_pn_data_pn = 'd0; reg [31:0] adc_pn_data_pn = 'd0;

2
library/axi_ad9625/axi_ad9625_if.v
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@ -38,7 +38,7 @@
module axi_ad9625_if #( module axi_ad9625_if #(
parameter ID = 0) ( parameter ID = 0) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
input rx_clk, input rx_clk,

2
library/axi_ad9671/axi_ad9671_if.v
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@ -40,7 +40,7 @@ module axi_ad9671_if #(
parameter QUAD_OR_DUAL_N = 1, parameter QUAD_OR_DUAL_N = 1,
parameter ID = 0) ( parameter ID = 0) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
input rx_clk, input rx_clk,

2
library/axi_ad9680/axi_ad9680.v
View File

@ -43,7 +43,7 @@ module axi_ad9680 #(
parameter SPEED_GRADE = 0, parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0) ( parameter DEV_PACKAGE = 0) (
// jesd interface // jesd interface
// rx_clk is (line-rate/40) // rx_clk is (line-rate/40)
input rx_clk, input rx_clk,

2
library/axi_ad9963/axi_ad9963_rx_channel.v
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@ -147,7 +147,7 @@ module axi_ad9963_rx_channel #(
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N), ad_iqcor #(.Q_OR_I_N (Q_OR_I_N),
.DISABLE(IQCORRECTION_DISABLE == 1), .DISABLE(IQCORRECTION_DISABLE == 1),
.SCALE_ONLY(SCALECORRECTION_ONLY)) .SCALE_ONLY(SCALECORRECTION_ONLY))
i_ad_iqcor ( i_ad_iqcor (
.clk (adc_clk), .clk (adc_clk),
.valid (adc_dcfilter_valid_s), .valid (adc_dcfilter_valid_s),

2
library/axi_dac_interpolate/axi_dac_interpolate_filter.v
View File

@ -76,7 +76,7 @@ module axi_dac_interpolate_filter #(
ad_iqcor #(.Q_OR_I_N (0), ad_iqcor #(.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE), .DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)) .SCALE_ONLY(1))
i_ad_iqcor ( i_ad_iqcor (
.clk (dac_clk), .clk (dac_clk),
.valid (dac_valid), .valid (dac_valid),

2
library/axi_dmac/axi_dmac_response_manager.v
View File

@ -244,7 +244,7 @@ always @(posedge req_clk) begin
end end
end end
// Once the last completion is received wit until all completions are done // Once the last completion is received wit until all completions are done
always @(posedge req_clk) begin always @(posedge req_clk) begin
if (req_resetn == 1'b0) begin if (req_resetn == 1'b0) begin
completion_req_ready <= 1'b1; completion_req_ready <= 1'b1;

6
library/axi_dmac/request_generator.v
View File

@ -153,13 +153,13 @@ always @(posedge clk) begin
end end
end end
/* /*
* Once rewind request is received we need to stop incrementing the burst ID. * Once rewind request is received we need to stop incrementing the burst ID.
* *
* If the current segment matches the segment that was interrupted and * If the current segment matches the segment that was interrupted and
* if it was a last segment we ignore consecutive segments until the last * if it was a last segment we ignore consecutive segments until the last
* segment is received, in other case we can jump to the next segment. * segment is received, in other case we can jump to the next segment.
* *
* If the current segment is newer than the one got interrupted and the * If the current segment is newer than the one got interrupted and the
* interrupted one was a last segment we need to replay the current * interrupted one was a last segment we need to replay the current
* segment with the adjusted burst ID. If the interrupted segment was not last * segment with the adjusted burst ID. If the interrupted segment was not last

24
library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
View File

@ -47,8 +47,8 @@ module axi_fmcadc5_sync #(
parameter [ 7:0] DEV_PACKAGE = 0) ( parameter [ 7:0] DEV_PACKAGE = 0) (
// receive interface // receive interface
input rx_clk, input rx_clk,
output rx_sysref, output rx_sysref,
input rx_sync_0, input rx_sync_0,
input rx_sync_1, input rx_sync_1,
@ -74,7 +74,7 @@ module axi_fmcadc5_sync #(
output psync, output psync,
// delay interface // delay interface
input delay_rst, input delay_rst,
input delay_clk, input delay_clk,
@ -252,7 +252,7 @@ module axi_fmcadc5_sync #(
assign up_clk = s_axi_aclk; assign up_clk = s_axi_aclk;
// switching regulator clocks (~602K) // switching regulator clocks (~602K)
assign psync = up_psync; assign psync = up_psync;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
@ -335,7 +335,7 @@ module axi_fmcadc5_sync #(
end end
end end
// calibration signal register(s) // calibration signal register(s)
assign vcal = up_vcal; assign vcal = up_vcal;
@ -362,7 +362,7 @@ module axi_fmcadc5_sync #(
end end
end end
// sysref register(s) // sysref register(s)
assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2; assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2;
@ -405,7 +405,7 @@ module axi_fmcadc5_sync #(
end end
end end
// sync register(s) // sync register(s)
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
@ -424,7 +424,7 @@ module axi_fmcadc5_sync #(
end end
// simple current status (no persistence) // simple current status (no persistence)
assign up_sync_status_t_s = up_sync_status_t_m3 ^ up_sync_status_t_m2; assign up_sync_status_t_s = up_sync_status_t_m3 ^ up_sync_status_t_m2;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
@ -464,7 +464,7 @@ module axi_fmcadc5_sync #(
end end
// switching must be glitchless // switching must be glitchless
assign spi_csn = up_spi_csn_int; assign spi_csn = up_spi_csn_int;
assign spi_clk = up_spi_clk_int; assign spi_clk = up_spi_clk_int;
assign spi_mosi = up_spi_mosi_int; assign spi_mosi = up_spi_mosi_int;
@ -480,7 +480,7 @@ module axi_fmcadc5_sync #(
up_spi_mosi_int <= spi_sdo_o; up_spi_mosi_int <= spi_sdo_o;
end end
end end
assign up_spi_gnt_s = (&spi_csn_o) & ~spi_clk_o; assign up_spi_gnt_s = (&spi_csn_o) & ~spi_clk_o;
always @(posedge up_clk or negedge up_rstn) begin always @(posedge up_clk or negedge up_rstn) begin
@ -748,7 +748,7 @@ module axi_fmcadc5_sync #(
end end
// sync buffers // sync buffers
OBUFDS i_obufds_rx_sync_1 ( OBUFDS i_obufds_rx_sync_1 (
.I (rx_sync_out_1), .I (rx_sync_out_1),
.O (rx_sync_1_p), .O (rx_sync_1_p),
@ -784,7 +784,7 @@ module axi_fmcadc5_sync #(
.delay_locked (up_delay_locked_s)); .delay_locked (up_delay_locked_s));
// up == micro("u") processor // up == micro("u") processor
up_axi i_up_axi ( up_axi i_up_axi (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),

8
library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
View File

@ -41,7 +41,7 @@
module axi_fmcadc5_sync_calcor ( module axi_fmcadc5_sync_calcor (
// receive interface // receive interface
input rx_clk, input rx_clk,
input rx_enable_0, input rx_enable_0,
input [255:0] rx_data_0, input [255:0] rx_data_0,
@ -102,11 +102,11 @@ module axi_fmcadc5_sync_calcor (
wire [ 15:0] rx_data_1_s[0:15]; wire [ 15:0] rx_data_1_s[0:15];
// iterations // iterations
genvar n; genvar n;
// offset & gain // offset & gain
assign rx_enable = rx_enable_int; assign rx_enable = rx_enable_int;
always @(posedge rx_clk) begin always @(posedge rx_clk) begin
@ -196,7 +196,7 @@ module axi_fmcadc5_sync_calcor (
end end
// peak iterations // peak iterations
generate generate
for (n = 0; n <= 1; n = n + 1) begin: g_rx_peak_4 for (n = 0; n <= 1; n = n + 1) begin: g_rx_peak_4
always @(posedge rx_clk) begin always @(posedge rx_clk) begin

2
library/axi_hdmi_rx/axi_hdmi_rx_core.v
View File

@ -37,7 +37,7 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_hdmi_rx_core #( module axi_hdmi_rx_core #(
parameter IO_INTERFACE = 1) ( parameter IO_INTERFACE = 1) (
// hdmi interface // hdmi interface

2
library/axi_i2s_adi/axi_i2s_adi_ip.tcl
View File

@ -23,7 +23,7 @@ adi_ip_properties axi_i2s_adi
set_property PROCESSING_ORDER LATE [ipx::get_files axi_i2s_adi_constr.xdc \ set_property PROCESSING_ORDER LATE [ipx::get_files axi_i2s_adi_constr.xdc \
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
-filter {NAME =~ *synthesis*}]] -filter {NAME =~ *synthesis*}]]
adi_ip_infer_streaming_interfaces axi_i2s_adi adi_ip_infer_streaming_interfaces axi_i2s_adi

2
library/axi_mc_current_monitor/axi_mc_current_monitor.v
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@ -78,7 +78,7 @@ module axi_mc_current_monitor (
input s_axi_rready, input s_axi_rready,
input [ 2:0] s_axi_awprot, input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot input [ 2:0] s_axi_arprot
); );
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------

4
library/axi_mc_current_monitor/dec256sinc24b.v
View File

@ -85,7 +85,7 @@ begin
end end
end end
/*ACCUMULATOR (INTEGRATOR) /*ACCUMULATOR (INTEGRATOR)
* Perform the accumulation (IIR) at the speed of the modulator. * Perform the accumulation (IIR) at the speed of the modulator.
* mclkout_i = modulators conversion bit rate */ * mclkout_i = modulators conversion bit rate */
always @(negedge mclkout_i or posedge reset_i) always @(negedge mclkout_i or posedge reset_i)
@ -124,7 +124,7 @@ begin
word_clk <= word_count[7]; word_clk <= word_count[7];
end end
/*DIFFERENTIATOR (including decimation stage) /*DIFFERENTIATOR (including decimation stage)
* Perform the differentiation stage (FIR) at a lower speed. * Perform the differentiation stage (FIR) at a lower speed.
WORD_CLK = output word rate */ WORD_CLK = output word rate */
always @(posedge word_clk or posedge reset_i) always @(posedge word_clk or posedge reset_i)

12
library/axi_mc_speed/delay_30_degrees.v
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@ -152,27 +152,27 @@ begin
if (position_i == 3'b101) if (position_i == 3'b101)
begin begin
position_o <= 100; position_o <= 100;
end end
if (position_i == 3'b100) if (position_i == 3'b100)
begin begin
position_o <= 110; position_o <= 110;
end end
if (position_i == 3'b110) if (position_i == 3'b110)
begin begin
position_o <= 010; position_o <= 010;
end end
if (position_i == 3'b010) if (position_i == 3'b010)
begin begin
position_o <= 011; position_o <= 011;
end end
if (position_i == 3'b011) if (position_i == 3'b011)
begin begin
position_o <= 001; position_o <= 001;
end end
if (position_i == 3'b001) if (position_i == 3'b001)
begin begin
position_o <= 101; position_o <= 101;
end end
position_old <= position_i; position_old <= position_i;
if (speed_count < MAX_SPEED_COUNT) if (speed_count < MAX_SPEED_COUNT)
begin begin

2
library/common/ad_pps_receiver_constr.ttcl
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@ -10,7 +10,7 @@
set_property ASYNC_REG TRUE \ set_property ASYNC_REG TRUE \
[get_cells -hier *_pps_m*] \ [get_cells -hier *_pps_m*] \
[get_cells -hier *_pps_status_m*] [get_cells -hier *_pps_status_m*]
set_false_path -to [get_cells -hier -filter {name =~ *_pps_m_reg[0] && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *_pps_m_reg[0] && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *pps_status_reg && IS_SEQUENTIAL}] \ set_false_path -from [get_cells -hier -filter {name =~ *pps_status_reg && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_pps_status_m_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_pps_status_m_reg && IS_SEQUENTIAL}]

2
library/common/ad_ss_444to422.v
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@ -75,7 +75,7 @@ module ad_ss_444to422 #(
wire [ 9:0] cr_s; wire [ 9:0] cr_s;
wire [ 9:0] cb_s; wire [ 9:0] cb_s;
// fill the data pipe lines, hold the last data on edges // fill the data pipe lines, hold the last data on edges
always @(posedge clk) begin always @(posedge clk) begin
s444_de_d <= s444_de; s444_de_d <= s444_de;

2
library/util_axis_fifo/util_axis_fifo.v
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@ -171,7 +171,7 @@ end else begin
); );
// When the clocks are asynchronous instantiate a block RAM // When the clocks are asynchronous instantiate a block RAM
// regardless of the requested size to make sure we threat the // regardless of the requested size to make sure we threat the
// clock crossing correctly // clock crossing correctly
ad_mem #( ad_mem #(
.DATA_WIDTH (DATA_WIDTH), .DATA_WIDTH (DATA_WIDTH),

2
library/util_bsplit/util_bsplit.v
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@ -59,7 +59,7 @@ module util_bsplit #(
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s; wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s;
// extend and split // extend and split
assign data_s[((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):(NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)] = 'd0; assign data_s[((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):(NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)] = 'd0;
assign data_s[((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] = data; assign data_s[((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] = data;

4
library/util_cdc/util_cdc_constr.tcl
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@ -2,8 +2,8 @@
# *************************************************************************** # ***************************************************************************
# Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. # Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
# #
# Each core or library found in this collection may have its own licensing terms. # Each core or library found in this collection may have its own licensing terms.
# The user should keep this in in mind while exploring these cores. # The user should keep this in in mind while exploring these cores.
# #
# Redistribution and use in source and binary forms, # Redistribution and use in source and binary forms,
# with or without modification of this file, are permitted under the terms of either # with or without modification of this file, are permitted under the terms of either

4
library/util_cdc/util_cdc_ip.tcl
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@ -2,8 +2,8 @@
# *************************************************************************** # ***************************************************************************
# Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. # Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
# #
# Each core or library found in this collection may have its own licensing terms. # Each core or library found in this collection may have its own licensing terms.
# The user should keep this in in mind while exploring these cores. # The user should keep this in in mind while exploring these cores.
# #
# Redistribution and use in source and binary forms, # Redistribution and use in source and binary forms,
# with or without modification of this file, are permitted under the terms of either # with or without modification of this file, are permitted under the terms of either

4
library/util_clkdiv/util_clkdiv_alt.v
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@ -61,13 +61,13 @@ end
always @(posedge clk) begin always @(posedge clk) begin
enable <= ~enable; enable <= ~enable;
end end
generate if (SIM_DEVICE == "CYCLONE5") begin generate if (SIM_DEVICE == "CYCLONE5") begin
cyclonev_clkena #( cyclonev_clkena #(
.clock_type ("Global Clock"), .clock_type ("Global Clock"),
.ena_register_mode ("falling edge"), .ena_register_mode ("falling edge"),
.lpm_type ("cyclonev_clkena") .lpm_type ("cyclonev_clkena")
) clock_divider_by_2 ( ) clock_divider_by_2 (
.ena(enable), .ena(enable),
.enaout(), .enaout(),
.inclk(clk), .inclk(clk),

2
library/util_pack/util_upack2/util_upack2_hw.tcl
View File

@ -102,7 +102,7 @@ proc util_upack_elab {} {
set_port_property fifo_rd_en_${n} fragment_list "fifo_rd_en(${n})" set_port_property fifo_rd_en_${n} fragment_list "fifo_rd_en(${n})"
add_interface_port dac_ch_${n} fifo_rd_valid_${n} data_valid Output 1 add_interface_port dac_ch_${n} fifo_rd_valid_${n} data_valid Output 1
set_port_property fifo_rd_valid_${n} fragment_list "fifo_rd_valid(0)" set_port_property fifo_rd_valid_${n} fragment_list "fifo_rd_valid(0)"
add_interface_port dac_ch_${n} fifo_rd_data_${n} data Output $channel_data_width add_interface_port dac_ch_${n} fifo_rd_data_${n} data Output $channel_data_width
set_port_property fifo_rd_data_${n} fragment_list [format "fifo_rd_data(%d:%d)" \ set_port_property fifo_rd_data_${n} fragment_list [format "fifo_rd_data(%d:%d)" \
[expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]] [expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]]
set_interface_property dac_ch_${n} associatedClock clk set_interface_property dac_ch_${n} associatedClock clk

2
library/util_rfifo/util_rfifo_hw.tcl
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@ -54,7 +54,7 @@ proc util_rfifo_elab {} {
add_interface_port din_${n} din_data_${n} data Input DIN_DATA_WIDTH add_interface_port din_${n} din_data_${n} data Input DIN_DATA_WIDTH
set_interface_property din_${n} associatedClock if_din_clk set_interface_property din_${n} associatedClock if_din_clk
set_interface_property din_${n} associatedReset none set_interface_property din_${n} associatedReset none
add_interface dout_${n} conduit end add_interface dout_${n} conduit end
add_interface_port dout_${n} dout_enable_${n} enable Input 1 add_interface_port dout_${n} dout_enable_${n} enable Input 1
add_interface_port dout_${n} dout_valid_${n} valid Input 1 add_interface_port dout_${n} dout_valid_${n} valid Input 1

2
library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
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@ -105,7 +105,7 @@ module axi_adcfifo_rd #(
wire axi_ready_s; wire axi_ready_s;
// read is way too slow- buffer mode // read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready; assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;

2
library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
View File

@ -155,7 +155,7 @@ module axi_adxcvr_mdrp (
end end
endgenerate endgenerate
endmodule endmodule
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************

2
library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
View File

@ -80,7 +80,7 @@ module axi_adxcvr_mstatus (
end end
end end
endmodule endmodule
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************

2
library/xilinx/common/ad_data_out.v
View File

@ -123,7 +123,7 @@ module ad_data_out #(
endgenerate endgenerate
// odelay // odelay
generate generate
if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)

2
projects/ad9208_dual_ebz/common/dual_ad9208_bd.tcl
View File

@ -84,7 +84,7 @@ ad_ip_parameter axi_ad9208_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9208_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad9208_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad9208_dma CONFIG.DMA_LENGTH_WIDTH 24 ad_ip_parameter axi_ad9208_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_ad9208_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9208_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9208_dma CONFIG.MAX_BYTES_PER_BURST 4096 ad_ip_parameter axi_ad9208_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_ad9208_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad9208_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9208_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_ad9208_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
ad_ip_parameter axi_ad9208_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width ad_ip_parameter axi_ad9208_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width

8
projects/ad9208_dual_ebz/vcu118/system_constr.xdc
View File

@ -77,20 +77,20 @@ set_property -dict {PACKAGE_PIN AJ36 IOSTANDARD LVCMOS18} [get_ports hmc_sync_
create_clock -name rx_ref_clk_0 -period 1.33 [get_ports rx_ref_clk_0_p] create_clock -name rx_ref_clk_0 -period 1.33 [get_ports rx_ref_clk_0_p]
create_clock -name rx_ref_clk_1 -period 1.33 [get_ports rx_ref_clk_1_p] create_clock -name rx_ref_clk_1 -period 1.33 [get_ports rx_ref_clk_1_p]
# The Global clock is routed from the REFCLK1 of the dual_ad9208 board # The Global clock is routed from the REFCLK1 of the dual_ad9208 board
# since GLBLCLK0 and GLBLCLK1 are not connected to global clock capable pins. # since GLBLCLK0 and GLBLCLK1 are not connected to global clock capable pins.
create_clock -name global_clk_0 -period 2.66 [get_ports glbl_clk_0_p] create_clock -name global_clk_0 -period 2.66 [get_ports glbl_clk_0_p]
# Constraint SYSREFs # Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay, # Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Center-Aligned signal to REFCLK # and the SYSREF is a source synchronous Center-Aligned signal to REFCLK
set_input_delay -clock [get_clocks global_clk_0] \ set_input_delay -clock [get_clocks global_clk_0] \
[expr [get_property PERIOD [get_clocks global_clk_0]] / 2] \ [expr [get_property PERIOD [get_clocks global_clk_0]] / 2] \
[get_ports {rx_sysref_*}] [get_ports {rx_sysref_*}]
# Place the sysref capture FFs near Bank 43, they can't be placed into the IOB due pulse width violation. # Place the sysref capture FFs near Bank 43, they can't be placed into the IOB due pulse width violation.
# Creating the pblock prevents the tool from placing the FFs on another SLR and not closing timing. # Creating the pblock prevents the tool from placing the FFs on another SLR and not closing timing.
create_pblock pblock_sysref create_pblock pblock_sysref
resize_pblock pblock_sysref -add SLICE_X50Y254:SLICE_X50Y278 resize_pblock pblock_sysref -add SLICE_X50Y254:SLICE_X50Y278
add_cells_to_pblock pblock_sysref [get_cells \ add_cells_to_pblock pblock_sysref [get_cells \

130
projects/ad9739a_fmc/zc706/system_constr.xdc
View File

@ -1,72 +1,72 @@
# ad9739a # ad9739a
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[0]] ; ## FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[0]] ; ## FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[0]] ; ## FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[0]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[1]] ; ## FMC_LPC_LA15_P set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[1]] ; ## FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[1]] ; ## FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[1]] ; ## FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[2]] ; ## FMC_LPC_LA14_P set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[2]] ; ## FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[2]] ; ## FMC_LPC_LA14_N set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[2]] ; ## FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[3]] ; ## FMC_LPC_LA13_P set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[3]] ; ## FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[3]] ; ## FMC_LPC_LA13_N set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[3]] ; ## FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[4]] ; ## FMC_LPC_LA11_P set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[4]] ; ## FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[4]] ; ## FMC_LPC_LA11_N set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[4]] ; ## FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[5]] ; ## FMC_LPC_LA12_P set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[5]] ; ## FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[5]] ; ## FMC_LPC_LA12_N set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[5]] ; ## FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[6]] ; ## FMC_LPC_LA10_P set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[6]] ; ## FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[6]] ; ## FMC_LPC_LA10_N set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[6]] ; ## FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[7]] ; ## FMC_LPC_LA07_P set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[7]] ; ## FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[7]] ; ## FMC_LPC_LA07_N set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[7]] ; ## FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[8]] ; ## FMC_LPC_LA08_P set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[8]] ; ## FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[8]] ; ## FMC_LPC_LA08_N set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[8]] ; ## FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[9]] ; ## FMC_LPC_LA05_P set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[9]] ; ## FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[9]] ; ## FMC_LPC_LA05_N set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[9]] ; ## FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[10]] ; ## FMC_LPC_LA06_P set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[10]] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[10]] ; ## FMC_LPC_LA06_N set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[10]] ; ## FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[11]] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[11]] ; ## FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[11]] ; ## FMC_LPC_LA03_N set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[11]] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[12]] ; ## FMC_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[12]] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[12]] ; ## FMC_LPC_LA01_CC_N set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[12]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[13]] ; ## FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_p[13]] ; ## FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[13]] ; ## FMC_LPC_LA02_N set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25} [get_ports dac_data_out_a_n[13]] ; ## FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[0]] ; ## FMC_LPC_LA30_P set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[0]] ; ## FMC_LPC_LA30_P
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[0]] ; ## FMC_LPC_LA30_N set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[0]] ; ## FMC_LPC_LA30_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[1]] ; ## FMC_LPC_LA31_P set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[1]] ; ## FMC_LPC_LA31_P
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[1]] ; ## FMC_LPC_LA31_N set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[1]] ; ## FMC_LPC_LA31_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[2]] ; ## FMC_LPC_LA28_P set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[2]] ; ## FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[2]] ; ## FMC_LPC_LA28_N set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[2]] ; ## FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[3]] ; ## FMC_LPC_LA29_P set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[3]] ; ## FMC_LPC_LA29_P
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[3]] ; ## FMC_LPC_LA29_N set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[3]] ; ## FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[4]] ; ## FMC_LPC_LA24_P set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[4]] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[4]] ; ## FMC_LPC_LA24_N set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[4]] ; ## FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[5]] ; ## FMC_LPC_LA25_P set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[5]] ; ## FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[5]] ; ## FMC_LPC_LA25_N set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[5]] ; ## FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[6]] ; ## FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[6]] ; ## FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[6]] ; ## FMC_LPC_LA27_N set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[6]] ; ## FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[7]] ; ## FMC_LPC_LA21_P set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[7]] ; ## FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[7]] ; ## FMC_LPC_LA21_N set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[7]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[8]] ; ## FMC_LPC_LA22_P set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[8]] ; ## FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[8]] ; ## FMC_LPC_LA22_N set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[8]] ; ## FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[9]] ; ## FMC_LPC_LA23_P set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[9]] ; ## FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[9]] ; ## FMC_LPC_LA23_N set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[9]] ; ## FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[10]] ; ## FMC_LPC_LA18_CC_P set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[10]] ; ## FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[10]] ; ## FMC_LPC_LA18_CC_N set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[10]] ; ## FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[11]] ; ## FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[11]] ; ## FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[11]] ; ## FMC_LPC_LA20_N set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[11]] ; ## FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[12]] ; ## FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[12]] ; ## FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[12]] ; ## FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[12]] ; ## FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[13]] ; ## FMC_LPC_LA09_P set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_p[13]] ; ## FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[13]] ; ## FMC_LPC_LA09_N set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports dac_data_out_b_n[13]] ; ## FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## FMC_LPC_LA17_CC_P set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## FMC_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## FMC_LPC_LA32_P set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## FMC_LPC_LA32_P
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## FMC_LPC_LA32_N set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## FMC_LPC_LA33_P set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## FMC_LPC_LA33_N set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## FMC_LPC_LA33_N
# clocks # clocks

16
projects/adrv9009/zc706/system_constr.xdc
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@ -27,12 +27,12 @@ set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_syn
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer) set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer)
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G06 FMC_HPC_LA00_CC_P set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G07 FMC_HPC_LA00_CC_N set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_p] ; ## H28 FMC_HPC_LA24_P set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_p] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_n] ; ## H29 FMC_HPC_LA24_N set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_n] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_p] ; ## D08 FMC_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_n] ; ## D09 FMC_HPC_LA01_CC_N set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adrv9009] ; ## D14 FMC_HPC_LA09_P set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adrv9009] ; ## D14 FMC_HPC_LA09_P
@ -46,7 +46,7 @@ set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports adrv9009
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports adrv9009_tx2_enable] ; ## C18 FMC_HPC_LA14_P set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports adrv9009_tx2_enable] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx1_enable] ; ## D18 FMC_HPC_LA13_N set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx1_enable] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx2_enable] ; ## C19 FMC_HPC_LA14_N set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx2_enable] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adrv9009_test] ; ## H16 FMC_HPC_LA11_P set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adrv9009_test] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports adrv9009_reset_b] ; ## H10 FMC_HPC_LA04_P set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports adrv9009_reset_b] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpint] ; ## H11 FMC_HPC_LA04_N set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpint] ; ## H11 FMC_HPC_LA04_N
@ -63,10 +63,10 @@ set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports adrv9009
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_13] ; ## G16 FMC_HPC_LA12_N set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_13] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_14] ; ## G15 FMC_HPC_LA12_P set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_14] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_16] ; ## C11 FMC_HPC_LA06_N set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_16] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_17] ; ## C10 FMC_HPC_LA06_P set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_17] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_18] ; ## H17 FMC_HPC_LA11_N set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_18] ; ## H17 FMC_HPC_LA11_N

6
projects/adrv9009/zc706/system_top.v
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@ -56,7 +56,7 @@ output tx_data_p[0], SERDIN0+ A22 FMC_HPC_DP1_C2M_P AK6
output tx_data_n[0], SERDIN0- A23 FMC_HPC_DP1_C2M_N AK5 output tx_data_n[0], SERDIN0- A23 FMC_HPC_DP1_C2M_N AK5
output tx_data_p[1], SERDIN3+ A26 FMC_HPC_DP2_C2M_P AJ4 output tx_data_p[1], SERDIN3+ A26 FMC_HPC_DP2_C2M_P AJ4
output tx_data_n[1], SERDIN3- A27 FMC_HPC_DP2_C2M_N AJ3 output tx_data_n[1], SERDIN3- A27 FMC_HPC_DP2_C2M_N AJ3
output tx_data_p[2], SERDIN2+ C2 FMC_HPC_DP0_C2M_P AK10 output tx_data_p[2], SERDIN2+ C2 FMC_HPC_DP0_C2M_P AK10
output tx_data_n[2], SERDIN2- C3 FMC_HPC_DP0_C2M_N AK9 output tx_data_n[2], SERDIN2- C3 FMC_HPC_DP0_C2M_N AK9
output tx_data_p[3], SERDIN1+ A30 FMC_HPC_DP3_C2M_P AK2 output tx_data_p[3], SERDIN1+ A30 FMC_HPC_DP3_C2M_P AK2
output tx_data_n[3], SERDIN1- A31 FMC_HPC_DP3_C2M_N AK1 output tx_data_n[3], SERDIN1- A31 FMC_HPC_DP3_C2M_N AK1
@ -86,7 +86,7 @@ inout adrv9009_tx1_enable, TX1_ENABLE D17 FMC_HPC_LA13_P AA2
inout adrv9009_tx2_enable, TX2_ENABLE C18 FMC_HPC_LA14_P AC24 inout adrv9009_tx2_enable, TX2_ENABLE C18 FMC_HPC_LA14_P AC24
inout adrv9009_rx1_enable, RX1_ENABLE D18 FMC_HPC_LA13_N AA23 inout adrv9009_rx1_enable, RX1_ENABLE D18 FMC_HPC_LA13_N AA23
inout adrv9009_rx2_enable, RX2_ENABLE C19 FMC_HPC_LA14_N AD24 inout adrv9009_rx2_enable, RX2_ENABLE C19 FMC_HPC_LA14_N AD24
inout adrv9009_test, TEST H16 FMC_HPC_LA11_P AD23 inout adrv9009_test, TEST H16 FMC_HPC_LA11_P AD23
inout adrv9009_reset_b, RESETB H10 FMC_HPC_LA04_P AJ20 inout adrv9009_reset_b, RESETB H10 FMC_HPC_LA04_P AJ20
inout adrv9009_gpint, GP_INTERRUPT H11 FMC_HPC_LA04_N AK20 inout adrv9009_gpint, GP_INTERRUPT H11 FMC_HPC_LA04_N AK20
@ -104,7 +104,7 @@ inout adrv9009_gpio_10, GPIO_10 H23 FMC_HPC_LA19_N T25
inout adrv9009_gpio_11, GPIO_11 G21 FMC_HPC_LA20_P U25 inout adrv9009_gpio_11, GPIO_11 G21 FMC_HPC_LA20_P U25
inout adrv9009_gpio_12, GPIO_12 G22 FMC_HPC_LA20_N V26 inout adrv9009_gpio_12, GPIO_12 G22 FMC_HPC_LA20_N V26
inout adrv9009_gpio_13, GPIO_13 G16 FMC_HPC_LA12_N AF24 inout adrv9009_gpio_13, GPIO_13 G16 FMC_HPC_LA12_N AF24
inout adrv9009_gpio_14, GPIO_14 G15 FMC_HPC_LA12_P AF23 inout adrv9009_gpio_14, GPIO_14 G15 FMC_HPC_LA12_P AF23
inout adrv9009_gpio_15, GPIO_15 G24 FMC_HPC_LA22_P V27 inout adrv9009_gpio_15, GPIO_15 G24 FMC_HPC_LA22_P V27
inout adrv9009_gpio_16, GPIO_16 C11 FMC_HPC_LA06_N AH22 inout adrv9009_gpio_16, GPIO_16 C11 FMC_HPC_LA06_N AH22
inout adrv9009_gpio_17, GPIO_17 C10 FMC_HPC_LA06_P AG22 inout adrv9009_gpio_17, GPIO_17 C10 FMC_HPC_LA06_P AG22

2
projects/adrv9361z7035/common/adrv9361z7035_constr.xdc
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@ -84,7 +84,7 @@ set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get
## U1,E20,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N) ## U1,E20,PS_MIO29_501_USB0_DIR (usb- JX3,69,USB_OTG_N)
## U1,K19,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG) ## U1,K19,PS_MIO30_501_USB0_STP (usb- JX3,68,USB_VBUS_OTG)
## U1,E21,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN) ## U1,E21,PS_MIO31_501_USB0_NXT (usb- JX3,70,USB_OTG_CPEN)
## U1,K16,PS_MIO36_501_USB0_CLK ## U1,K16,PS_MIO36_501_USB0_CLK
## U1,K17,PS_MIO32_501_USB0_D0 ## U1,K17,PS_MIO32_501_USB0_D0
## U1,E22,PS_MIO33_501_USB0_D1 ## U1,E22,PS_MIO33_501_USB0_D1
## U1,J16,PS_MIO34_501_USB0_D2 ## U1,J16,PS_MIO34_501_USB0_D2

170
projects/adrv9361z7035/common/ccfmc_constr.xdc
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@ -11,69 +11,69 @@ set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync
# ethernet-1 (U1,B20,PS_MIO51_501_JX4,JX4,100,ETH1_RESETN) # ethernet-1 (U1,B20,PS_MIO51_501_JX4,JX4,100,ETH1_RESETN)
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports eth1_mdc] ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,ETH1_MDC set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports eth1_mdc] ; ## U1,B10,IO_L16_34_JX4_P,JX4,58,ETH1_MDC
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports eth1_mdio] ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,ETH1_MDIO set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports eth1_mdio] ; ## U1,A10,IO_L16_34_JX4_N,JX4,60,ETH1_MDIO
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk] ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,ETH1_RX_CLK set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxclk] ; ## U1,G7,IO_L12_MRCC_34_JX4_P,JX4,46,ETH1_RX_CLK
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl] ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,ETH1_RX_CTRL set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxctl] ; ## U1,F7,IO_L12_MRCC_34_JX4_N,JX4,48,ETH1_RX_CTRL
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,ETH1_RXD0 set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[0]] ; ## U1,E6,IO_L10_34_JX4_P,JX4,42,ETH1_RXD0
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]] ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,ETH1_RXD1 set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[1]] ; ## U1,D5,IO_L10_34_JX4_N,JX4,44,ETH1_RXD1
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]] ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,ETH1_RXD2 set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[2]] ; ## U1,F8,IO_L11_SRCC_34_JX4_P,JX4,45,ETH1_RXD2
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]] ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,ETH1_RXD3 set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_rxdata[3]] ; ## U1,E7,IO_L11_SRCC_34_JX4_N,JX4,47,ETH1_RXD3
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk] ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,ETH1_TX_CLK set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txclk] ; ## U1,C8,IO_L13_MRCC_34_JX4_P,JX4,51,ETH1_TX_CLK
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl] ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,ETH1_TX_CTRL set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txctl] ; ## U1,C7,IO_L13_MRCC_34_JX4_N,JX4,53,ETH1_TX_CTRL
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]] ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,ETH1_TXD0 set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[0]] ; ## U1,D6,IO_L14_SRCC_34_JX4_P,JX4,52,ETH1_TXD0
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]] ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,ETH1_TXD1 set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[1]] ; ## U1,C6,IO_L14_SRCC_34_JX4_N,JX4,54,ETH1_TXD1
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]] ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,ETH1_TXD2 set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[2]] ; ## U1,C9,IO_L15_34_JX4_P,JX4,57,ETH1_TXD2
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]] ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,ETH1_TXD3 set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports eth1_rgmii_txdata[3]] ; ## U1,B9,IO_L15_34_JX4_N,JX4,59,ETH1_TXD3
# hdmi # hdmi
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,HDMI_CLK set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] ; ## U1,L3,IO_L11_SRCC_33_JX1_P,JX1,74,HDMI_CLK
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_vsync] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,HDMI_VSYNC set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_vsync] ; ## U1,D4,IO_L02_33_JX1_P,JX1,41,HDMI_VSYNC
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_hsync] ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,HDMI_HSYNC set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_hsync] ; ## U1,D3,IO_L02_33_JX1_N,JX1,43,HDMI_HSYNC
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data_e] ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,HDMI_DE set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data_e] ; ## U1,K3,IO_L11_SRCC_33_JX1_N,JX1,76,HDMI_DE
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[0]] ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,HDMI_D20 set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[0]] ; ## U1,G2,IO_L03_33_JX1_P,JX1,42,HDMI_D20
set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[1]] ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,HDMI_D21 set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[1]] ; ## U1,F2,IO_L03_33_JX1_N,JX1,44,HDMI_D21
set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[2]] ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,HDMI_D22 set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[2]] ; ## U1,D1,IO_L04_33_JX1_P,JX1,47,HDMI_D22
set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[3]] ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,HDMI_D23 set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[3]] ; ## U1,C1,IO_L04_33_JX1_N,JX1,49,HDMI_D23
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[4]] ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,HDMI_D24 set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[4]] ; ## U1,E2,IO_L05_33_JX1_P,JX1,54,HDMI_D24
set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[5]] ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,HDMI_D25 set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[5]] ; ## U1,E1,IO_L05_33_JX1_N,JX1,56,HDMI_D25
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[6]] ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,HDMI_D26 set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[6]] ; ## U1,F3,IO_L06_33_JX1_P,JX1,61,HDMI_D26
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[7]] ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,HDMI_D27 set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[7]] ; ## U1,E3,IO_L06_33_JX1_N,JX1,63,HDMI_D27
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[8]] ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,HDMI_D28 set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[8]] ; ## U1,J1,IO_L07_33_JX1_P,JX1,62,HDMI_D28
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[9]] ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,HDMI_D29 set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[9]] ; ## U1,H1,IO_L07_33_JX1_N,JX1,64,HDMI_D29
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[10]] ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,HDMI_D30 set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[10]] ; ## U1,H4,IO_L08_33_JX1_P,JX1,67,HDMI_D30
set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[11]] ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,HDMI_D31 set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[11]] ; ## U1,H3,IO_L08_33_JX1_N,JX1,69,HDMI_D31
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[12]] ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,HDMI_D32 set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[12]] ; ## U1,K2,IO_L09_33_JX1_P,JX1,68,HDMI_D32
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[13]] ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,HDMI_D33 set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[13]] ; ## U1,K1,IO_L09_33_JX1_N,JX1,70,HDMI_D33
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[14]] ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,HDMI_D34 set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[14]] ; ## U1,H2,IO_L10_33_JX1_P,JX1,73,HDMI_D34
set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[15]] ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,HDMI_D35 set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS18 IOB TRUE} [get_ports hdmi_data[15]] ; ## U1,G1,IO_L10_33_JX1_N,JX1,75,HDMI_D35
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports hdmi_pd] ; ## U1,L9,IO_00_33_JX1,JX1,9,HDMI_PD set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports hdmi_pd] ; ## U1,L9,IO_00_33_JX1,JX1,9,HDMI_PD
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports hdmi_intn] ; ## U1,N8,IO_25_33_JX1,JX1,10,HDMI_INTN set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports hdmi_intn] ; ## U1,N8,IO_25_33_JX1,JX1,10,HDMI_INTN
# hdmi-spdif # hdmi-spdif
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports spdif] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,HDMI_SPDIF set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS18} [get_ports spdif] ; ## U1,G4,IO_L01_33_JX1_P,JX1,35,HDMI_SPDIF
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports spdif_in] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,HDMI_SPDIF_OUT set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports spdif_in] ; ## U1,F4,IO_L01_33_JX1_N,JX1,37,HDMI_SPDIF_OUT
# audio # audio
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports i2s_mclk] ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,I2S_MCLK set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports i2s_mclk] ; ## U1,J8,IO_L06_34_JX4_P,JX4,32,I2S_MCLK
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports i2s_bclk] ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,I2S_BCLK set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports i2s_bclk] ; ## U1,H8,IO_L06_34_JX4_N,JX4,34,I2S_BCLK
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk] ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,I2S_LRCLK set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk] ; ## U1,F5,IO_L07_34_JX4_P,JX4,35,I2S_LRCLK
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out] ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,I2S_SDATA_OUT set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out] ; ## U1,E5,IO_L07_34_JX4_N,JX4,37,I2S_SDATA_OUT
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in] ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,I2S_SDATA_IN set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in] ; ## U1,D9,IO_L08_34_JX4_P,JX4,36,I2S_SDATA_IN
# ad9517 # ad9517
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9517_csn] ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,PMOD1_D3 set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9517_csn] ; ## U1,B4,IO_L20_34_JX4_N,JX4,76,PMOD1_D3
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9517_clk] ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,PMOD1_D0 set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9517_clk] ; ## U1,C4,IO_L19_34_JX4_P,JX4,73,PMOD1_D0
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9517_mosi] ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,PMOD1_D1 set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9517_mosi] ; ## U1,C3,IO_L19_34_JX4_N,JX4,75,PMOD1_D1
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9517_miso] ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,PMOD1_D2 set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9517_miso] ; ## U1,B5,IO_L20_34_JX4_P,JX4,74,PMOD1_D2
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9517_pdn] ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,PMOD1_D4 set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9517_pdn] ; ## U1,B6,IO_L21_34_JX4_P,JX4,77,PMOD1_D4
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel] ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,PMOD1_D5 set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9517_ref_sel] ; ## U1,A5,IO_L21_34_JX4_N,JX4,79,PMOD1_D5
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9517_ld] ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,PMOD1_D6 set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9517_ld] ; ## U1,A4,IO_L22_34_JX4_P,JX4,78,PMOD1_D6
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9517_status] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,PMOD1_D7 set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9517_status] ; ## U1,A3,IO_L22_34_JX4_N,JX4,80,PMOD1_D7
# clocks # clocks
@ -92,42 +92,42 @@ set_property IODELAY_GROUP gmii2rgmii_iodelay_group\
# fan control/sense # fan control/sense
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports fan_pwm] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,FAN_PWM set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports fan_pwm] ; ## U1,B7,IO_L18_34_JX4_P,JX4,68,FAN_PWM
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports fan_tach] ; ## U1,A7,IO_L18_34_JX4_N,JX4,70,FAN_TACH set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports fan_tach] ; ## U1,A7,IO_L18_34_JX4_N,JX4,70,FAN_TACH
## led, push buttons, dip switches ## led, push buttons, dip switches
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0 set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## U1,J3,IO_L12_MRCC_33_JX1_N,JX1,83,PB_GPIO_0
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1 set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## U1,D8,IO_L08_34_JX4_N,JX4,38,PB_GPIO_1
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2 set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## U1,F9,IO_L09_34_JX4_P,JX4,41,PB_GPIO_2
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3 set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## U1,E8,IO_L09_34_JX4_N,JX4,43,PB_GPIO_3
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0 set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## U1,A8,IO_L17_34_JX4_N,JX4,69,LED_GPIO_0
set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1 set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports gpio_bd[5]] ; ## U1,W14,IO_00_12_JX4,JX4,14,LED_GPIO_1
set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2 set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## U1,W17,IO_25_12_JX4,JX4,16,LED_GPIO_2
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3 set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## U1,Y16,IO_L23_12_JX2_P,JX2,97,LED_GPIO_3
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0 set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[8]] ; ## U1,Y15,IO_L23_12_JX2_N,JX2,99,DIP_GPIO_0
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1 set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## U1,W16,IO_L24_12_JX4_P,JX4,13,DIP_GPIO_1
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2 set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[10]] ; ## U1,W15,IO_L24_12_JX4_N,JX4,15,DIP_GPIO_2
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3 set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## U1,V19,IO_00_13_JX2,JX2,13,DIP_GPIO_3
## orphans (ps7- gpio) ## orphans (ps7- gpio)
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## U1,V18,IO_25_13_JX2,JX2,14,FMC_PRSNT set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## U1,V18,IO_25_13_JX2,JX2,14,FMC_PRSNT
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,PMOD0_D1,R103,1 set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## U1,AC19,IO_L21_13_JX2_N,JX2,69,PMOD0_D1,R103,1
set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,SFP_GPIO_0 set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## U1,Y17,IO_L19_12_JX2_P,JX2,88,SFP_GPIO_0
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,SFP_GPIO_1 set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]] ; ## U1,AA17,IO_L19_12_JX2_N,JX2,90,SFP_GPIO_1
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,SFP_GPIO_2 set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]] ; ## U1,AB17,IO_L20_12_JX2_P,JX2,87,SFP_GPIO_2
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,SFP_GPIO_3 set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]] ; ## U1,AB16,IO_L20_12_JX2_N,JX2,89,SFP_GPIO_3
set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,SFP_GPIO_4 set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]] ; ## U1,AC17,IO_L21_12_JX2_P,JX2,93,SFP_GPIO_4
set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[19]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,SFP_GPIO_5 set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[19]] ; ## U1,AC16,IO_L21_12_JX2_N,JX2,95,SFP_GPIO_5
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[20]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,SFP_GPIO_6 set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[20]] ; ## U1,AA15,IO_L22_12_JX2_P,JX2,94,SFP_GPIO_6
# unused io (clocks & gt) # unused io (clocks & gt)
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,FMC_CLK0_M2C_P set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_p] ; ## U1,AC14,IO_L13_MRCC_12_JX3_P,JX3,91,FMC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,FMC_CLK0_M2C_N set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_0_n] ; ## U1,AD14,IO_L13_MRCC_12_JX3_N,JX3,93,FMC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,FMC_CLK1_M2C_P set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## U1,AD20,IO_L13_MRCC_13_JX2_P,JX2,41,FMC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,FMC_CLK1_M2C_N set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## U1,AD21,IO_L13_MRCC_13_JX2_N,JX2,43,FMC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN R6} [get_ports gt_ref_clk_0_p] ; ## U1,R6,UNNAMED_7_CAP_I123_N2,JX1,87,MGTREFCLK0_112_JX1_P set_property -dict {PACKAGE_PIN R6} [get_ports gt_ref_clk_0_p] ; ## U1,R6,UNNAMED_7_CAP_I123_N2,JX1,87,MGTREFCLK0_112_JX1_P
set_property -dict {PACKAGE_PIN R5} [get_ports gt_ref_clk_0_n] ; ## U1,R5,UNNAMED_7_CAP_I125_N2,JX1,89,MGTREFCLK0_112_JX1_N set_property -dict {PACKAGE_PIN R5} [get_ports gt_ref_clk_0_n] ; ## U1,R5,UNNAMED_7_CAP_I125_N2,JX1,89,MGTREFCLK0_112_JX1_N
@ -223,13 +223,13 @@ set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[32
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,FMC_LA33_N,P2,G37 set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## U1,Y20,IO_L19_13_JX2_N,JX2,63,FMC_LA33_N,P2,G37
## loopback (regular io- pmod) ## loopback (regular io- pmod)
## U1,C24,PS_MIO15_500_JX4,JX4,85,PMOD_MIO_D0 ## U1,C24,PS_MIO15_500_JX4,JX4,85,PMOD_MIO_D0
## U1,A25,PS_MIO10_500_JX4,JX4,87,PMOD_MIO_D1 ## U1,A25,PS_MIO10_500_JX4,JX4,87,PMOD_MIO_D1
## U1,B26,PS_MIO11_500_JX4,JX4,88,PMOD_MIO_D3 ## U1,B26,PS_MIO11_500_JX4,JX4,88,PMOD_MIO_D3
## U1,B25,PS_MIO13_500_JX4,JX4,91,PMOD_MIO_D4 ## U1,B25,PS_MIO13_500_JX4,JX4,91,PMOD_MIO_D4
## U1,D23,PS_MIO14_500_JX4,JX4,93,PMOD_MIO_D5 ## U1,D23,PS_MIO14_500_JX4,JX4,93,PMOD_MIO_D5
## U1,E17,PS_MIO46_501_JX4,JX4,92,PMOD_MIO_D6 ## U1,E17,PS_MIO46_501_JX4,JX4,92,PMOD_MIO_D6
## U1,B19,PS_MIO47_501_JX4,JX4,94,PMOD_MIO_D7 ## U1,B19,PS_MIO47_501_JX4,JX4,94,PMOD_MIO_D7
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,PMOD0_D0,R95,1 set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## U1,AC18,IO_L21_13_JX2_P,JX2,67,PMOD0_D0,R95,1
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,PMOD0_D2,R96,1 set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## U1,AA19,IO_L22_13_JX2_P,JX2,68,PMOD0_D2,R96,1
@ -274,4 +274,4 @@ set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports gp_in[50
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,CAM_SPI_EN,P9,B14 set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gp_in[51]] ; ## U1,N7,IO_L23_33_JX1_P,JX1,30,CAM_SPI_EN,P9,B14
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,CAM_SPI_CLK,P9,B12 set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS18} [get_ports gp_in[52]] ; ## U1,N6,IO_L23_33_JX1_N,JX1,32,CAM_SPI_CLK,P9,B12
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,CAM_REFCLK,P9,A2 set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports gp_in[53]] ; ## U1,J4,IO_L12_MRCC_33_JX1_P,JX1,81,CAM_REFCLK,P9,A2

6
projects/adrv9364z7020/ccbox_lvds/system_project.tcl
View File

@ -1,7 +1,7 @@
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
set p_device "xc7z020clg400-1" set p_device "xc7z020clg400-1"
adi_project_xilinx adrv9364z7020_ccbox_lvds adi_project_xilinx adrv9364z7020_ccbox_lvds

8
projects/adrv9371x/a10soc/system_top.v
View File

@ -64,7 +64,7 @@ module system_top (
input hps_ddr_rzq, input hps_ddr_rzq,
// pl-ddr4 // pl-ddr4
input sys_ddr_ref_clk, input sys_ddr_ref_clk,
output [ 0:0] sys_ddr_clk_p, output [ 0:0] sys_ddr_clk_p,
output [ 0:0] sys_ddr_clk_n, output [ 0:0] sys_ddr_clk_n,
@ -122,7 +122,7 @@ module system_top (
// hps-gpio (max-v-u16) // hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio, inout [ 3:0] hps_gpio,
// gpio (max-v-u21) // gpio (max-v-u21)
input [ 7:0] gpio_bd_i, input [ 7:0] gpio_bd_i,
@ -148,7 +148,7 @@ module system_top (
output ad9371_test, output ad9371_test,
output ad9371_reset_b, output ad9371_reset_b,
input ad9371_gpint, input ad9371_gpint,
inout [ 18:0] ad9371_gpio, inout [ 18:0] ad9371_gpio,
output spi_csn_ad9528, output spi_csn_ad9528,
@ -193,7 +193,7 @@ module system_top (
assign gpio_i[51:51] = ad9371_gpint; assign gpio_i[51:51] = ad9371_gpint;
assign gpio_i[50:32] = gpio_o[50:32]; assign gpio_i[50:32] = gpio_o[50:32];
// board stuff (max-v-u21) // board stuff (max-v-u21)
assign gpio_i[31:14] = gpio_o[31:14]; assign gpio_i[31:14] = gpio_o[31:14];

34
projects/adrv9371x/zc706/system_constr.xdc
View File

@ -46,25 +46,25 @@ set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports ad9371_t
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b] ; ## H10 FMC_HPC_LA04_P set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint] ; ## H11 FMC_HPC_LA04_N set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_00] ; ## H19 FMC_HPC_LA15_P set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_00] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_01] ; ## H20 FMC_HPC_LA15_N set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_01] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_02] ; ## G18 FMC_HPC_LA16_P set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_02] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_03] ; ## G19 FMC_HPC_LA16_N set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_03] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_04] ; ## H25 FMC_HPC_LA21_P set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_04] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_05] ; ## H26 FMC_HPC_LA21_N set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_05] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_17] ; ## G15 FMC_HPC_LA12_P (LVDS Pairs?) set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_17] ; ## G15 FMC_HPC_LA12_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_16] ; ## G16 FMC_HPC_LA12_N (LVDS Pairs?) set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_16] ; ## G16 FMC_HPC_LA12_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_18] ; ## D12 FMC_HPC_LA05_N set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9371_gpio_18] ; ## D12 FMC_HPC_LA05_N
# clocks # clocks

4
projects/arradio/c5soc/system_constr.sdc
View File

@ -22,14 +22,14 @@ set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_dat
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}] set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}] set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}] set_input_delay -add_delay -rise -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[3]}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[4]}]
set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}] set_input_delay -add_delay -fall -max 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[5]}]
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}] set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_frame_in}]
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}] set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[0]}]
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}] set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[1]}]
set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}] set_input_delay -add_delay -fall -min 0.2 -clock {v_rx_clk} [get_ports {rx_data_in[2]}]

4
projects/common/a10soc/a10soc_system_assign.tcl
View File

@ -13,8 +13,8 @@ set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "FORCE ALL USE
set_location_assignment PIN_F25 -to hps_ddr_ref_clk set_location_assignment PIN_F25 -to hps_ddr_ref_clk
set_location_assignment PIN_G24 -to "hps_ddr_ref_clk(n)" set_location_assignment PIN_G24 -to "hps_ddr_ref_clk(n)"
set_location_assignment PIN_B20 -to hps_ddr_clk_p set_location_assignment PIN_B20 -to hps_ddr_clk_p
set_location_assignment PIN_B19 -to hps_ddr_clk_n set_location_assignment PIN_B19 -to hps_ddr_clk_n
set_location_assignment PIN_B26 -to hps_ddr_a[0] set_location_assignment PIN_B26 -to hps_ddr_a[0]
set_location_assignment PIN_C26 -to hps_ddr_a[1] set_location_assignment PIN_C26 -to hps_ddr_a[1]
set_location_assignment PIN_C22 -to hps_ddr_a[2] set_location_assignment PIN_C22 -to hps_ddr_a[2]

14
projects/common/kcu105/kcu105_system_constr.xdc
View File

@ -1,20 +1,20 @@
# constraints # constraints
set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst] set_property -dict {PACKAGE_PIN AN8 IOSTANDARD LVCMOS18} [get_ports sys_rst]
# uart # uart
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout] set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS18} [get_ports uart_sout]
set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sin] set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports uart_sin]
# ethernet (phy_rst_n automation cannot be used with axi_ethernet 7.0) # ethernet (phy_rst_n automation cannot be used with axi_ethernet 7.0)
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n] set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS18} [get_ports phy_rst_n]
# fan # fan
set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm] set_property -dict {PACKAGE_PIN AJ9 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
# sw/led # sw/led
@ -38,8 +38,8 @@ set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18 DRIVE 8} [get_port
# iic # iic
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl] set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda] set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports iic_sda]
# ddr # ddr

4
projects/common/kcu105/kcu105_system_lutram_constr.xdc
View File

@ -7,8 +7,8 @@
# Michael_Board=KCU105 SN=1280723c031 DV=N8F245_3_0_7 LOCs=2 # Michael_Board=KCU105 SN=1280723c031 DV=N8F245_3_0_7 LOCs=2
# #
################################################### ###################################################
# NOTE: Ensure that the following constraints are # NOTE: Ensure that the following constraints are
# in place for ALL Designs # in place for ALL Designs
################################################### ###################################################
set_property PROHIBIT true [get_bels {SLICE_X23Y295/*LUT}] set_property PROHIBIT true [get_bels {SLICE_X23Y295/*LUT}]
set_property PROHIBIT true [get_bels {SLICE_X29Y282/*LUT}] set_property PROHIBIT true [get_bels {SLICE_X29Y282/*LUT}]

34
projects/common/vc707/vc707_system_constr.xdc
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@ -18,7 +18,7 @@ set_property PACKAGE_PIN AM7 [get_ports sgmii_rxn]
set_property PACKAGE_PIN AH8 [get_ports mgt_clk_p] set_property PACKAGE_PIN AH8 [get_ports mgt_clk_p]
set_property PACKAGE_PIN AH7 [get_ports mgt_clk_n] set_property PACKAGE_PIN AH7 [get_ports mgt_clk_n]
# Define the 125 MHz SGMII clock # Define the 125 MHz SGMII clock
create_clock -name mgt_clk -period 8.00 [get_ports mgt_clk_p] create_clock -name mgt_clk -period 8.00 [get_ports mgt_clk_p]
set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18} [get_ports phy_rstn] set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18} [get_ports phy_rstn]
@ -38,26 +38,26 @@ set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm
# lcd # lcd
set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[6]] ; ## lcd_e set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[6]] ; ## lcd_e
set_property -dict {PACKAGE_PIN AN41 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[5]] ; ## lcd_rs set_property -dict {PACKAGE_PIN AN41 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[5]] ; ## lcd_rs
set_property -dict {PACKAGE_PIN AR42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[4]] ; ## lcd_rw set_property -dict {PACKAGE_PIN AR42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[4]] ; ## lcd_rw
set_property -dict {PACKAGE_PIN AN40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[3]] ; ## lcd_db[7] set_property -dict {PACKAGE_PIN AN40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[3]] ; ## lcd_db[7]
set_property -dict {PACKAGE_PIN AR39 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[2]] ; ## lcd_db[6] set_property -dict {PACKAGE_PIN AR39 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[2]] ; ## lcd_db[6]
set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[1]] ; ## lcd_db[5] set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[1]] ; ## lcd_db[5]
set_property -dict {PACKAGE_PIN AT42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[0]] ; ## lcd_db[4] set_property -dict {PACKAGE_PIN AT42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[0]] ; ## lcd_db[4]
set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0 set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0
set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1 set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1
set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2 set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2
set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3 set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3
set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_DIP_SW4 set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_DIP_SW4
set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_DIP_SW5 set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_DIP_SW5
set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_DIP_SW6 set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_DIP_SW6
set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_DIP_SW7 set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_DIP_SW7
set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## GPIO_SW_N set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## GPIO_SW_N
set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## GPIO_SW_E set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## GPIO_SW_E
set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## GPIO_SW_S set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## GPIO_SW_S
set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## GPIO_SW_W set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## GPIO_SW_W
set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## GPIO_SW_C set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## GPIO_SW_C
set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## GPIO_LED_0_LS set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## GPIO_LED_0_LS
set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## GPIO_LED_1_LS set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## GPIO_LED_1_LS
set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## GPIO_LED_2_LS set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## GPIO_LED_2_LS

4
projects/daq2/a10soc/system_top.v
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@ -122,7 +122,7 @@ module system_top (
// hps-gpio (max-v-u16) // hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio, inout [ 3:0] hps_gpio,
// gpio (max-v-u21) // gpio (max-v-u21)
input [ 7:0] gpio_bd_i, input [ 7:0] gpio_bd_i,
@ -210,7 +210,7 @@ module system_top (
assign gpio_i[35:35] = adc_fda; assign gpio_i[35:35] = adc_fda;
assign gpio_i[34:34] = dac_irq; assign gpio_i[34:34] = dac_irq;
assign gpio_i[33:32] = clkd_status; assign gpio_i[33:32] = clkd_status;
// board stuff (max-v-u21) // board stuff (max-v-u21)
assign gpio_i[31:12] = gpio_o[31:12]; assign gpio_i[31:12] = gpio_o[31:12];

4
projects/daq2/kcu105/system_constr.xdc
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@ -33,8 +33,8 @@ set_property -dict {PACKAGE_PIN E10 IOSTANDARD LVCMOS18} [get_ports dac_irq]
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_p] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports trig_n] ; ## H14 FMC_HPC_LA07_N
# clocks # clocks

40
projects/fmcadc5/vc707/system_constr.xdc
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@ -22,30 +22,30 @@ set_property -dict {PACKAGE_PIN C5 } [get_ports rx_data_0_n[7]]
set_property -dict {PACKAGE_PIN K8 } [get_ports rx_ref_clk_1_p] ; ## D04 FMC2_HPC_GBTCLK0_M2C_P set_property -dict {PACKAGE_PIN K8 } [get_ports rx_ref_clk_1_p] ; ## D04 FMC2_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN K7 } [get_ports rx_ref_clk_1_n] ; ## D05 FMC2_HPC_GBTCLK0_M2C_N set_property -dict {PACKAGE_PIN K7 } [get_ports rx_ref_clk_1_n] ; ## D05 FMC2_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN V4 } [get_ports rx_data_1_p[0]] ; ## A18 FMC2_HPC_DP5_M2C_P set_property -dict {PACKAGE_PIN V4 } [get_ports rx_data_1_p[0]] ; ## A18 FMC2_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN V3 } [get_ports rx_data_1_n[0]] ; ## A19 FMC2_HPC_DP5_M2C_N set_property -dict {PACKAGE_PIN V3 } [get_ports rx_data_1_n[0]] ; ## A19 FMC2_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN U6 } [get_ports rx_data_1_p[1]] ; ## B16 FMC2_HPC_DP6_M2C_P set_property -dict {PACKAGE_PIN U6 } [get_ports rx_data_1_p[1]] ; ## B16 FMC2_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN U5 } [get_ports rx_data_1_n[1]] ; ## B17 FMC2_HPC_DP6_M2C_N set_property -dict {PACKAGE_PIN U5 } [get_ports rx_data_1_n[1]] ; ## B17 FMC2_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN W6 } [get_ports rx_data_1_p[2]] ; ## A14 FMC2_HPC_DP4_M2C_P set_property -dict {PACKAGE_PIN W6 } [get_ports rx_data_1_p[2]] ; ## A14 FMC2_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN W5 } [get_ports rx_data_1_n[2]] ; ## A15 FMC2_HPC_DP4_M2C_N set_property -dict {PACKAGE_PIN W5 } [get_ports rx_data_1_n[2]] ; ## A15 FMC2_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN R6 } [get_ports rx_data_1_p[3]] ; ## B12 FMC2_HPC_DP7_M2C_P set_property -dict {PACKAGE_PIN R6 } [get_ports rx_data_1_p[3]] ; ## B12 FMC2_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN R5 } [get_ports rx_data_1_n[3]] ; ## B13 FMC2_HPC_DP7_M2C_N set_property -dict {PACKAGE_PIN R5 } [get_ports rx_data_1_n[3]] ; ## B13 FMC2_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN J6 } [get_ports rx_data_1_p[4]] ; ## A10 FMC2_HPC_DP3_M2C_P set_property -dict {PACKAGE_PIN J6 } [get_ports rx_data_1_p[4]] ; ## A10 FMC2_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN J5 } [get_ports rx_data_1_n[4]] ; ## A11 FMC2_HPC_DP3_M2C_N set_property -dict {PACKAGE_PIN J5 } [get_ports rx_data_1_n[4]] ; ## A11 FMC2_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN L6 } [get_ports rx_data_1_p[5]] ; ## A06 FMC2_HPC_DP2_M2C_P set_property -dict {PACKAGE_PIN L6 } [get_ports rx_data_1_p[5]] ; ## A06 FMC2_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN L5 } [get_ports rx_data_1_n[5]] ; ## A07 FMC2_HPC_DP2_M2C_N set_property -dict {PACKAGE_PIN L5 } [get_ports rx_data_1_n[5]] ; ## A07 FMC2_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN P8 } [get_ports rx_data_1_p[6]] ; ## C06 FMC2_HPC_DP0_M2C_P set_property -dict {PACKAGE_PIN P8 } [get_ports rx_data_1_p[6]] ; ## C06 FMC2_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN P7 } [get_ports rx_data_1_n[6]] ; ## C07 FMC2_HPC_DP0_M2C_N set_property -dict {PACKAGE_PIN P7 } [get_ports rx_data_1_n[6]] ; ## C07 FMC2_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN N6 } [get_ports rx_data_1_p[7]] ; ## A02 FMC2_HPC_DP1_M2C_P set_property -dict {PACKAGE_PIN N6 } [get_ports rx_data_1_p[7]] ; ## A02 FMC2_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN N5 } [get_ports rx_data_1_n[7]] ; ## A03 FMC2_HPC_DP1_M2C_N set_property -dict {PACKAGE_PIN N5 } [get_ports rx_data_1_n[7]] ; ## A03 FMC2_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS} [get_ports rx_sysref_p] ; ## G06 FMC1_HPC_LA00_CC_P set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS} [get_ports rx_sysref_p] ; ## G06 FMC1_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS} [get_ports rx_sysref_n] ; ## G07 FMC1_HPC_LA00_CC_N set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS} [get_ports rx_sysref_n] ; ## G07 FMC1_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS} [get_ports rx_sync_0_p] ; ## D08 FMC1_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS} [get_ports rx_sync_0_p] ; ## D08 FMC1_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS} [get_ports rx_sync_0_n] ; ## D09 FMC1_HPC_LA01_CC_N set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS} [get_ports rx_sync_0_n] ; ## D09 FMC1_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS} [get_ports rx_sync_1_p] ; ## H07 FMC1_HPC_LA02_P set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS} [get_ports rx_sync_1_p] ; ## H07 FMC1_HPC_LA02_P
set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS} [get_ports rx_sync_1_n] ; ## H08 FMC1_HPC_LA02_N set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS} [get_ports rx_sync_1_n] ; ## H08 FMC1_HPC_LA02_N
set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_csn_0] ; ## D11 FMC1_HPC_LA05_P set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_csn_0] ; ## D11 FMC1_HPC_LA05_P
set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_csn_1] ; ## D12 FMC1_HPC_LA05_N set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_csn_1] ; ## D12 FMC1_HPC_LA05_N

130
projects/fmcomms5/zc702/system_constr.xdc
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@ -1,43 +1,43 @@
# constraints # constraints
# ad9361 master # ad9361 master
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC1_LPC_LA17_CC_P set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC1_LPC_LA17_CC_N set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC1_LPC_LA17_CC_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC1_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC1_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC1_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC1_LPC_LA01_CC_N set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC1_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC1_LPC_LA02_P set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC1_LPC_LA02_N set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC1_LPC_LA03_P set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC1_LPC_LA03_N set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC1_LPC_LA04_P set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC1_LPC_LA04_N set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC1_LPC_LA05_P set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC1_LPC_LA05_N set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC1_LPC_LA06_P set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC1_LPC_LA06_N set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC1_LPC_LA07_P set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC1_LPC_LA07_N set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_p] ; ## G12 FMC1_LPC_LA08_P set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_p] ; ## G12 FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_n] ; ## G13 FMC1_LPC_LA08_N set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_n] ; ## G13 FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_p] ; ## D14 FMC1_LPC_LA09_P set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_p] ; ## D14 FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_n] ; ## D15 FMC1_LPC_LA09_N set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_n] ; ## D15 FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC1_LPC_LA10_P set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC1_LPC_LA10_N set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC1_LPC_LA11_P set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC1_LPC_LA11_N set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC1_LPC_LA12_P set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC1_LPC_LA12_N set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC1_LPC_LA13_P set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC1_LPC_LA13_N set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC1_LPC_LA14_P set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC1_LPC_LA14_N set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC1_LPC_LA15_P set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC1_LPC_LA15_N set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[0]] ; ## H22 FMC1_LPC_LA19_P set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[0]] ; ## H22 FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[1]] ; ## H23 FMC1_LPC_LA19_N set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[1]] ; ## H23 FMC1_LPC_LA19_N
@ -56,8 +56,8 @@ set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports mcs_syn
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC1_LPC_LA18_CC_N set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC1_LPC_LA16_P set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC1_LPC_LA16_N set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC1_LPC_LA16_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC1_LPC_LA27_P set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC1_LPC_LA27_N set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC1_LPC_LA26_P set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_2_0] ; ## D27 FMC1_LPC_LA26_N set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_2_0] ; ## D27 FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_rfen] ; ## H31 FMC1_LPC_LA28_P set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_rfen] ; ## H31 FMC1_LPC_LA28_P
@ -66,46 +66,46 @@ set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports gpio_ad
# spi # spi
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC1_LPC_LA29_P set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC1_LPC_LA29_N set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC1_LPC_LA30_P set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H35 FMC1_LPC_LA30_N set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H35 FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G34 FMC1_LPC_LA31_N set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G34 FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G33 FMC1_LPC_LA31_P set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G33 FMC1_LPC_LA31_P
# ad9361 slave # ad9361 slave
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G6 FMC2_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G6 FMC2_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G7 FMC2_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G7 FMC2_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D8 FMC2_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D8 FMC2_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D9 FMC2_LPC_LA01_CC_N set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D9 FMC2_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H7 FMC2_LPC_LA02_P set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H7 FMC2_LPC_LA02_P
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H8 FMC2_LPC_LA02_N set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H8 FMC2_LPC_LA02_N
set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G9 FMC2_LPC_LA03_P set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G9 FMC2_LPC_LA03_P
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC2_LPC_LA03_N set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC2_LPC_LA03_N
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC2_LPC_LA04_P set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC2_LPC_LA04_P
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC2_LPC_LA04_N set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC2_LPC_LA04_N
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC2_LPC_LA05_P set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC2_LPC_LA05_P
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC2_LPC_LA05_N set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC2_LPC_LA05_N
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC2_LPC_LA06_P set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC2_LPC_LA06_P
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC2_LPC_LA06_N set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC2_LPC_LA06_N
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC2_LPC_LA07_P set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC2_LPC_LA07_P
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC2_LPC_LA07_N set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC2_LPC_LA07_N
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_p] ; ## G12 FMC2_LPC_LA08_P set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_p] ; ## G12 FMC2_LPC_LA08_P
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_n] ; ## G13 FMC2_LPC_LA08_N set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_n] ; ## G13 FMC2_LPC_LA08_N
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_p] ; ## D14 FMC2_LPC_LA09_P set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_p] ; ## D14 FMC2_LPC_LA09_P
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_n] ; ## D15 FMC2_LPC_LA09_N set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_n] ; ## D15 FMC2_LPC_LA09_N
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC2_LPC_LA10_P set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC2_LPC_LA10_P
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC2_LPC_LA10_N set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC2_LPC_LA10_N
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC2_LPC_LA11_P set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC2_LPC_LA11_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC2_LPC_LA11_N set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC2_LPC_LA11_N
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC2_LPC_LA12_P set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC2_LPC_LA12_P
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC2_LPC_LA12_N set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC2_LPC_LA12_N
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC2_LPC_LA13_P set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC2_LPC_LA13_P
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC2_LPC_LA13_N set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC2_LPC_LA13_N
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC2_LPC_LA14_P set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC2_LPC_LA14_P
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC2_LPC_LA14_N set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC2_LPC_LA14_N
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC2_LPC_LA15_P set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC2_LPC_LA15_P
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC2_LPC_LA15_N set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC2_LPC_LA15_N
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[0]] ; ## H22 FMC2_LPC_LA19_P set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[0]] ; ## H22 FMC2_LPC_LA19_P
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[1]] ; ## H23 FMC2_LPC_LA19_N set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[1]] ; ## H23 FMC2_LPC_LA19_N

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projects/fmcomms5/zc706/system_constr.xdc
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@ -1,132 +1,132 @@
# constraints # constraints
# ad9361 master # ad9361 master
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC_HPC_LA17_CC_P set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC_HPC_LA17_CC_P
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC_HPC_LA17_CC_N set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC_HPC_LA17_CC_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC_HPC_LA00_CC_P set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC_HPC_LA00_CC_N set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC_HPC_LA01_CC_N set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC_HPC_LA03_P set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_HPC_LA03_N set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_HPC_LA04_P set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_HPC_LA04_N set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_HPC_LA05_P set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_HPC_LA05_N set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_HPC_LA06_P set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_HPC_LA06_N set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_HPC_LA07_P set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_HPC_LA07_N set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_p] ; ## G12 FMC_HPC_LA08_P set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_p] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_n] ; ## G13 FMC_HPC_LA08_N set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_n] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_p] ; ## D14 FMC_HPC_LA09_P set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_p] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_n] ; ## D15 FMC_HPC_LA09_N set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_n] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC_HPC_LA10_P set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC_HPC_LA10_N set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC_HPC_LA11_P set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC_HPC_LA11_N set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC_HPC_LA12_P set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC_HPC_LA12_N set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC_HPC_LA13_P set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC_HPC_LA13_N set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC_HPC_LA14_P set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC_HPC_LA14_N set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC_HPC_LA15_P set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC_HPC_LA15_N set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[0]] ; ## H22 FMC_HPC_LA19_P set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[0]] ; ## H22 FMC_HPC_LA19_P
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[1]] ; ## H23 FMC_HPC_LA19_N set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[1]] ; ## H23 FMC_HPC_LA19_N
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[2]] ; ## G21 FMC_HPC_LA20_P set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[2]] ; ## G21 FMC_HPC_LA20_P
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[3]] ; ## G22 FMC_HPC_LA20_N set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[3]] ; ## G22 FMC_HPC_LA20_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[4]] ; ## H25 FMC_HPC_LA21_P set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[4]] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[5]] ; ## H26 FMC_HPC_LA21_N set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[5]] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[6]] ; ## G24 FMC_HPC_LA22_P set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[6]] ; ## G24 FMC_HPC_LA22_P
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[7]] ; ## G25 FMC_HPC_LA22_N set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[7]] ; ## G25 FMC_HPC_LA22_N
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[0]] ; ## D23 FMC_HPC_LA23_P set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[0]] ; ## D23 FMC_HPC_LA23_P
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[1]] ; ## D24 FMC_HPC_LA23_N set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[1]] ; ## D24 FMC_HPC_LA23_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[2]] ; ## H28 FMC_HPC_LA24_P set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[2]] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[3]] ; ## H29 FMC_HPC_LA24_N set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[3]] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC_LA25_P set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC_LA25_P
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports mcs_sync] ; ## C22 FMC_HPC_LA18_CC_P set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports mcs_sync] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC_LA18_CC_N set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC_HPC_LA16_P set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports enable_0] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC_HPC_LA16_N set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports txnrx_0] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC_LA27_P set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC_LA27_P
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC_LA27_N set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC_LA27_N
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC_LA26_P set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_2_0] ; ## D27 FMC_HPC_LA26_N set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_2_0] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_rfen] ; ## H31 FMC_HPC_LA28_P set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_rfen] ; ## H31 FMC_HPC_LA28_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_lock] ; ## H37 FMC_HPC_LA32_P set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_lock] ; ## H37 FMC_HPC_LA32_P
# spi # spi
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC_HPC_LA29_P set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC_HPC_LA29_P
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC_HPC_LA29_N set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC_HPC_LA29_N
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC_HPC_LA30_P set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC_HPC_LA30_P
set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H35 FMC_HPC_LA30_N set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H35 FMC_HPC_LA30_N
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G33 FMC_HPC_LA31_P set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G34 FMC_HPC_LA31_N set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G34 FMC_HPC_LA31_N
# ad9361 slave # ad9361 slave
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G06 FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G07 FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D08 FMC_LPC_LA01_CC_P set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D09 FMC_LPC_LA01_CC_N set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H07 FMC_LPC_LA02_P set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H08 FMC_LPC_LA02_N set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G09 FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC_LPC_LA03_N set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC_LPC_LA04_P set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC_LPC_LA04_N set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC_LPC_LA05_P set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC_LPC_LA05_N set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC_LPC_LA06_P set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC_LPC_LA06_N set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC_LPC_LA07_P set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC_LPC_LA07_N set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_p] ; ## G12 FMC_LPC_LA08_P set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_p] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_n] ; ## G13 FMC_LPC_LA08_N set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_n] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_p] ; ## D14 FMC_LPC_LA09_P set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_p] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_n] ; ## D15 FMC_LPC_LA09_N set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_n] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC_LPC_LA10_P set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC_LPC_LA10_N set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC_LPC_LA11_P set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC_LPC_LA11_N set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC_LPC_LA12_P set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC_LPC_LA12_N set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC_LPC_LA13_P set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC_LPC_LA13_N set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC_LPC_LA14_P set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC_LPC_LA14_N set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC_LPC_LA15_P set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[0]] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[0]] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[1]] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[1]] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[2]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[2]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[3]] ; ## G22 FMC_LPC_LA20_N set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[3]] ; ## G22 FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[4]] ; ## H25 FMC_LPC_LA21_P set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[4]] ; ## H25 FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[5]] ; ## H26 FMC_LPC_LA21_N set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[5]] ; ## H26 FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[6]] ; ## G24 FMC_LPC_LA22_P set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[6]] ; ## G24 FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[7]] ; ## G25 FMC_LPC_LA22_N set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[7]] ; ## G25 FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[0]] ; ## D23 FMC_LPC_LA23_P set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[0]] ; ## D23 FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[1]] ; ## D24 FMC_LPC_LA23_N set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[1]] ; ## D24 FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[2]] ; ## H28 FMC_LPC_LA24_P set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[2]] ; ## H28 FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_LPC_LA24_N set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_1] ; ## G27 FMC_LPC_LA25_P set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_1] ; ## G27 FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_1] ; ## G30 FMC_LPC_29_P set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_1] ; ## G30 FMC_LPC_29_P
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable_1] ; ## G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable_1] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx_1] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx_1] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_3_1] ; ## C26 FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_3_1] ; ## C26 FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_4_1] ; ## C27 FMC_LPC_LA27_N set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_4_1] ; ## C27 FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_3_1] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_3_1] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_4_1] ; ## D27 FMC_LPC_LA26_N set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_4_1] ; ## D27 FMC_LPC_LA26_N
# clocks # clocks