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axi_adrv9371/zc706: Constraints update 

From source *jesd_rstgen* is a false path for TX and RX_OS too.
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Istvan Csomortani 2016-11-11 10:35:09 +02:00
parent 85eac8c811
commit 7008c641b5
1 changed files with 2 additions and 0 deletions
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projects/adrv9371x/zc706/system_constr.xdc
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@ -75,4 +75,6 @@ create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/syste
create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]