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axi_hdmi_tx: Upgrade hdmi clipping process 

-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
main
AndreiGrozav 2016-04-12 22:01:07 +03:00
parent 21208ca208
commit 6fe41ebb08
3 changed files with 145 additions and 48 deletions
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8
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -202,6 +202,8 @@ module axi_hdmi_tx (
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire [31:0] hdmi_clip_max_s;
wire [31:0] hdmi_clip_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
@ -271,6 +273,8 @@ module axi_hdmi_tx (
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
@ -356,7 +360,9 @@ module axi_hdmi_tx (
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s));
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s));
// hdmi output clock

149
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -97,7 +97,9 @@ module axi_hdmi_tx_core (
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min);
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min);
// parameters
@ -164,6 +166,8 @@ module axi_hdmi_tx_core (
input [15:0] hdmi_vs_width;
input [15:0] hdmi_ve_max;
input [15:0] hdmi_ve_min;
input [23:0] hdmi_clip_max;
input [23:0] hdmi_clip_min;
// internal registers
@ -205,12 +209,24 @@ module axi_hdmi_tx_core (
reg hdmi_vsync_data_e = 'd0;
reg hdmi_data_e = 'd0;
reg [23:0] hdmi_data = 'd0;
reg hdmi_24_csc_hsync = 'd0;
reg hdmi_24_csc_vsync = 'd0;
reg hdmi_24_csc_hsync_data_e = 'd0;
reg hdmi_24_csc_vsync_data_e = 'd0;
reg hdmi_24_csc_data_e = 'd0;
reg [23:0] hdmi_24_csc_data = 'd0;
reg hdmi_24_hsync = 'd0;
reg hdmi_24_vsync = 'd0;
reg hdmi_24_hsync_data_e = 'd0;
reg hdmi_24_vsync_data_e = 'd0;
reg hdmi_24_data_e = 'd0;
reg [23:0] hdmi_24_data = 'd0;
reg hdmi_24_hsync_ss = 'd0;
reg hdmi_24_vsync_ss = 'd0;
reg hdmi_24_hsync_data_e_ss = 'd0;
reg hdmi_24_vsync_data_e_ss = 'd0;
reg hdmi_24_data_e_ss = 'd0;
reg [23:0] hdmi_24_data_ss = 'd0;
reg hdmi_16_hsync = 'd0;
reg hdmi_16_vsync = 'd0;
reg hdmi_16_hsync_data_e = 'd0;
@ -220,6 +236,12 @@ module axi_hdmi_tx_core (
reg hdmi_es_hs_de = 'd0;
reg hdmi_es_vs_de = 'd0;
reg [15:0] hdmi_es_data = 'd0;
reg [23:0] hdmi_clip_data = 'd0;
reg hdmi_clip_hs_de_d = 'd0;
reg hdmi_clip_vs_de_d = 'd0;
reg hdmi_clip_hs_d = 'd0;
reg hdmi_clip_vs_d = 'd0;
reg hdmi_clip_de_d = 'd0;
// internal wires
@ -245,6 +267,10 @@ module axi_hdmi_tx_core (
wire hdmi_ss_vsync_data_e_s;
wire hdmi_ss_data_e_s;
wire [15:0] hdmi_ss_data_s;
wire hdmi_clip_hs_de_s;
wire hdmi_clip_vs_de_s;
wire hdmi_clip_de_s;
wire [23:0] hdmi_clip_data_s;
wire hdmi_es_hs_de_s;
wire hdmi_es_vs_de_s;
wire hdmi_es_de_s;
@ -453,6 +479,68 @@ module axi_hdmi_tx_core (
endcase
end
// Color space conversion bypass (RGB/YCbCr)
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_csc_hsync <= hdmi_hsync;
hdmi_24_csc_vsync <= hdmi_vsync;
hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_csc_data_e <= hdmi_data_e;
hdmi_24_csc_data <= hdmi_data;
end else begin
hdmi_24_csc_hsync <= hdmi_csc_hsync_s;
hdmi_24_csc_vsync <= hdmi_csc_vsync_s;
hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_csc_data_e <= hdmi_csc_data_e_s;
hdmi_24_csc_data <= hdmi_csc_data_s;
end
end
// hdmi clipping
assign hdmi_clip_data_s = hdmi_24_csc_data;
always @(posedge hdmi_clk) begin
hdmi_clip_hs_d <= hdmi_24_csc_hsync;
hdmi_clip_vs_d <= hdmi_24_csc_vsync;
hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e;
hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e;
hdmi_clip_de_d <= hdmi_24_csc_data_e;
// Cr (red-diff) / red
if (hdmi_clip_data_s[23:16] > hdmi_clip_max[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_max[23:16];
end else if (hdmi_clip_data_s[23:16] < hdmi_clip_min[23:16]) begin
hdmi_clip_data[23:16] <= hdmi_clip_min[23:16];
end else begin
hdmi_clip_data[23:16] <= hdmi_clip_data_s[23:16];
end
// Y (luma) / green
if (hdmi_clip_data_s[15:8] > hdmi_clip_max[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_max[15:8];
end else if (hdmi_clip_data_s[15:8] < hdmi_clip_min[15:8]) begin
hdmi_clip_data[15:8] <= hdmi_clip_min[15:8];
end else begin
hdmi_clip_data[15:8] <= hdmi_clip_data_s[15:8];
end
// Cb (blue-diff) / blue
if (hdmi_clip_data_s[7:0] > hdmi_clip_max[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_max[7:0];
end else if (hdmi_clip_data_s[7:0] < hdmi_clip_min[7:0]) begin
hdmi_clip_data[7:0] <= hdmi_clip_min[7:0];
end else begin
hdmi_clip_data[7:0] <= hdmi_clip_data_s[7:0];
end
end
// hdmi csc 16, 24 and 36 outputs
assign hdmi_36_hsync = hdmi_24_hsync;
@ -463,21 +551,14 @@ module axi_hdmi_tx_core (
assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]};
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_hsync <= hdmi_hsync;
hdmi_24_vsync <= hdmi_vsync;
hdmi_24_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_data_e <= hdmi_data_e;
hdmi_24_data <= hdmi_data;
end else begin
hdmi_24_hsync <= hdmi_csc_hsync_s;
hdmi_24_vsync <= hdmi_csc_vsync_s;
hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_data_e <= hdmi_csc_data_e_s;
hdmi_24_data <= hdmi_csc_data_s;
end
hdmi_24_hsync <= hdmi_clip_hs_d;
hdmi_24_vsync <= hdmi_clip_vs_d;
hdmi_24_hsync_data_e <= hdmi_clip_hs_de_d;
hdmi_24_vsync_data_e <= hdmi_clip_vs_de_d;
hdmi_24_data_e <= hdmi_clip_de_d;
hdmi_24_data <= hdmi_clip_data;
if (hdmi_ss_bypass == 1'b1) begin
hdmi_16_hsync <= hdmi_24_hsync;
hdmi_16_vsync <= hdmi_24_vsync;
@ -495,7 +576,7 @@ module axi_hdmi_tx_core (
end
end
// hdmi embedded sync clipping
// hdmi embedded sync
assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e;
assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e;
@ -507,31 +588,11 @@ module axi_hdmi_tx_core (
hdmi_es_vs_de <= hdmi_es_vs_de_s;
if (hdmi_es_de_s == 1'b0) begin
hdmi_es_data[15:8] <= 8'h80;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[15:8] > 8'heb)) begin
hdmi_es_data[15:8] <= 8'heb;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[15:8] < 8'h10)) begin
hdmi_es_data[15:8] <= 8'h10;
end else if (hdmi_es_data_s[15:8] > 8'hfe) begin
hdmi_es_data[15:8] <= 8'hfe;
end else if (hdmi_es_data_s[15:8] < 8'h01) begin
hdmi_es_data[15:8] <= 8'h01;
end else begin
hdmi_es_data[15:8] <= hdmi_es_data_s[15:8];
end
if (hdmi_es_de_s == 1'b0) begin
hdmi_es_data[7:0] <= 8'h80;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[7:0] > 8'heb)) begin
hdmi_es_data[7:0] <= 8'heb;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[7:0] < 8'h10)) begin
hdmi_es_data[7:0] <= 8'h10;
end else if (hdmi_es_data_s[7:0] > 8'hfe) begin
hdmi_es_data[7:0] <= 8'hfe;
end else if (hdmi_es_data_s[7:0] < 8'h01) begin
hdmi_es_data[7:0] <= 8'h01;
end else begin
hdmi_es_data[7:0] <= hdmi_es_data_s[7:0];
end
@ -569,13 +630,13 @@ module axi_hdmi_tx_core (
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .CR_CB_N(CR_CB_N)) i_ss_444to422 (
.clk (hdmi_clk),
.s444_de (hdmi_24_data_e),
.s444_sync ({hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_hsync_data_e,
hdmi_24_vsync_data_e,
hdmi_24_data_e}),
.s444_data (hdmi_24_data),
.s444_de (hdmi_clip_de_d),
.s444_sync ({hdmi_clip_hs_d,
hdmi_clip_vs_d,
hdmi_clip_hs_de_d,
hdmi_clip_vs_de_d,
hdmi_clip_de_d}),
.s444_data (hdmi_clip_data),
.s422_sync ({hdmi_ss_hsync_s,
hdmi_ss_vsync_s,
hdmi_ss_hsync_data_e_s,

36
library/common/up_hdmi_tx.v
View File

@ -58,6 +58,8 @@ module up_hdmi_tx (
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min,
hdmi_status,
hdmi_tpm_oos,
hdmi_clk_ratio,
@ -107,6 +109,8 @@ module up_hdmi_tx (
output [15:0] hdmi_vs_width;
output [15:0] hdmi_ve_max;
output [15:0] hdmi_ve_min;
output [23:0] hdmi_clip_max;
output [23:0] hdmi_clip_min;
input hdmi_status;
input hdmi_tpm_oos;
input [31:0] hdmi_clk_ratio;
@ -157,6 +161,8 @@ module up_hdmi_tx (
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_ve_max = 'd0;
reg [15:0] up_ve_min = 'd0;
reg [23:0] up_clip_max = 'd0;
reg [23:0] up_clip_min = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -203,6 +209,8 @@ module up_hdmi_tx (
up_vs_width <= 'd0;
up_ve_max <= 'd0;
up_ve_min <= 'd0;
up_clip_max <= 24'hf0ebf0;
up_clip_min <= 24'h101010;
end else begin
up_core_preset <= ~up_resetn;
up_wack <= up_wreq_s;
@ -243,6 +251,21 @@ module up_hdmi_tx (
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
if ((up_wdata[1]== 1'b1) || (up_wdata[0] == 1'b1)) begin
up_clip_max <= 24'hfefefe;
up_clip_min <= 24'h010101;
end else begin
up_clip_max <= 24'hf0ebf0;
up_clip_min <= 24'h101010;
end
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin
up_clip_max <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
up_clip_min <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_hl_active <= up_wdata[31:16];
up_hl_width <= up_wdata[15:0];
@ -290,6 +313,9 @@ module up_hdmi_tx (
12'h017: up_rdata <= {31'd0, up_hdmi_status_s};
12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos};
12'h01a: up_rdata <= {8'd0, up_clip_max};
12'h01b: up_rdata <= {8'd0, up_clip_min};
12'h100: up_rdata <= {up_hl_active, up_hl_width};
12'h101: up_rdata <= {16'd0, up_hs_width};
12'h102: up_rdata <= {up_he_max, up_he_min};
@ -311,7 +337,7 @@ module up_hdmi_tx (
// hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(189)) i_xfer_cntrl (
up_xfer_cntrl #(.DATA_WIDTH(237)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_ss_bypass,
@ -328,7 +354,9 @@ module up_hdmi_tx (
up_vf_width,
up_vs_width,
up_ve_max,
up_ve_min}),
up_ve_min,
up_clip_max,
up_clip_min}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
@ -346,7 +374,9 @@ module up_hdmi_tx (
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min}));
hdmi_ve_min,
hdmi_clip_max,
hdmi_clip_min}));
up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
.up_rstn (up_rstn),