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fmcadc2: Update projecct to 2015.2.1 

- updated to the new jesd framework
main
Adrian Costina 2015-09-25 17:25:32 +03:00
parent 2816812e0a
commit 6fbd8dd9a5
1 changed files with 134 additions and 90 deletions
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224
projects/fmcadc2/common/fmcadc2_bd.tcl
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@ -11,19 +11,80 @@ create_bd_port -dir I -from 7 -to 0 rx_data_n
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9625_jesd]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_2 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_3 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_4 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_5 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_6 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_ad9625_gt
set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_7 {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_ad9625_gt
set util_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9625_gt]
set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9625_gt
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9625_gt
set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_ad9625_gt
set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9625_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_ad9625_gt
set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9625_gt
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
@ -40,95 +101,78 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
# connections (gt)
ad_connect axi_ad9625_gt/ref_clk_c rx_ref_clk
ad_connect axi_ad9625_gt/rx_data_p rx_data_p
ad_connect axi_ad9625_gt/rx_data_n rx_data_n
ad_connect axi_ad9625_gt/rx_sync rx_sync
ad_connect axi_ad9625_gt/rx_sysref rx_sysref
ad_connect util_ad9625_gt/qpll_ref_clk rx_ref_clk
ad_connect util_ad9625_gt/cpll_ref_clk rx_ref_clk
ad_connect axi_ad9625_gt/gt_pll_0 util_ad9625_gt/gt_pll_0
ad_connect axi_ad9625_gt/gt_pll_1 util_ad9625_gt/gt_pll_1
ad_connect axi_ad9625_gt/gt_pll_2 util_ad9625_gt/gt_pll_2
ad_connect axi_ad9625_gt/gt_pll_3 util_ad9625_gt/gt_pll_3
ad_connect axi_ad9625_gt/gt_pll_4 util_ad9625_gt/gt_pll_4
ad_connect axi_ad9625_gt/gt_pll_5 util_ad9625_gt/gt_pll_5
ad_connect axi_ad9625_gt/gt_pll_6 util_ad9625_gt/gt_pll_6
ad_connect axi_ad9625_gt/gt_pll_7 util_ad9625_gt/gt_pll_7
ad_connect axi_ad9625_gt/gt_rx_0 util_ad9625_gt/gt_rx_0
ad_connect axi_ad9625_gt/gt_rx_1 util_ad9625_gt/gt_rx_1
ad_connect axi_ad9625_gt/gt_rx_2 util_ad9625_gt/gt_rx_2
ad_connect axi_ad9625_gt/gt_rx_3 util_ad9625_gt/gt_rx_3
ad_connect axi_ad9625_gt/gt_rx_4 util_ad9625_gt/gt_rx_4
ad_connect axi_ad9625_gt/gt_rx_5 util_ad9625_gt/gt_rx_5
ad_connect axi_ad9625_gt/gt_rx_6 util_ad9625_gt/gt_rx_6
ad_connect axi_ad9625_gt/gt_rx_7 util_ad9625_gt/gt_rx_7
ad_connect axi_ad9625_gt/gt_rx_ip_0 axi_ad9625_jesd/gt0_rx
ad_connect axi_ad9625_gt/gt_rx_ip_1 axi_ad9625_jesd/gt1_rx
ad_connect axi_ad9625_gt/gt_rx_ip_2 axi_ad9625_jesd/gt2_rx
ad_connect axi_ad9625_gt/gt_rx_ip_3 axi_ad9625_jesd/gt3_rx
ad_connect axi_ad9625_gt/gt_rx_ip_4 axi_ad9625_jesd/gt4_rx
ad_connect axi_ad9625_gt/gt_rx_ip_5 axi_ad9625_jesd/gt5_rx
ad_connect axi_ad9625_gt/gt_rx_ip_6 axi_ad9625_jesd/gt6_rx
ad_connect axi_ad9625_gt/gt_rx_ip_7 axi_ad9625_jesd/gt7_rx
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_0 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_1 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_2 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_3 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_4 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_5 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_6 axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_gt_comma_align_enb_7 axi_ad9625_jesd/rxencommaalign_out
# connections (adc)
ad_connect axi_ad9625_gt/tx_clk_g axi_ad9625_gt/tx_clk
ad_connect axi_ad9625_gt/rx_clk_g axi_ad9625_gt/rx_clk
ad_connect axi_ad9625_gt/rx_clk_g axi_ad9625_core/rx_clk
ad_connect axi_ad9625_gt/rx_clk_g axi_ad9625_jesd/rx_core_clk
ad_connect axi_ad9625_gt/rx_jesd_rst axi_ad9625_jesd/rx_reset
ad_connect axi_ad9625_gt/rx_sysref axi_ad9625_jesd/rx_sysref
ad_connect util_ad9625_gt/rx_p rx_data_p
ad_connect util_ad9625_gt/rx_n rx_data_n
ad_connect util_ad9625_gt/rx_sync rx_sync
ad_connect util_ad9625_gt/rx_ip_sysref rx_sysref
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_charisk]
ad_connect util_ad9625_gt/rx_out_clk util_ad9625_gt/rx_clk
ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_jesd/rx_core_clk
ad_connect util_ad9625_gt/rx_ip_rst axi_ad9625_jesd/rx_reset
ad_connect util_ad9625_gt/rx_ip_rst_done axi_ad9625_jesd/rx_reset_done
ad_connect util_ad9625_gt/rx_ip_sysref axi_ad9625_jesd/rx_sysref
ad_connect util_ad9625_gt/rx_ip_sync axi_ad9625_jesd/rx_sync
ad_connect util_ad9625_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame
ad_connect util_ad9625_gt/rx_ip_data axi_ad9625_jesd/rx_tdata
ad_connect util_bsplit_rx_gt_charisk/data axi_ad9625_gt/rx_gt_charisk
ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9625_jesd/gt0_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9625_jesd/gt1_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9625_jesd/gt2_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9625_jesd/gt3_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_4 axi_ad9625_jesd/gt4_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_5 axi_ad9625_jesd/gt5_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_6 axi_ad9625_jesd/gt6_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_7 axi_ad9625_jesd/gt7_rxcharisk
ad_connect util_ad9625_gt/rx_out_clk axi_ad9625_core/rx_clk
ad_connect util_ad9625_gt/rx_data axi_ad9625_core/rx_data
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_disperr]
ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_core/adc_rst
ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect util_bsplit_rx_gt_disperr/data axi_ad9625_gt/rx_gt_disperr
ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9625_jesd/gt0_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad9625_jesd/gt1_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9625_jesd/gt2_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9625_jesd/gt3_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_4 axi_ad9625_jesd/gt4_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_5 axi_ad9625_jesd/gt5_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_6 axi_ad9625_jesd/gt6_rxdisperr
ad_connect util_bsplit_rx_gt_disperr/split_data_7 axi_ad9625_jesd/gt7_rxdisperr
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_notintable]
ad_connect util_bsplit_rx_gt_notintable/data axi_ad9625_gt/rx_gt_notintable
ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9625_jesd/gt0_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9625_jesd/gt1_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9625_jesd/gt2_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9625_jesd/gt3_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_4 axi_ad9625_jesd/gt4_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_5 axi_ad9625_jesd/gt5_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_6 axi_ad9625_jesd/gt6_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_7 axi_ad9625_jesd/gt7_rxnotintable
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_gt_data]
ad_connect util_bsplit_rx_gt_data/data axi_ad9625_gt/rx_gt_data
ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9625_jesd/gt0_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9625_jesd/gt1_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_2 axi_ad9625_jesd/gt2_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_3 axi_ad9625_jesd/gt3_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_4 axi_ad9625_jesd/gt4_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_5 axi_ad9625_jesd/gt5_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_6 axi_ad9625_jesd/gt6_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_7 axi_ad9625_jesd/gt7_rxdata
ad_connect axi_ad9625_gt/rx_rst_done axi_ad9625_jesd/rx_reset_done
ad_connect axi_ad9625_gt/rx_ip_comma_align axi_ad9625_jesd/rxencommaalign_out
ad_connect axi_ad9625_gt/rx_ip_sync axi_ad9625_jesd/rx_sync
ad_connect axi_ad9625_gt/rx_ip_sof axi_ad9625_jesd/rx_start_of_frame
ad_connect axi_ad9625_gt/rx_ip_data axi_ad9625_jesd/rx_tdata
ad_connect axi_ad9625_gt/rx_data axi_ad9625_core/rx_data
ad_connect axi_ad9625_fifo/adc_rst axi_ad9625_gt/rx_rst
ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk
ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr
ad_connect axi_ad9625_core/adc_data axi_ad9625_fifo/adc_wdata
ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
# interconnect (cpu)