axi_dmac: patch for partial transfers support

This patch addresses the following issue:

  In case of transfers with multiple segments, if TLAST asserts on the last
beat of a non-last segment while more descriptors are queued up,
the completions for the queued segments may be missed causing timeout in
processes that wait for transfer completions.

library/axi_dmac/data_mover.v

@@ -196,8 +196,12 @@ end
 
 // If we want to support zero delay between transfers we have to assert
 // req_ready on the same cycle on which the last load happens.
+// In case early tlast happens accept the new descriptor only when the rewind
+// request got accepted.
 assign last_load = m_axi_valid && last_eot && eot;
-assign req_ready = last_load || ~active || (transfer_abort_s & rewind_req_ready);
+assign req_ready = (last_load && ~early_tlast) ||
+                   (~active && ~transfer_abort_s) ||
+                   (transfer_abort_s && rewind_req_ready);
 
 always @(posedge clk) begin
   if (req_ready) begin