library axi-slave missing protection signal added

library/axi_ad6676/axi_ad6676.v

@@ -80,7 +80,9 @@ module axi_ad6676 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
@@ -126,6 +128,9 @@ module axi_ad6676 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad7616/axi_ad7616.v

@@ -66,6 +66,7 @@ module axi_ad7616 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -76,6 +77,7 @@ module axi_ad7616 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -140,6 +142,9 @@ module axi_ad7616 (
   output  [ 1:0]                    s_axi_rresp;
   output  [31:0]                    s_axi_rdata;
   input                             s_axi_rready;
+  input   [ 2:0]                    s_axi_awprot;
+  input   [ 2:0]                    s_axi_arprot;
+
 
   output                            adc_valid;
   output  [15:0]                    adc_data;

library/axi_ad9122/axi_ad9122.v

@@ -87,7 +87,9 @@ module axi_ad9122 (
   s_axi_rvalid,
   s_axi_rdata,
   s_axi_rresp,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -152,6 +154,9 @@ module axi_ad9122 (
   output  [31:0]  s_axi_rdata;
   output  [ 1:0]  s_axi_rresp;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal clocks and resets
 

library/axi_ad9234/axi_ad9234.v

@@ -79,7 +79,9 @@ module axi_ad9234 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
@@ -124,6 +126,9 @@ module axi_ad9234 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9265/axi_ad9265.v

@@ -84,7 +84,9 @@ module axi_ad9265 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -137,6 +139,9 @@ module axi_ad9265 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9434/axi_ad9434.v

@@ -79,7 +79,9 @@ module axi_ad9434 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
 
   // parameters
@@ -128,6 +130,9 @@ module axi_ad9434 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal clocks & resets
   wire            adc_rst;

library/axi_ad9467/axi_ad9467.v

@@ -69,6 +69,7 @@ module axi_ad9467(
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -79,6 +80,7 @@ module axi_ad9467(
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -134,6 +136,9 @@ module axi_ad9467(
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9625/axi_ad9625.v

@@ -80,7 +80,9 @@ module axi_ad9625 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   parameter ID = 0;
   parameter DEVICE_TYPE = 0;
@@ -126,6 +128,9 @@ module axi_ad9625 (
   output  [  1:0] s_axi_rresp;
   output  [ 31:0] s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9643/axi_ad9643.v

@@ -87,7 +87,9 @@ module axi_ad9643 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -145,6 +147,9 @@ module axi_ad9643 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9652/axi_ad9652.v

@@ -87,7 +87,9 @@ module axi_ad9652 (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -145,6 +147,9 @@ module axi_ad9652 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9684/axi_ad9684.v

@@ -74,6 +74,7 @@ module axi_ad9684 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -84,6 +85,7 @@ module axi_ad9684 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -139,6 +141,9 @@ module axi_ad9684 (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal registers
 

library/axi_ad9739a/axi_ad9739a.v

@@ -81,7 +81,9 @@ module axi_ad9739a (
   s_axi_rvalid,
   s_axi_rdata,
   s_axi_rresp,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -133,6 +135,9 @@ module axi_ad9739a (
   output  [ 31:0]   s_axi_rdata;
   output  [  1:0]   s_axi_rresp;
   input             s_axi_rready;
+  input   [ 2:0]    s_axi_awprot;
+  input   [ 2:0]    s_axi_arprot;
+
 
   // internal clocks and resets
 

library/axi_clkgen/axi_clkgen.v

@@ -65,7 +65,9 @@ module axi_clkgen (
   s_axi_rvalid,
   s_axi_rdata,
   s_axi_rresp,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -110,6 +112,10 @@ module axi_clkgen (
   output  [31:0]  s_axi_rdata;
   output  [ 1:0]  s_axi_rresp;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
+
 
   // reset and clocks
 

library/axi_generic_adc/axi_generic_adc.v

@@ -21,7 +21,10 @@ module axi_generic_adc (
 	output		s_axi_rvalid,
 	output	[ 1:0]	s_axi_rresp,
 	output	[31:0]	s_axi_rdata,
-	input		s_axi_rready
+	input		s_axi_rready,
+  input   [ 2:0]  s_axi_awprot,
+  input   [ 2:0]  s_axi_arprot
+
 );
 
 parameter NUM_OF_CHANNELS = 2;

library/axi_gpreg/axi_gpreg.v

@@ -111,7 +111,10 @@ module axi_gpreg #(
   output            s_axi_rvalid,
   output  [ 31:0]   s_axi_rdata,
   output  [  1:0]   s_axi_rresp,
-  input             s_axi_rready);
+  input             s_axi_rready,
+  input   [ 2:0]    s_axi_awprot,
+  input   [ 2:0]    s_axi_arprot);
+
 
   // version
 

library/axi_hdmi_rx/axi_hdmi_rx.v

@@ -73,7 +73,9 @@ module axi_hdmi_rx  (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -114,6 +116,9 @@ module axi_hdmi_rx  (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal signals
 

library/axi_i2s_adi/axi_i2s_adi.vhd

@@ -101,7 +101,10 @@ entity axi_i2s_adi is
 		S_AXI_WREADY		: out std_logic;
 		S_AXI_BRESP		: out std_logic_vector(1 downto 0);
 		S_AXI_BVALID		: out std_logic;
-		S_AXI_AWREADY		: out std_logic
+		S_AXI_AWREADY		: out std_logic;
+    S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
+    S_AXI_ARPROT  : in  std_logic_vector(2 downto 0)
+
 	);
 end entity axi_i2s_adi;
 

library/axi_jesd_gt/axi_jesd_gt.v

@@ -690,6 +690,8 @@ module axi_jesd_gt #(
   output  [ 31:0]                             s_axi_rdata,
   output  [  1:0]                             s_axi_rresp,
   input                                       s_axi_rready,
+  input   [ 2:0]                              s_axi_awprot,
+  input   [ 2:0]                              s_axi_arprot,
 
   // master interface
 

library/axi_mc_controller/axi_mc_controller.v

@@ -84,7 +84,10 @@ module axi_mc_controller
   output          s_axi_rvalid,
   output  [1:0]   s_axi_rresp,
   output  [31:0]  s_axi_rdata,
-  input           s_axi_rready
+  input           s_axi_rready,
+  input   [ 2:0]  s_axi_awprot,
+  input   [ 2:0]  s_axi_arprot
+
 );
 
 //------------------------------------------------------------------------------

library/axi_mc_current_monitor/axi_mc_current_monitor.v

@@ -77,7 +77,10 @@ module axi_mc_current_monitor (
     output          s_axi_rvalid,
     output  [1:0]   s_axi_rresp,
     output  [31:0]  s_axi_rdata,
-    input           s_axi_rready
+    input           s_axi_rready,
+    input   [ 2:0]  s_axi_awprot,
+    input   [ 2:0]  s_axi_arprot
+  
 );
 
 //------------------------------------------------------------------------------

library/axi_mc_speed/axi_mc_speed.v

@@ -68,7 +68,10 @@ module axi_mc_speed
     output          s_axi_rvalid,
     output  [ 1:0]  s_axi_rresp,
     output  [31:0]  s_axi_rdata,
-    input           s_axi_rready);
+    input           s_axi_rready,
+    input   [ 2:0]  s_axi_awprot,
+    input   [ 2:0]  s_axi_arprot
+);
 
 //------------------------------------------------------------------------------
 //----------- Registers Declarations -------------------------------------------

library/axi_spdif_rx/axi_spdif_rx.vhd

@@ -84,6 +84,9 @@ entity axi_spdif_rx is
     S_AXI_BRESP         : out std_logic_vector(1 downto 0);
     S_AXI_BVALID        : out std_logic;
     S_AXI_AWREADY       : out std_logic;
+    S_AXI_AWPROT        : in  std_logic_vector(2 downto 0);
+    S_AXI_ARPROT        : in  std_logic_vector(2 downto 0);
+
 
     --AXI STREAM interface
     M_AXIS_ACLK         : in  std_logic;

library/axi_spdif_tx/axi_spdif_tx.vhd

@@ -63,12 +63,14 @@ entity axi_spdif_tx is
 		S_AXI_ACLK	: in  std_logic;
 		S_AXI_ARESETN	: in  std_logic;
 		S_AXI_AWADDR	: in  std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
+    S_AXI_AWPROT  : in  std_logic_vector(2 downto 0);
 		S_AXI_AWVALID	: in  std_logic;
 		S_AXI_WDATA	: in  std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
 		S_AXI_WSTRB	: in  std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
 		S_AXI_WVALID	: in  std_logic;
 		S_AXI_BREADY	: in  std_logic;
 		S_AXI_ARADDR	: in  std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
+    S_AXI_ARPROT  : in  std_logic_vector(2 downto 0);
 		S_AXI_ARVALID	: in  std_logic;
 		S_AXI_RREADY	: in  std_logic;
 		S_AXI_ARREADY	: out std_logic;

library/axi_usb_fx3/axi_usb_fx3.v

@@ -91,6 +91,7 @@ module axi_usb_fx3 (
   s_axi_aresetn,
   s_axi_awvalid,
   s_axi_awaddr,
+  s_axi_awprot,
   s_axi_awready,
   s_axi_wvalid,
   s_axi_wdata,
@@ -101,6 +102,7 @@ module axi_usb_fx3 (
   s_axi_bready,
   s_axi_arvalid,
   s_axi_araddr,
+  s_axi_arprot,
   s_axi_arready,
   s_axi_rvalid,
   s_axi_rresp,
@@ -157,6 +159,7 @@ module axi_usb_fx3 (
   input           s_axi_aresetn;
   input           s_axi_awvalid;
   input   [31:0]  s_axi_awaddr;
+  input   [ 2:0]  s_axi_awprot;
   output          s_axi_awready;
   input           s_axi_wvalid;
   input   [31:0]  s_axi_wdata;
@@ -167,6 +170,7 @@ module axi_usb_fx3 (
   input           s_axi_bready;
   input           s_axi_arvalid;
   input   [31:0]  s_axi_araddr;
+  input   [ 2:0]  s_axi_arprot;
   output          s_axi_arready;
   output          s_axi_rvalid;
   output  [ 1:0]  s_axi_rresp;

library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl

@@ -67,6 +67,6 @@ adi_add_bus "dma_wr" "master" \
 	}
 
 
-adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "resetn:processing_resetn"
+adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "processing_resetn"
 
 ipx::save_core [ipx::current_core]

library/util_pmod_fmeter/util_pmod_fmeter.v

@@ -62,7 +62,9 @@ module util_pmod_fmeter (
   s_axi_rvalid,
   s_axi_rresp,
   s_axi_rdata,
-  s_axi_rready);
+  s_axi_rready,
+  s_axi_awprot,
+  s_axi_arprot);
 
   // parameters
 
@@ -94,6 +96,9 @@ module util_pmod_fmeter (
   output  [ 1:0]  s_axi_rresp;
   output  [31:0]  s_axi_rdata;
   input           s_axi_rready;
+  input   [ 2:0]  s_axi_awprot;
+  input   [ 2:0]  s_axi_arprot;
+
 
   // internal signals