util_delay: Initial commit

Generic module to introduce a fix N cycle delay into a datapath.
main
Istvan Csomortani 2017-05-12 11:44:04 +03:00
parent 9a6dc36289
commit 6ea87d094e
4 changed files with 140 additions and 0 deletions

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@ -68,6 +68,7 @@ clean:
make -C util_clkdiv clean make -C util_clkdiv clean
make -C util_cpack clean make -C util_cpack clean
make -C util_dacfifo clean make -C util_dacfifo clean
make -C util_delay clean
make -C util_extract clean make -C util_extract clean
make -C util_fir_dec clean make -C util_fir_dec clean
make -C util_fir_int clean make -C util_fir_int clean
@ -154,6 +155,7 @@ lib:
make -C util_clkdiv make -C util_clkdiv
make -C util_cpack make -C util_cpack
make -C util_dacfifo make -C util_dacfifo
make -C util_delay
make -C util_extract make -C util_extract
make -C util_fir_dec make -C util_fir_dec
make -C util_fir_int make -C util_fir_int

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@ -0,0 +1,76 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2016(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_delay #(
parameter DATA_WIDTH = 1,
// the minimum valid value for DELAY_CYCLES is 1
parameter DELAY_CYCLES = 1) (
input clk,
input reset,
input din,
output [DATA_WIDTH-1:0] dout);
reg [DATA_WIDTH-1:0] dbuf[0:(DELAY_CYCLES-1)];
always @(posedge clk) begin
if (reset) begin
dbuf[0] <= 0;
end else begin
dbuf[0] <= din;
end
end
generate
genvar i;
for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe
always @(posedge clk) begin
if (reset) begin
dbuf[i] <= 0;
end else begin
dbuf[i] <= dbuf[i-1];
end
end
end
endgenerate
assign dout = dbuf[(DELAY_CYCLES-1)];
endmodule

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@ -0,0 +1,46 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/util_delay.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_delay_ip.tcl
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_delay.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_delay.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) util_delay_ip.tcl >> util_delay_ip.log 2>&1
####################################################################################
####################################################################################

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@ -0,0 +1,16 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_delay
adi_ip_files util_delay [list \
"$ad_hdl_dir/library/common/util_delay.v"]
adi_ip_properties_lite util_delay
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
set_property value_validation_range_minimum 1 [ipx::get_user_parameters DELAY_CYCLES -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]