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zc706: remove top level constraints

main
Rejeesh Kutty 2014-10-15 14:48:38 -04:00
parent 9d43a08865
commit 6d76e0b768
2 changed files with 8 additions and 28 deletions
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17
projects/common/zc706/zc706_system_constr.xdc
View File

@ -60,20 +60,3 @@ set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3
# clocks
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK0]
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK1]
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
create_clock -name clk_fpga_0 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]]
create_clock -name clk_fpga_1 -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]]
set_clock_groups -asynchronous -group {cpu_clk}
set_clock_groups -asynchronous -group {m200_clk}
set_clock_groups -asynchronous -group {hdmi_clk}
set_clock_groups -asynchronous -group {spdif_clk}
set_clock_groups -asynchronous -group {clk_fpga_0}
set_clock_groups -asynchronous -group {clk_fpga_1}

19
projects/daq3/zc706/system_constr.xdc
View File

@ -17,14 +17,14 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0])
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0])
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3])
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3])
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P
@ -57,6 +57,3 @@ create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq3_gt_tx_clk]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq3_gt_rx_clk]
set_clock_groups -asynchronous -group {tx_div_clk}
set_clock_groups -asynchronous -group {rx_div_clk}