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avl_dacfifo: dma_ready was muxed incorrectly

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Istvan Csomortani 2017-05-15 12:35:35 +03:00
parent da68705fee
commit 6d52034abb
1 changed files with 1 additions and 1 deletions
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library/altera/avl_dacfifo/avl_dacfifo.v
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@ -229,7 +229,7 @@ module avl_dacfifo #(
// mux for the dma_ready // mux for the dma_ready
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s; dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s;
end end
// mux for dac data // mux for dac data