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axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access 

When using non-broadcast access to the GT DRP registers lane filtering is
done on both sides. The ready and data signals are filtered in the in the
axi_adxcvr module and the enable signal is filtered in the util_adxcvr
module. This works fine as long as both sides use the same transceiver IDs.
E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the
util_adxcvr module.

But this is not always the case. E.g. on the ADRV9371 platform there are
two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr.
The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses
lane 2 and 3.

Non-broadcast access for the first RX axi_adxcvr module works fine, but
always generates a timeout for the second axi_adxcvr module. This is
because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the
util_adxcvr and when ID based filtering is done both can't match at the
same time.

To avoid this perform the filtering for all the signals in the axi_adxcvr
module. This makes sure that the same base ID is used.

This also removes the sel signal from the transceiver interfaces since it
is no longer used on the util_adxcvr side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-06-28 16:22:10 +02:00
parent e4e74fe6ce
commit 6d4430cfda
7 changed files with 59 additions and 358 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

144
library/xilinx/axi_adxcvr/axi_adxcvr.v
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@ -50,7 +50,6 @@ module axi_adxcvr #(
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
output [ 7:0] up_cm_sel_0,
output up_cm_enb_0,
output [11:0] up_cm_addr_0,
output up_cm_wr_0,
@ -58,7 +57,6 @@ module axi_adxcvr #(
input [15:0] up_cm_rdata_0,
input up_cm_ready_0,
output [ 7:0] up_es_sel_0,
output up_es_enb_0,
output [11:0] up_es_addr_0,
output up_es_wr_0,
@ -74,7 +72,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_0,
output [ 1:0] up_ch_sys_clk_sel_0,
output [ 2:0] up_ch_out_clk_sel_0,
output [ 7:0] up_ch_sel_0,
output up_ch_enb_0,
output [11:0] up_ch_addr_0,
output up_ch_wr_0,
@ -82,7 +79,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_0,
input up_ch_ready_0,
output [ 7:0] up_es_sel_1,
output up_es_enb_1,
output [11:0] up_es_addr_1,
output up_es_wr_1,
@ -98,7 +94,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_1,
output [ 1:0] up_ch_sys_clk_sel_1,
output [ 2:0] up_ch_out_clk_sel_1,
output [ 7:0] up_ch_sel_1,
output up_ch_enb_1,
output [11:0] up_ch_addr_1,
output up_ch_wr_1,
@ -106,7 +101,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_1,
input up_ch_ready_1,
output [ 7:0] up_es_sel_2,
output up_es_enb_2,
output [11:0] up_es_addr_2,
output up_es_wr_2,
@ -122,7 +116,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_2,
output [ 1:0] up_ch_sys_clk_sel_2,
output [ 2:0] up_ch_out_clk_sel_2,
output [ 7:0] up_ch_sel_2,
output up_ch_enb_2,
output [11:0] up_ch_addr_2,
output up_ch_wr_2,
@ -130,7 +123,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_2,
input up_ch_ready_2,
output [ 7:0] up_es_sel_3,
output up_es_enb_3,
output [11:0] up_es_addr_3,
output up_es_wr_3,
@ -146,7 +138,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_3,
output [ 1:0] up_ch_sys_clk_sel_3,
output [ 2:0] up_ch_out_clk_sel_3,
output [ 7:0] up_ch_sel_3,
output up_ch_enb_3,
output [11:0] up_ch_addr_3,
output up_ch_wr_3,
@ -154,7 +145,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_3,
input up_ch_ready_3,
output [ 7:0] up_cm_sel_4,
output up_cm_enb_4,
output [11:0] up_cm_addr_4,
output up_cm_wr_4,
@ -162,7 +152,6 @@ module axi_adxcvr #(
input [15:0] up_cm_rdata_4,
input up_cm_ready_4,
output [ 7:0] up_es_sel_4,
output up_es_enb_4,
output [11:0] up_es_addr_4,
output up_es_wr_4,
@ -178,7 +167,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_4,
output [ 1:0] up_ch_sys_clk_sel_4,
output [ 2:0] up_ch_out_clk_sel_4,
output [ 7:0] up_ch_sel_4,
output up_ch_enb_4,
output [11:0] up_ch_addr_4,
output up_ch_wr_4,
@ -186,7 +174,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_4,
input up_ch_ready_4,
output [ 7:0] up_es_sel_5,
output up_es_enb_5,
output [11:0] up_es_addr_5,
output up_es_wr_5,
@ -202,7 +189,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_5,
output [ 1:0] up_ch_sys_clk_sel_5,
output [ 2:0] up_ch_out_clk_sel_5,
output [ 7:0] up_ch_sel_5,
output up_ch_enb_5,
output [11:0] up_ch_addr_5,
output up_ch_wr_5,
@ -210,7 +196,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_5,
input up_ch_ready_5,
output [ 7:0] up_es_sel_6,
output up_es_enb_6,
output [11:0] up_es_addr_6,
output up_es_wr_6,
@ -226,7 +211,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_6,
output [ 1:0] up_ch_sys_clk_sel_6,
output [ 2:0] up_ch_out_clk_sel_6,
output [ 7:0] up_ch_sel_6,
output up_ch_enb_6,
output [11:0] up_ch_addr_6,
output up_ch_wr_6,
@ -234,7 +218,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_6,
input up_ch_ready_6,
output [ 7:0] up_es_sel_7,
output up_es_enb_7,
output [11:0] up_es_addr_7,
output up_es_wr_7,
@ -250,7 +233,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_7,
output [ 1:0] up_ch_sys_clk_sel_7,
output [ 2:0] up_ch_out_clk_sel_7,
output [ 7:0] up_ch_sel_7,
output up_ch_enb_7,
output [11:0] up_ch_addr_7,
output up_ch_wr_7,
@ -258,7 +240,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_7,
input up_ch_ready_7,
output [ 7:0] up_cm_sel_8,
output up_cm_enb_8,
output [11:0] up_cm_addr_8,
output up_cm_wr_8,
@ -266,7 +247,6 @@ module axi_adxcvr #(
input [15:0] up_cm_rdata_8,
input up_cm_ready_8,
output [ 7:0] up_es_sel_8,
output up_es_enb_8,
output [11:0] up_es_addr_8,
output up_es_wr_8,
@ -282,7 +262,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_8,
output [ 1:0] up_ch_sys_clk_sel_8,
output [ 2:0] up_ch_out_clk_sel_8,
output [ 7:0] up_ch_sel_8,
output up_ch_enb_8,
output [11:0] up_ch_addr_8,
output up_ch_wr_8,
@ -290,7 +269,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_8,
input up_ch_ready_8,
output [ 7:0] up_es_sel_9,
output up_es_enb_9,
output [11:0] up_es_addr_9,
output up_es_wr_9,
@ -306,7 +284,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_9,
output [ 1:0] up_ch_sys_clk_sel_9,
output [ 2:0] up_ch_out_clk_sel_9,
output [ 7:0] up_ch_sel_9,
output up_ch_enb_9,
output [11:0] up_ch_addr_9,
output up_ch_wr_9,
@ -314,7 +291,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_9,
input up_ch_ready_9,
output [ 7:0] up_es_sel_10,
output up_es_enb_10,
output [11:0] up_es_addr_10,
output up_es_wr_10,
@ -330,7 +306,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_10,
output [ 1:0] up_ch_sys_clk_sel_10,
output [ 2:0] up_ch_out_clk_sel_10,
output [ 7:0] up_ch_sel_10,
output up_ch_enb_10,
output [11:0] up_ch_addr_10,
output up_ch_wr_10,
@ -338,7 +313,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_10,
input up_ch_ready_10,
output [ 7:0] up_es_sel_11,
output up_es_enb_11,
output [11:0] up_es_addr_11,
output up_es_wr_11,
@ -354,7 +328,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_11,
output [ 1:0] up_ch_sys_clk_sel_11,
output [ 2:0] up_ch_out_clk_sel_11,
output [ 7:0] up_ch_sel_11,
output up_ch_enb_11,
output [11:0] up_ch_addr_11,
output up_ch_wr_11,
@ -362,7 +335,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_11,
input up_ch_ready_11,
output [ 7:0] up_cm_sel_12,
output up_cm_enb_12,
output [11:0] up_cm_addr_12,
output up_cm_wr_12,
@ -370,7 +342,6 @@ module axi_adxcvr #(
input [15:0] up_cm_rdata_12,
input up_cm_ready_12,
output [ 7:0] up_es_sel_12,
output up_es_enb_12,
output [11:0] up_es_addr_12,
output up_es_wr_12,
@ -386,7 +357,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_12,
output [ 1:0] up_ch_sys_clk_sel_12,
output [ 2:0] up_ch_out_clk_sel_12,
output [ 7:0] up_ch_sel_12,
output up_ch_enb_12,
output [11:0] up_ch_addr_12,
output up_ch_wr_12,
@ -394,7 +364,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_12,
input up_ch_ready_12,
output [ 7:0] up_es_sel_13,
output up_es_enb_13,
output [11:0] up_es_addr_13,
output up_es_wr_13,
@ -410,7 +379,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_13,
output [ 1:0] up_ch_sys_clk_sel_13,
output [ 2:0] up_ch_out_clk_sel_13,
output [ 7:0] up_ch_sel_13,
output up_ch_enb_13,
output [11:0] up_ch_addr_13,
output up_ch_wr_13,
@ -418,7 +386,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_13,
input up_ch_ready_13,
output [ 7:0] up_es_sel_14,
output up_es_enb_14,
output [11:0] up_es_addr_14,
output up_es_wr_14,
@ -434,7 +401,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_14,
output [ 1:0] up_ch_sys_clk_sel_14,
output [ 2:0] up_ch_out_clk_sel_14,
output [ 7:0] up_ch_sel_14,
output up_ch_enb_14,
output [11:0] up_ch_addr_14,
output up_ch_wr_14,
@ -442,7 +408,6 @@ module axi_adxcvr #(
input [15:0] up_ch_rdata_14,
input up_ch_ready_14,
output [ 7:0] up_es_sel_15,
output up_es_enb_15,
output [11:0] up_es_addr_15,
output up_es_wr_15,
@ -458,7 +423,6 @@ module axi_adxcvr #(
output [ 2:0] up_ch_rate_15,
output [ 1:0] up_ch_sys_clk_sel_15,
output [ 2:0] up_ch_out_clk_sel_15,
output [ 7:0] up_ch_sel_15,
output up_ch_enb_15,
output [11:0] up_ch_addr_15,
output up_ch_wr_15,
@ -666,8 +630,6 @@ module axi_adxcvr #(
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign up_cm_sel_0 = up_cm_sel;
assign up_cm_enb_0 = up_cm_enb;
assign up_cm_addr_0 = up_cm_addr;
assign up_cm_wr_0 = up_cm_wr;
assign up_cm_wdata_0 = up_cm_wdata;
@ -680,6 +642,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_cm_sel),
.up_enb (up_cm_enb),
.up_enb_out (up_cm_enb_0),
.up_rdata_in (16'd0),
.up_ready_in (1'd1),
.up_rdata (up_cm_rdata_0),
@ -687,8 +650,6 @@ module axi_adxcvr #(
.up_rdata_out (up_cm_rdata_0_s),
.up_ready_out (up_cm_ready_0_s));
assign up_es_sel_0 = up_es_sel;
assign up_es_enb_0 = up_es_enb;
assign up_es_addr_0 = up_es_addr;
assign up_es_wr_0 = up_es_wr;
assign up_es_wdata_0 = up_es_wdata;
@ -701,6 +662,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_0),
.up_rdata_in (16'd0),
.up_ready_in (1'd1),
.up_rdata (up_es_rdata_0),
@ -728,8 +690,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_0_s),
.up_rst_done_out (up_ch_rst_done_0_s));
assign up_ch_sel_0 = up_ch_sel;
assign up_ch_enb_0 = up_ch_enb;
assign up_ch_addr_0 = up_ch_addr;
assign up_ch_wr_0 = up_ch_wr;
assign up_ch_wdata_0 = up_ch_wdata;
@ -742,6 +702,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_0),
.up_rdata_in (16'd0),
.up_ready_in (1'd1),
.up_rdata (up_ch_rdata_0),
@ -749,8 +710,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_0_s),
.up_ready_out (up_ch_ready_0_s));
assign up_es_sel_1 = up_es_sel;
assign up_es_enb_1 = up_es_enb;
assign up_es_addr_1 = up_es_addr;
assign up_es_wr_1 = up_es_wr;
assign up_es_wdata_1 = up_es_wdata;
@ -763,6 +722,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_1),
.up_rdata_in (up_es_rdata_0_s),
.up_ready_in (up_es_ready_0_s),
.up_rdata (up_es_rdata_1),
@ -790,8 +750,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_1_s),
.up_rst_done_out (up_ch_rst_done_1_s));
assign up_ch_sel_1 = up_ch_sel;
assign up_ch_enb_1 = up_ch_enb;
assign up_ch_addr_1 = up_ch_addr;
assign up_ch_wr_1 = up_ch_wr;
assign up_ch_wdata_1 = up_ch_wdata;
@ -804,6 +762,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_1),
.up_rdata_in (up_ch_rdata_0_s),
.up_ready_in (up_ch_ready_0_s),
.up_rdata (up_ch_rdata_1),
@ -811,8 +770,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_1_s),
.up_ready_out (up_ch_ready_1_s));
assign up_es_sel_2 = up_es_sel;
assign up_es_enb_2 = up_es_enb;
assign up_es_addr_2 = up_es_addr;
assign up_es_wr_2 = up_es_wr;
assign up_es_wdata_2 = up_es_wdata;
@ -825,6 +782,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_2),
.up_rdata_in (up_es_rdata_1_s),
.up_ready_in (up_es_ready_1_s),
.up_rdata (up_es_rdata_2),
@ -852,8 +810,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_2_s),
.up_rst_done_out (up_ch_rst_done_2_s));
assign up_ch_sel_2 = up_ch_sel;
assign up_ch_enb_2 = up_ch_enb;
assign up_ch_addr_2 = up_ch_addr;
assign up_ch_wr_2 = up_ch_wr;
assign up_ch_wdata_2 = up_ch_wdata;
@ -866,6 +822,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_2),
.up_rdata_in (up_ch_rdata_1_s),
.up_ready_in (up_ch_ready_1_s),
.up_rdata (up_ch_rdata_2),
@ -873,8 +830,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_2_s),
.up_ready_out (up_ch_ready_2_s));
assign up_es_sel_3 = up_es_sel;
assign up_es_enb_3 = up_es_enb;
assign up_es_addr_3 = up_es_addr;
assign up_es_wr_3 = up_es_wr;
assign up_es_wdata_3 = up_es_wdata;
@ -887,6 +842,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_3),
.up_rdata_in (up_es_rdata_2_s),
.up_ready_in (up_es_ready_2_s),
.up_rdata (up_es_rdata_3),
@ -914,8 +870,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_3_s),
.up_rst_done_out (up_ch_rst_done_3_s));
assign up_ch_sel_3 = up_ch_sel;
assign up_ch_enb_3 = up_ch_enb;
assign up_ch_addr_3 = up_ch_addr;
assign up_ch_wr_3 = up_ch_wr;
assign up_ch_wdata_3 = up_ch_wdata;
@ -928,6 +882,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_3),
.up_rdata_in (up_ch_rdata_2_s),
.up_ready_in (up_ch_ready_2_s),
.up_rdata (up_ch_rdata_3),
@ -935,8 +890,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_3_s),
.up_ready_out (up_ch_ready_3_s));
assign up_cm_sel_4 = up_cm_sel;
assign up_cm_enb_4 = up_cm_enb;
assign up_cm_addr_4 = up_cm_addr;
assign up_cm_wr_4 = up_cm_wr;
assign up_cm_wdata_4 = up_cm_wdata;
@ -949,6 +902,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_cm_sel),
.up_enb (up_cm_enb),
.up_enb_out (up_cm_enb_4),
.up_rdata_in (up_cm_rdata_0_s),
.up_ready_in (up_cm_ready_0_s),
.up_rdata (up_cm_rdata_4),
@ -956,8 +910,6 @@ module axi_adxcvr #(
.up_rdata_out (up_cm_rdata_4_s),
.up_ready_out (up_cm_ready_4_s));
assign up_es_sel_4 = up_es_sel;
assign up_es_enb_4 = up_es_enb;
assign up_es_addr_4 = up_es_addr;
assign up_es_wr_4 = up_es_wr;
assign up_es_wdata_4 = up_es_wdata;
@ -970,6 +922,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_4),
.up_rdata_in (up_es_rdata_3_s),
.up_ready_in (up_es_ready_3_s),
.up_rdata (up_es_rdata_4),
@ -997,8 +950,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_4_s),
.up_rst_done_out (up_ch_rst_done_4_s));
assign up_ch_sel_4 = up_ch_sel;
assign up_ch_enb_4 = up_ch_enb;
assign up_ch_addr_4 = up_ch_addr;
assign up_ch_wr_4 = up_ch_wr;
assign up_ch_wdata_4 = up_ch_wdata;
@ -1011,6 +962,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_4),
.up_rdata_in (up_ch_rdata_3_s),
.up_ready_in (up_ch_ready_3_s),
.up_rdata (up_ch_rdata_4),
@ -1018,8 +970,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_4_s),
.up_ready_out (up_ch_ready_4_s));
assign up_es_sel_5 = up_es_sel;
assign up_es_enb_5 = up_es_enb;
assign up_es_addr_5 = up_es_addr;
assign up_es_wr_5 = up_es_wr;
assign up_es_wdata_5 = up_es_wdata;
@ -1032,6 +982,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_5),
.up_rdata_in (up_es_rdata_4_s),
.up_ready_in (up_es_ready_4_s),
.up_rdata (up_es_rdata_5),
@ -1059,8 +1010,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_5_s),
.up_rst_done_out (up_ch_rst_done_5_s));
assign up_ch_sel_5 = up_ch_sel;
assign up_ch_enb_5 = up_ch_enb;
assign up_ch_addr_5 = up_ch_addr;
assign up_ch_wr_5 = up_ch_wr;
assign up_ch_wdata_5 = up_ch_wdata;
@ -1073,6 +1022,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_5),
.up_rdata_in (up_ch_rdata_4_s),
.up_ready_in (up_ch_ready_4_s),
.up_rdata (up_ch_rdata_5),
@ -1080,8 +1030,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_5_s),
.up_ready_out (up_ch_ready_5_s));
assign up_es_sel_6 = up_es_sel;
assign up_es_enb_6 = up_es_enb;
assign up_es_addr_6 = up_es_addr;
assign up_es_wr_6 = up_es_wr;
assign up_es_wdata_6 = up_es_wdata;
@ -1094,6 +1042,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_6),
.up_rdata_in (up_es_rdata_5_s),
.up_ready_in (up_es_ready_5_s),
.up_rdata (up_es_rdata_6),
@ -1121,8 +1070,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_6_s),
.up_rst_done_out (up_ch_rst_done_6_s));
assign up_ch_sel_6 = up_ch_sel;
assign up_ch_enb_6 = up_ch_enb;
assign up_ch_addr_6 = up_ch_addr;
assign up_ch_wr_6 = up_ch_wr;
assign up_ch_wdata_6 = up_ch_wdata;
@ -1135,6 +1082,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_6),
.up_rdata_in (up_ch_rdata_5_s),
.up_ready_in (up_ch_ready_5_s),
.up_rdata (up_ch_rdata_6),
@ -1142,8 +1090,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_6_s),
.up_ready_out (up_ch_ready_6_s));
assign up_es_sel_7 = up_es_sel;
assign up_es_enb_7 = up_es_enb;
assign up_es_addr_7 = up_es_addr;
assign up_es_wr_7 = up_es_wr;
assign up_es_wdata_7 = up_es_wdata;
@ -1156,6 +1102,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_7),
.up_rdata_in (up_es_rdata_6_s),
.up_ready_in (up_es_ready_6_s),
.up_rdata (up_es_rdata_7),
@ -1183,8 +1130,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_7_s),
.up_rst_done_out (up_ch_rst_done_7_s));
assign up_ch_sel_7 = up_ch_sel;
assign up_ch_enb_7 = up_ch_enb;
assign up_ch_addr_7 = up_ch_addr;
assign up_ch_wr_7 = up_ch_wr;
assign up_ch_wdata_7 = up_ch_wdata;
@ -1197,6 +1142,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_7),
.up_rdata_in (up_ch_rdata_6_s),
.up_ready_in (up_ch_ready_6_s),
.up_rdata (up_ch_rdata_7),
@ -1204,8 +1150,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_7_s),
.up_ready_out (up_ch_ready_7_s));
assign up_cm_sel_8 = up_cm_sel;
assign up_cm_enb_8 = up_cm_enb;
assign up_cm_addr_8 = up_cm_addr;
assign up_cm_wr_8 = up_cm_wr;
assign up_cm_wdata_8 = up_cm_wdata;
@ -1218,6 +1162,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_cm_sel),
.up_enb (up_cm_enb),
.up_enb_out (up_cm_enb_8),
.up_rdata_in (up_cm_rdata_4_s),
.up_ready_in (up_cm_ready_4_s),
.up_rdata (up_cm_rdata_8),
@ -1225,8 +1170,6 @@ module axi_adxcvr #(
.up_rdata_out (up_cm_rdata_8_s),
.up_ready_out (up_cm_ready_8_s));
assign up_es_sel_8 = up_es_sel;
assign up_es_enb_8 = up_es_enb;
assign up_es_addr_8 = up_es_addr;
assign up_es_wr_8 = up_es_wr;
assign up_es_wdata_8 = up_es_wdata;
@ -1239,6 +1182,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_8),
.up_rdata_in (up_es_rdata_7_s),
.up_ready_in (up_es_ready_7_s),
.up_rdata (up_es_rdata_8),
@ -1266,8 +1210,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_8_s),
.up_rst_done_out (up_ch_rst_done_8_s));
assign up_ch_sel_8 = up_ch_sel;
assign up_ch_enb_8 = up_ch_enb;
assign up_ch_addr_8 = up_ch_addr;
assign up_ch_wr_8 = up_ch_wr;
assign up_ch_wdata_8 = up_ch_wdata;
@ -1280,6 +1222,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_8),
.up_rdata_in (up_ch_rdata_7_s),
.up_ready_in (up_ch_ready_7_s),
.up_rdata (up_ch_rdata_8),
@ -1287,8 +1230,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_8_s),
.up_ready_out (up_ch_ready_8_s));
assign up_es_sel_9 = up_es_sel;
assign up_es_enb_9 = up_es_enb;
assign up_es_addr_9 = up_es_addr;
assign up_es_wr_9 = up_es_wr;
assign up_es_wdata_9 = up_es_wdata;
@ -1301,6 +1242,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_9),
.up_rdata_in (up_es_rdata_8_s),
.up_ready_in (up_es_ready_8_s),
.up_rdata (up_es_rdata_9),
@ -1328,8 +1270,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_9_s),
.up_rst_done_out (up_ch_rst_done_9_s));
assign up_ch_sel_9 = up_ch_sel;
assign up_ch_enb_9 = up_ch_enb;
assign up_ch_addr_9 = up_ch_addr;
assign up_ch_wr_9 = up_ch_wr;
assign up_ch_wdata_9 = up_ch_wdata;
@ -1342,6 +1282,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_9),
.up_rdata_in (up_ch_rdata_8_s),
.up_ready_in (up_ch_ready_8_s),
.up_rdata (up_ch_rdata_9),
@ -1349,8 +1290,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_9_s),
.up_ready_out (up_ch_ready_9_s));
assign up_es_sel_10 = up_es_sel;
assign up_es_enb_10 = up_es_enb;
assign up_es_addr_10 = up_es_addr;
assign up_es_wr_10 = up_es_wr;
assign up_es_wdata_10 = up_es_wdata;
@ -1363,6 +1302,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_10),
.up_rdata_in (up_es_rdata_9_s),
.up_ready_in (up_es_ready_9_s),
.up_rdata (up_es_rdata_10),
@ -1390,8 +1330,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_10_s),
.up_rst_done_out (up_ch_rst_done_10_s));
assign up_ch_sel_10 = up_ch_sel;
assign up_ch_enb_10 = up_ch_enb;
assign up_ch_addr_10 = up_ch_addr;
assign up_ch_wr_10 = up_ch_wr;
assign up_ch_wdata_10 = up_ch_wdata;
@ -1404,6 +1342,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_10),
.up_rdata_in (up_ch_rdata_9_s),
.up_ready_in (up_ch_ready_9_s),
.up_rdata (up_ch_rdata_10),
@ -1411,8 +1350,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_10_s),
.up_ready_out (up_ch_ready_10_s));
assign up_es_sel_11 = up_es_sel;
assign up_es_enb_11 = up_es_enb;
assign up_es_addr_11 = up_es_addr;
assign up_es_wr_11 = up_es_wr;
assign up_es_wdata_11 = up_es_wdata;
@ -1425,6 +1362,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_11),
.up_rdata_in (up_es_rdata_10_s),
.up_ready_in (up_es_ready_10_s),
.up_rdata (up_es_rdata_11),
@ -1452,8 +1390,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_11_s),
.up_rst_done_out (up_ch_rst_done_11_s));
assign up_ch_sel_11 = up_ch_sel;
assign up_ch_enb_11 = up_ch_enb;
assign up_ch_addr_11 = up_ch_addr;
assign up_ch_wr_11 = up_ch_wr;
assign up_ch_wdata_11 = up_ch_wdata;
@ -1466,6 +1402,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_11),
.up_rdata_in (up_ch_rdata_10_s),
.up_ready_in (up_ch_ready_10_s),
.up_rdata (up_ch_rdata_11),
@ -1473,8 +1410,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_11_s),
.up_ready_out (up_ch_ready_11_s));
assign up_cm_sel_12 = up_cm_sel;
assign up_cm_enb_12 = up_cm_enb;
assign up_cm_addr_12 = up_cm_addr;
assign up_cm_wr_12 = up_cm_wr;
assign up_cm_wdata_12 = up_cm_wdata;
@ -1487,6 +1422,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_cm_sel),
.up_enb (up_cm_enb),
.up_enb_out (up_cm_enb_12),
.up_rdata_in (up_cm_rdata_8_s),
.up_ready_in (up_cm_ready_8_s),
.up_rdata (up_cm_rdata_12),
@ -1494,8 +1430,6 @@ module axi_adxcvr #(
.up_rdata_out (up_cm_rdata_12_s),
.up_ready_out (up_cm_ready_12_s));
assign up_es_sel_12 = up_es_sel;
assign up_es_enb_12 = up_es_enb;
assign up_es_addr_12 = up_es_addr;
assign up_es_wr_12 = up_es_wr;
assign up_es_wdata_12 = up_es_wdata;
@ -1508,6 +1442,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_12),
.up_rdata_in (up_es_rdata_11_s),
.up_ready_in (up_es_ready_11_s),
.up_rdata (up_es_rdata_12),
@ -1535,8 +1470,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_12_s),
.up_rst_done_out (up_ch_rst_done_12_s));
assign up_ch_sel_12 = up_ch_sel;
assign up_ch_enb_12 = up_ch_enb;
assign up_ch_addr_12 = up_ch_addr;
assign up_ch_wr_12 = up_ch_wr;
assign up_ch_wdata_12 = up_ch_wdata;
@ -1549,6 +1482,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_12),
.up_rdata_in (up_ch_rdata_11_s),
.up_ready_in (up_ch_ready_11_s),
.up_rdata (up_ch_rdata_12),
@ -1556,8 +1490,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_12_s),
.up_ready_out (up_ch_ready_12_s));
assign up_es_sel_13 = up_es_sel;
assign up_es_enb_13 = up_es_enb;
assign up_es_addr_13 = up_es_addr;
assign up_es_wr_13 = up_es_wr;
assign up_es_wdata_13 = up_es_wdata;
@ -1570,6 +1502,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_13),
.up_rdata_in (up_es_rdata_12_s),
.up_ready_in (up_es_ready_12_s),
.up_rdata (up_es_rdata_13),
@ -1597,8 +1530,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_13_s),
.up_rst_done_out (up_ch_rst_done_13_s));
assign up_ch_sel_13 = up_ch_sel;
assign up_ch_enb_13 = up_ch_enb;
assign up_ch_addr_13 = up_ch_addr;
assign up_ch_wr_13 = up_ch_wr;
assign up_ch_wdata_13 = up_ch_wdata;
@ -1611,6 +1542,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_13),
.up_rdata_in (up_ch_rdata_12_s),
.up_ready_in (up_ch_ready_12_s),
.up_rdata (up_ch_rdata_13),
@ -1618,8 +1550,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_13_s),
.up_ready_out (up_ch_ready_13_s));
assign up_es_sel_14 = up_es_sel;
assign up_es_enb_14 = up_es_enb;
assign up_es_addr_14 = up_es_addr;
assign up_es_wr_14 = up_es_wr;
assign up_es_wdata_14 = up_es_wdata;
@ -1632,6 +1562,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_14),
.up_rdata_in (up_es_rdata_13_s),
.up_ready_in (up_es_ready_13_s),
.up_rdata (up_es_rdata_14),
@ -1659,8 +1590,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_14_s),
.up_rst_done_out (up_ch_rst_done_14_s));
assign up_ch_sel_14 = up_ch_sel;
assign up_ch_enb_14 = up_ch_enb;
assign up_ch_addr_14 = up_ch_addr;
assign up_ch_wr_14 = up_ch_wr;
assign up_ch_wdata_14 = up_ch_wdata;
@ -1673,6 +1602,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_14),
.up_rdata_in (up_ch_rdata_13_s),
.up_ready_in (up_ch_ready_13_s),
.up_rdata (up_ch_rdata_14),
@ -1680,8 +1610,6 @@ module axi_adxcvr #(
.up_rdata_out (up_ch_rdata_14_s),
.up_ready_out (up_ch_ready_14_s));
assign up_es_sel_15 = up_es_sel;
assign up_es_enb_15 = up_es_enb;
assign up_es_addr_15 = up_es_addr;
assign up_es_wr_15 = up_es_wr;
assign up_es_wdata_15 = up_es_wdata;
@ -1694,6 +1622,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_es_sel),
.up_enb (up_es_enb),
.up_enb_out (up_es_enb_15),
.up_rdata_in (up_es_rdata_14_s),
.up_ready_in (up_es_ready_14_s),
.up_rdata (up_es_rdata_15),
@ -1721,8 +1650,6 @@ module axi_adxcvr #(
.up_pll_locked_out (up_ch_pll_locked_15_s),
.up_rst_done_out (up_ch_rst_done_15_s));
assign up_ch_sel_15 = up_ch_sel;
assign up_ch_enb_15 = up_ch_enb;
assign up_ch_addr_15 = up_ch_addr;
assign up_ch_wr_15 = up_ch_wr;
assign up_ch_wdata_15 = up_ch_wdata;
@ -1735,6 +1662,7 @@ module axi_adxcvr #(
.up_clk (up_clk),
.up_sel (up_ch_sel),
.up_enb (up_ch_enb),
.up_enb_out (up_ch_enb_15),
.up_rdata_in (up_ch_rdata_14_s),
.up_ready_in (up_ch_ready_14_s),
.up_rdata (up_ch_rdata_15),

3
library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
View File

@ -25,7 +25,6 @@ for {set n 0} {$n < 16} {incr n} {
if {($n%4) == 0} {
adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \
"sel up_cm_sel_${n} "\
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
@ -35,7 +34,6 @@ for {set n 0} {$n < 16} {incr n} {
}
adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \
"sel up_es_sel_${n} "\
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
@ -52,7 +50,6 @@ for {set n 0} {$n < 16} {incr n} {
"rate up_ch_rate_${n} "\
"sys_clk_sel up_ch_sys_clk_sel_${n} "\
"out_clk_sel up_ch_out_clk_sel_${n} "\
"sel up_ch_sel_${n} "\
"enb up_ch_enb_${n} "\
"addr up_ch_addr_${n} "\
"wr up_ch_wr_${n} "\

3
library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
View File

@ -42,6 +42,7 @@ module axi_adxcvr_mdrp (
input [ 7:0] up_sel,
input up_enb,
output up_enb_out,
input [15:0] up_rdata_in,
input up_ready_in,
input [15:0] up_rdata,
@ -75,6 +76,8 @@ module axi_adxcvr_mdrp (
assign up_rdata_out = up_rdata_int;
assign up_ready_out = up_ready_int;
assign up_enb_out = (up_sel == 8'hff || up_sel == XCVR_ID) ? up_enb : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata_int <= 16'd0;

217
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -94,14 +94,12 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_0,
input [31:0] tx_data_0,
input [ 7:0] up_cm_sel_0,
input up_cm_enb_0,
input [11:0] up_cm_addr_0,
input up_cm_wr_0,
input [15:0] up_cm_wdata_0,
output [15:0] up_cm_rdata_0,
output up_cm_ready_0,
input [ 7:0] up_es_sel_0,
input up_es_enb_0,
input [11:0] up_es_addr_0,
input up_es_wr_0,
@ -116,7 +114,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_0,
input [ 1:0] up_rx_sys_clk_sel_0,
input [ 2:0] up_rx_out_clk_sel_0,
input [ 7:0] up_rx_sel_0,
input up_rx_enb_0,
input [11:0] up_rx_addr_0,
input up_rx_wr_0,
@ -131,7 +128,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_0,
input [ 1:0] up_tx_sys_clk_sel_0,
input [ 2:0] up_tx_out_clk_sel_0,
input [ 7:0] up_tx_sel_0,
input up_tx_enb_0,
input [11:0] up_tx_addr_0,
input up_tx_wr_0,
@ -159,7 +155,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_1,
input [31:0] tx_data_1,
input [ 7:0] up_es_sel_1,
input up_es_enb_1,
input [11:0] up_es_addr_1,
input up_es_wr_1,
@ -174,7 +169,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_1,
input [ 1:0] up_rx_sys_clk_sel_1,
input [ 2:0] up_rx_out_clk_sel_1,
input [ 7:0] up_rx_sel_1,
input up_rx_enb_1,
input [11:0] up_rx_addr_1,
input up_rx_wr_1,
@ -189,7 +183,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_1,
input [ 1:0] up_tx_sys_clk_sel_1,
input [ 2:0] up_tx_out_clk_sel_1,
input [ 7:0] up_tx_sel_1,
input up_tx_enb_1,
input [11:0] up_tx_addr_1,
input up_tx_wr_1,
@ -217,7 +210,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_2,
input [31:0] tx_data_2,
input [ 7:0] up_es_sel_2,
input up_es_enb_2,
input [11:0] up_es_addr_2,
input up_es_wr_2,
@ -232,7 +224,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_2,
input [ 1:0] up_rx_sys_clk_sel_2,
input [ 2:0] up_rx_out_clk_sel_2,
input [ 7:0] up_rx_sel_2,
input up_rx_enb_2,
input [11:0] up_rx_addr_2,
input up_rx_wr_2,
@ -247,7 +238,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_2,
input [ 1:0] up_tx_sys_clk_sel_2,
input [ 2:0] up_tx_out_clk_sel_2,
input [ 7:0] up_tx_sel_2,
input up_tx_enb_2,
input [11:0] up_tx_addr_2,
input up_tx_wr_2,
@ -275,7 +265,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_3,
input [31:0] tx_data_3,
input [ 7:0] up_es_sel_3,
input up_es_enb_3,
input [11:0] up_es_addr_3,
input up_es_wr_3,
@ -290,7 +279,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_3,
input [ 1:0] up_rx_sys_clk_sel_3,
input [ 2:0] up_rx_out_clk_sel_3,
input [ 7:0] up_rx_sel_3,
input up_rx_enb_3,
input [11:0] up_rx_addr_3,
input up_rx_wr_3,
@ -305,7 +293,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_3,
input [ 1:0] up_tx_sys_clk_sel_3,
input [ 2:0] up_tx_out_clk_sel_3,
input [ 7:0] up_tx_sel_3,
input up_tx_enb_3,
input [11:0] up_tx_addr_3,
input up_tx_wr_3,
@ -335,14 +322,12 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_4,
input [31:0] tx_data_4,
input [ 7:0] up_cm_sel_4,
input up_cm_enb_4,
input [11:0] up_cm_addr_4,
input up_cm_wr_4,
input [15:0] up_cm_wdata_4,
output [15:0] up_cm_rdata_4,
output up_cm_ready_4,
input [ 7:0] up_es_sel_4,
input up_es_enb_4,
input [11:0] up_es_addr_4,
input up_es_wr_4,
@ -357,7 +342,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_4,
input [ 1:0] up_rx_sys_clk_sel_4,
input [ 2:0] up_rx_out_clk_sel_4,
input [ 7:0] up_rx_sel_4,
input up_rx_enb_4,
input [11:0] up_rx_addr_4,
input up_rx_wr_4,
@ -372,7 +356,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_4,
input [ 1:0] up_tx_sys_clk_sel_4,
input [ 2:0] up_tx_out_clk_sel_4,
input [ 7:0] up_tx_sel_4,
input up_tx_enb_4,
input [11:0] up_tx_addr_4,
input up_tx_wr_4,
@ -400,7 +383,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_5,
input [31:0] tx_data_5,
input [ 7:0] up_es_sel_5,
input up_es_enb_5,
input [11:0] up_es_addr_5,
input up_es_wr_5,
@ -415,7 +397,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_5,
input [ 1:0] up_rx_sys_clk_sel_5,
input [ 2:0] up_rx_out_clk_sel_5,
input [ 7:0] up_rx_sel_5,
input up_rx_enb_5,
input [11:0] up_rx_addr_5,
input up_rx_wr_5,
@ -430,7 +411,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_5,
input [ 1:0] up_tx_sys_clk_sel_5,
input [ 2:0] up_tx_out_clk_sel_5,
input [ 7:0] up_tx_sel_5,
input up_tx_enb_5,
input [11:0] up_tx_addr_5,
input up_tx_wr_5,
@ -458,7 +438,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_6,
input [31:0] tx_data_6,
input [ 7:0] up_es_sel_6,
input up_es_enb_6,
input [11:0] up_es_addr_6,
input up_es_wr_6,
@ -473,7 +452,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_6,
input [ 1:0] up_rx_sys_clk_sel_6,
input [ 2:0] up_rx_out_clk_sel_6,
input [ 7:0] up_rx_sel_6,
input up_rx_enb_6,
input [11:0] up_rx_addr_6,
input up_rx_wr_6,
@ -488,7 +466,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_6,
input [ 1:0] up_tx_sys_clk_sel_6,
input [ 2:0] up_tx_out_clk_sel_6,
input [ 7:0] up_tx_sel_6,
input up_tx_enb_6,
input [11:0] up_tx_addr_6,
input up_tx_wr_6,
@ -516,7 +493,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_7,
input [31:0] tx_data_7,
input [ 7:0] up_es_sel_7,
input up_es_enb_7,
input [11:0] up_es_addr_7,
input up_es_wr_7,
@ -531,7 +507,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_7,
input [ 1:0] up_rx_sys_clk_sel_7,
input [ 2:0] up_rx_out_clk_sel_7,
input [ 7:0] up_rx_sel_7,
input up_rx_enb_7,
input [11:0] up_rx_addr_7,
input up_rx_wr_7,
@ -546,7 +521,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_7,
input [ 1:0] up_tx_sys_clk_sel_7,
input [ 2:0] up_tx_out_clk_sel_7,
input [ 7:0] up_tx_sel_7,
input up_tx_enb_7,
input [11:0] up_tx_addr_7,
input up_tx_wr_7,
@ -576,14 +550,12 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_8,
input [31:0] tx_data_8,
input [ 7:0] up_cm_sel_8,
input up_cm_enb_8,
input [11:0] up_cm_addr_8,
input up_cm_wr_8,
input [15:0] up_cm_wdata_8,
output [15:0] up_cm_rdata_8,
output up_cm_ready_8,
input [ 7:0] up_es_sel_8,
input up_es_enb_8,
input [11:0] up_es_addr_8,
input up_es_wr_8,
@ -598,7 +570,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_8,
input [ 1:0] up_rx_sys_clk_sel_8,
input [ 2:0] up_rx_out_clk_sel_8,
input [ 7:0] up_rx_sel_8,
input up_rx_enb_8,
input [11:0] up_rx_addr_8,
input up_rx_wr_8,
@ -613,7 +584,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_8,
input [ 1:0] up_tx_sys_clk_sel_8,
input [ 2:0] up_tx_out_clk_sel_8,
input [ 7:0] up_tx_sel_8,
input up_tx_enb_8,
input [11:0] up_tx_addr_8,
input up_tx_wr_8,
@ -641,7 +611,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_9,
input [31:0] tx_data_9,
input [ 7:0] up_es_sel_9,
input up_es_enb_9,
input [11:0] up_es_addr_9,
input up_es_wr_9,
@ -656,7 +625,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_9,
input [ 1:0] up_rx_sys_clk_sel_9,
input [ 2:0] up_rx_out_clk_sel_9,
input [ 7:0] up_rx_sel_9,
input up_rx_enb_9,
input [11:0] up_rx_addr_9,
input up_rx_wr_9,
@ -671,7 +639,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_9,
input [ 1:0] up_tx_sys_clk_sel_9,
input [ 2:0] up_tx_out_clk_sel_9,
input [ 7:0] up_tx_sel_9,
input up_tx_enb_9,
input [11:0] up_tx_addr_9,
input up_tx_wr_9,
@ -699,7 +666,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_10,
input [31:0] tx_data_10,
input [ 7:0] up_es_sel_10,
input up_es_enb_10,
input [11:0] up_es_addr_10,
input up_es_wr_10,
@ -714,7 +680,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_10,
input [ 1:0] up_rx_sys_clk_sel_10,
input [ 2:0] up_rx_out_clk_sel_10,
input [ 7:0] up_rx_sel_10,
input up_rx_enb_10,
input [11:0] up_rx_addr_10,
input up_rx_wr_10,
@ -729,7 +694,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_10,
input [ 1:0] up_tx_sys_clk_sel_10,
input [ 2:0] up_tx_out_clk_sel_10,
input [ 7:0] up_tx_sel_10,
input up_tx_enb_10,
input [11:0] up_tx_addr_10,
input up_tx_wr_10,
@ -757,7 +721,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_11,
input [31:0] tx_data_11,
input [ 7:0] up_es_sel_11,
input up_es_enb_11,
input [11:0] up_es_addr_11,
input up_es_wr_11,
@ -772,7 +735,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_11,
input [ 1:0] up_rx_sys_clk_sel_11,
input [ 2:0] up_rx_out_clk_sel_11,
input [ 7:0] up_rx_sel_11,
input up_rx_enb_11,
input [11:0] up_rx_addr_11,
input up_rx_wr_11,
@ -787,7 +749,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_11,
input [ 1:0] up_tx_sys_clk_sel_11,
input [ 2:0] up_tx_out_clk_sel_11,
input [ 7:0] up_tx_sel_11,
input up_tx_enb_11,
input [11:0] up_tx_addr_11,
input up_tx_wr_11,
@ -817,14 +778,12 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_12,
input [31:0] tx_data_12,
input [ 7:0] up_cm_sel_12,
input up_cm_enb_12,
input [11:0] up_cm_addr_12,
input up_cm_wr_12,
input [15:0] up_cm_wdata_12,
output [15:0] up_cm_rdata_12,
output up_cm_ready_12,
input [ 7:0] up_es_sel_12,
input up_es_enb_12,
input [11:0] up_es_addr_12,
input up_es_wr_12,
@ -839,7 +798,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_12,
input [ 1:0] up_rx_sys_clk_sel_12,
input [ 2:0] up_rx_out_clk_sel_12,
input [ 7:0] up_rx_sel_12,
input up_rx_enb_12,
input [11:0] up_rx_addr_12,
input up_rx_wr_12,
@ -854,7 +812,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_12,
input [ 1:0] up_tx_sys_clk_sel_12,
input [ 2:0] up_tx_out_clk_sel_12,
input [ 7:0] up_tx_sel_12,
input up_tx_enb_12,
input [11:0] up_tx_addr_12,
input up_tx_wr_12,
@ -882,7 +839,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_13,
input [31:0] tx_data_13,
input [ 7:0] up_es_sel_13,
input up_es_enb_13,
input [11:0] up_es_addr_13,
input up_es_wr_13,
@ -897,7 +853,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_13,
input [ 1:0] up_rx_sys_clk_sel_13,
input [ 2:0] up_rx_out_clk_sel_13,
input [ 7:0] up_rx_sel_13,
input up_rx_enb_13,
input [11:0] up_rx_addr_13,
input up_rx_wr_13,
@ -912,7 +867,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_13,
input [ 1:0] up_tx_sys_clk_sel_13,
input [ 2:0] up_tx_out_clk_sel_13,
input [ 7:0] up_tx_sel_13,
input up_tx_enb_13,
input [11:0] up_tx_addr_13,
input up_tx_wr_13,
@ -940,7 +894,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_14,
input [31:0] tx_data_14,
input [ 7:0] up_es_sel_14,
input up_es_enb_14,
input [11:0] up_es_addr_14,
input up_es_wr_14,
@ -955,7 +908,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_14,
input [ 1:0] up_rx_sys_clk_sel_14,
input [ 2:0] up_rx_out_clk_sel_14,
input [ 7:0] up_rx_sel_14,
input up_rx_enb_14,
input [11:0] up_rx_addr_14,
input up_rx_wr_14,
@ -970,7 +922,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_14,
input [ 1:0] up_tx_sys_clk_sel_14,
input [ 2:0] up_tx_out_clk_sel_14,
input [ 7:0] up_tx_sel_14,
input up_tx_enb_14,
input [11:0] up_tx_addr_14,
input up_tx_wr_14,
@ -998,7 +949,6 @@ module util_adxcvr #(
input [ 3:0] tx_charisk_15,
input [31:0] tx_data_15,
input [ 7:0] up_es_sel_15,
input up_es_enb_15,
input [11:0] up_es_addr_15,
input up_es_wr_15,
@ -1013,7 +963,6 @@ module util_adxcvr #(
input [ 2:0] up_rx_rate_15,
input [ 1:0] up_rx_sys_clk_sel_15,
input [ 2:0] up_rx_out_clk_sel_15,
input [ 7:0] up_rx_sel_15,
input up_rx_enb_15,
input [11:0] up_rx_addr_15,
input up_rx_wr_15,
@ -1028,7 +977,6 @@ module util_adxcvr #(
input [ 2:0] up_tx_rate_15,
input [ 1:0] up_tx_sys_clk_sel_15,
input [ 2:0] up_tx_out_clk_sel_15,
input [ 7:0] up_tx_sel_15,
input up_tx_enb_15,
input [11:0] up_tx_addr_15,
input up_tx_wr_15,
@ -1061,7 +1009,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 1) begin
util_adxcvr_xcm #(
.XCVR_ID (0),
.XCVR_TYPE (XCVR_TYPE),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
@ -1075,7 +1022,6 @@ module util_adxcvr #(
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_qpll_rst (up_qpll_rst_0),
.up_cm_sel (up_cm_sel_0),
.up_cm_enb (up_cm_enb_0),
.up_cm_addr (up_cm_addr_0),
.up_cm_wr (up_cm_wr_0),
@ -1094,7 +1040,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 1) begin
util_adxcvr_xch #(
.XCVR_ID (0),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1128,7 +1073,6 @@ module util_adxcvr #(
.tx_data (tx_data_0),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_0),
.up_es_enb (up_es_enb_0),
.up_es_addr (up_es_addr_0),
.up_es_wr (up_es_wr_0),
@ -1143,7 +1087,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_0),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_0),
.up_rx_out_clk_sel (up_rx_out_clk_sel_0),
.up_rx_sel (up_rx_sel_0),
.up_rx_enb (up_rx_enb_0),
.up_rx_addr (up_rx_addr_0),
.up_rx_wr (up_rx_wr_0),
@ -1158,7 +1101,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_0),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_0),
.up_tx_out_clk_sel (up_tx_out_clk_sel_0),
.up_tx_sel (up_tx_sel_0),
.up_tx_enb (up_tx_enb_0),
.up_tx_addr (up_tx_addr_0),
.up_tx_wr (up_tx_wr_0),
@ -1191,7 +1133,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 2) begin
util_adxcvr_xch #(
.XCVR_ID (1),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1225,7 +1166,6 @@ module util_adxcvr #(
.tx_data (tx_data_1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_1),
.up_es_enb (up_es_enb_1),
.up_es_addr (up_es_addr_1),
.up_es_wr (up_es_wr_1),
@ -1240,7 +1180,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_1),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_1),
.up_rx_out_clk_sel (up_rx_out_clk_sel_1),
.up_rx_sel (up_rx_sel_1),
.up_rx_enb (up_rx_enb_1),
.up_rx_addr (up_rx_addr_1),
.up_rx_wr (up_rx_wr_1),
@ -1255,7 +1194,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_1),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_1),
.up_tx_out_clk_sel (up_tx_out_clk_sel_1),
.up_tx_sel (up_tx_sel_1),
.up_tx_enb (up_tx_enb_1),
.up_tx_addr (up_tx_addr_1),
.up_tx_wr (up_tx_wr_1),
@ -1288,7 +1226,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 3) begin
util_adxcvr_xch #(
.XCVR_ID (2),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1322,7 +1259,6 @@ module util_adxcvr #(
.tx_data (tx_data_2),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_2),
.up_es_enb (up_es_enb_2),
.up_es_addr (up_es_addr_2),
.up_es_wr (up_es_wr_2),
@ -1337,7 +1273,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_2),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_2),
.up_rx_out_clk_sel (up_rx_out_clk_sel_2),
.up_rx_sel (up_rx_sel_2),
.up_rx_enb (up_rx_enb_2),
.up_rx_addr (up_rx_addr_2),
.up_rx_wr (up_rx_wr_2),
@ -1352,7 +1287,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_2),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_2),
.up_tx_out_clk_sel (up_tx_out_clk_sel_2),
.up_tx_sel (up_tx_sel_2),
.up_tx_enb (up_tx_enb_2),
.up_tx_addr (up_tx_addr_2),
.up_tx_wr (up_tx_wr_2),
@ -1385,7 +1319,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 4) begin
util_adxcvr_xch #(
.XCVR_ID (3),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1419,7 +1352,6 @@ module util_adxcvr #(
.tx_data (tx_data_3),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_3),
.up_es_enb (up_es_enb_3),
.up_es_addr (up_es_addr_3),
.up_es_wr (up_es_wr_3),
@ -1434,7 +1366,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_3),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_3),
.up_rx_out_clk_sel (up_rx_out_clk_sel_3),
.up_rx_sel (up_rx_sel_3),
.up_rx_enb (up_rx_enb_3),
.up_rx_addr (up_rx_addr_3),
.up_rx_wr (up_rx_wr_3),
@ -1449,7 +1380,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_3),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_3),
.up_tx_out_clk_sel (up_tx_out_clk_sel_3),
.up_tx_sel (up_tx_sel_3),
.up_tx_enb (up_tx_enb_3),
.up_tx_addr (up_tx_addr_3),
.up_tx_wr (up_tx_wr_3),
@ -1481,7 +1411,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 5) begin
util_adxcvr_xcm #(
.XCVR_ID (4),
.XCVR_TYPE (XCVR_TYPE),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
@ -1495,7 +1424,6 @@ module util_adxcvr #(
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_qpll_rst (up_qpll_rst_4),
.up_cm_sel (up_cm_sel_4),
.up_cm_enb (up_cm_enb_4),
.up_cm_addr (up_cm_addr_4),
.up_cm_wr (up_cm_wr_4),
@ -1514,7 +1442,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 5) begin
util_adxcvr_xch #(
.XCVR_ID (4),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1548,7 +1475,6 @@ module util_adxcvr #(
.tx_data (tx_data_4),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_4),
.up_es_enb (up_es_enb_4),
.up_es_addr (up_es_addr_4),
.up_es_wr (up_es_wr_4),
@ -1563,7 +1489,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_4),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_4),
.up_rx_out_clk_sel (up_rx_out_clk_sel_4),
.up_rx_sel (up_rx_sel_4),
.up_rx_enb (up_rx_enb_4),
.up_rx_addr (up_rx_addr_4),
.up_rx_wr (up_rx_wr_4),
@ -1578,7 +1503,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_4),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_4),
.up_tx_out_clk_sel (up_tx_out_clk_sel_4),
.up_tx_sel (up_tx_sel_4),
.up_tx_enb (up_tx_enb_4),
.up_tx_addr (up_tx_addr_4),
.up_tx_wr (up_tx_wr_4),
@ -1611,7 +1535,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 6) begin
util_adxcvr_xch #(
.XCVR_ID (5),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1645,7 +1568,6 @@ module util_adxcvr #(
.tx_data (tx_data_5),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_5),
.up_es_enb (up_es_enb_5),
.up_es_addr (up_es_addr_5),
.up_es_wr (up_es_wr_5),
@ -1660,7 +1582,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_5),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_5),
.up_rx_out_clk_sel (up_rx_out_clk_sel_5),
.up_rx_sel (up_rx_sel_5),
.up_rx_enb (up_rx_enb_5),
.up_rx_addr (up_rx_addr_5),
.up_rx_wr (up_rx_wr_5),
@ -1675,7 +1596,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_5),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_5),
.up_tx_out_clk_sel (up_tx_out_clk_sel_5),
.up_tx_sel (up_tx_sel_5),
.up_tx_enb (up_tx_enb_5),
.up_tx_addr (up_tx_addr_5),
.up_tx_wr (up_tx_wr_5),
@ -1708,7 +1628,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 7) begin
util_adxcvr_xch #(
.XCVR_ID (6),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1742,7 +1661,6 @@ module util_adxcvr #(
.tx_data (tx_data_6),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_6),
.up_es_enb (up_es_enb_6),
.up_es_addr (up_es_addr_6),
.up_es_wr (up_es_wr_6),
@ -1757,7 +1675,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_6),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_6),
.up_rx_out_clk_sel (up_rx_out_clk_sel_6),
.up_rx_sel (up_rx_sel_6),
.up_rx_enb (up_rx_enb_6),
.up_rx_addr (up_rx_addr_6),
.up_rx_wr (up_rx_wr_6),
@ -1772,7 +1689,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_6),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_6),
.up_tx_out_clk_sel (up_tx_out_clk_sel_6),
.up_tx_sel (up_tx_sel_6),
.up_tx_enb (up_tx_enb_6),
.up_tx_addr (up_tx_addr_6),
.up_tx_wr (up_tx_wr_6),
@ -1805,7 +1721,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 8) begin
util_adxcvr_xch #(
.XCVR_ID (7),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1839,7 +1754,6 @@ module util_adxcvr #(
.tx_data (tx_data_7),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_7),
.up_es_enb (up_es_enb_7),
.up_es_addr (up_es_addr_7),
.up_es_wr (up_es_wr_7),
@ -1854,7 +1768,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_7),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_7),
.up_rx_out_clk_sel (up_rx_out_clk_sel_7),
.up_rx_sel (up_rx_sel_7),
.up_rx_enb (up_rx_enb_7),
.up_rx_addr (up_rx_addr_7),
.up_rx_wr (up_rx_wr_7),
@ -1869,7 +1782,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_7),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_7),
.up_tx_out_clk_sel (up_tx_out_clk_sel_7),
.up_tx_sel (up_tx_sel_7),
.up_tx_enb (up_tx_enb_7),
.up_tx_addr (up_tx_addr_7),
.up_tx_wr (up_tx_wr_7),
@ -1901,7 +1813,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 9) begin
util_adxcvr_xcm #(
.XCVR_ID (8),
.XCVR_TYPE (XCVR_TYPE),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
@ -1915,7 +1826,6 @@ module util_adxcvr #(
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_qpll_rst (up_qpll_rst_8),
.up_cm_sel (up_cm_sel_8),
.up_cm_enb (up_cm_enb_8),
.up_cm_addr (up_cm_addr_8),
.up_cm_wr (up_cm_wr_8),
@ -1934,7 +1844,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 9) begin
util_adxcvr_xch #(
.XCVR_ID (8),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -1968,104 +1877,6 @@ module util_adxcvr #(
.tx_data (tx_data_8),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_8),
.up_es_enb (up_es_enb_8),
.up_es_addr (up_es_addr_8),
.up_es_wr (up_es_wr_8),
.up_es_wdata (up_es_wdata_8),
.up_es_rdata (up_es_rdata_8),
.up_es_ready (up_es_ready_8),
.up_rx_pll_locked (up_rx_pll_locked_8),
.up_rx_rst (up_rx_rst_8),
.up_rx_user_ready (up_rx_user_ready_8),
.up_rx_rst_done (up_rx_rst_done_8),
.up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8),
.up_rx_rate (up_rx_rate_8),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_8),
.up_rx_out_clk_sel (up_rx_out_clk_sel_8),
.up_rx_sel (up_rx_sel_8),
.up_rx_enb (up_rx_enb_8),
.up_rx_addr (up_rx_addr_8),
.up_rx_wr (up_rx_wr_8),
.up_rx_wdata (up_rx_wdata_8),
.up_rx_rdata (up_rx_rdata_8),
.up_rx_ready (up_rx_ready_8),
.up_tx_pll_locked (up_tx_pll_locked_8),
.up_tx_rst (up_tx_rst_8),
.up_tx_user_ready (up_tx_user_ready_8),
.up_tx_rst_done (up_tx_rst_done_8),
.up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8),
.up_tx_rate (up_tx_rate_8),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_8),
.up_tx_out_clk_sel (up_tx_out_clk_sel_8),
.up_tx_sel (up_tx_sel_8),
.up_tx_enb (up_tx_enb_8),
.up_tx_addr (up_tx_addr_8),
.up_tx_wr (up_tx_wr_8),
.up_tx_wdata (up_tx_wdata_8),
.up_tx_rdata (up_tx_rdata_8),
.up_tx_ready (up_tx_ready_8));
end else begin
assign rx_out_clk_8 = 1'd0;
assign rx_charisk_8 = 4'd0;
assign rx_disperr_8 = 4'd0;
assign rx_notintable_8 = 4'd0;
assign rx_data_8 = 32'd0;
assign tx_8_p = 1'd0;
assign tx_8_n = 1'd0;
assign tx_out_clk_8 = 1'd0;
assign up_es_rdata_8 = 16'd0;
assign up_es_ready_8 = 1'd0;
assign up_rx_pll_locked_8 = 1'd0;
assign up_rx_rst_done_8 = 1'd0;
assign up_rx_rdata_8 = 16'd0;
assign up_rx_ready_8 = 1'd0;
assign up_tx_pll_locked_8 = 1'd0;
assign up_tx_rst_done_8 = 1'd0;
assign up_tx_rdata_8 = 16'd0;
assign up_tx_ready_8 = 1'd0;
end
endgenerate
generate
if (NUM_OF_LANES >= 10) begin
util_adxcvr_xch #(
.XCVR_ID (9),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG))
i_xch_9 (
.qpll2ch_clk (qpll2ch_clk_8),
.qpll2ch_ref_clk (qpll2ch_ref_clk_8),
.qpll2ch_locked (qpll2ch_locked_8),
.cpll_ref_clk (cpll_ref_clk_9),
.up_cpll_rst (up_cpll_rst_9),
.rx_p (rx_9_p),
.rx_n (rx_9_n),
.rx_out_clk (rx_out_clk_9),
.rx_clk (rx_clk_9),
.rx_charisk (rx_charisk_9),
.rx_disperr (rx_disperr_9),
.rx_notintable (rx_notintable_9),
.rx_data (rx_data_9),
.rx_calign (rx_calign_9),
.tx_p (tx_9_p),
.tx_n (tx_9_n),
.tx_out_clk (tx_out_clk_9),
.tx_clk (tx_clk_9),
.tx_charisk (tx_charisk_9),
.tx_data (tx_data_9),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_9),
.up_es_enb (up_es_enb_9),
.up_es_addr (up_es_addr_9),
.up_es_wr (up_es_wr_9),
@ -2080,7 +1891,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_9),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_9),
.up_rx_out_clk_sel (up_rx_out_clk_sel_9),
.up_rx_sel (up_rx_sel_9),
.up_rx_enb (up_rx_enb_9),
.up_rx_addr (up_rx_addr_9),
.up_rx_wr (up_rx_wr_9),
@ -2095,7 +1905,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_9),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_9),
.up_tx_out_clk_sel (up_tx_out_clk_sel_9),
.up_tx_sel (up_tx_sel_9),
.up_tx_enb (up_tx_enb_9),
.up_tx_addr (up_tx_addr_9),
.up_tx_wr (up_tx_wr_9),
@ -2128,7 +1937,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 11) begin
util_adxcvr_xch #(
.XCVR_ID (10),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -2162,7 +1970,6 @@ module util_adxcvr #(
.tx_data (tx_data_10),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_10),
.up_es_enb (up_es_enb_10),
.up_es_addr (up_es_addr_10),
.up_es_wr (up_es_wr_10),
@ -2177,7 +1984,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_10),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_10),
.up_rx_out_clk_sel (up_rx_out_clk_sel_10),
.up_rx_sel (up_rx_sel_10),
.up_rx_enb (up_rx_enb_10),
.up_rx_addr (up_rx_addr_10),
.up_rx_wr (up_rx_wr_10),
@ -2192,7 +1998,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_10),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_10),
.up_tx_out_clk_sel (up_tx_out_clk_sel_10),
.up_tx_sel (up_tx_sel_10),
.up_tx_enb (up_tx_enb_10),
.up_tx_addr (up_tx_addr_10),
.up_tx_wr (up_tx_wr_10),
@ -2225,7 +2030,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 12) begin
util_adxcvr_xch #(
.XCVR_ID (11),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -2259,7 +2063,6 @@ module util_adxcvr #(
.tx_data (tx_data_11),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_11),
.up_es_enb (up_es_enb_11),
.up_es_addr (up_es_addr_11),
.up_es_wr (up_es_wr_11),
@ -2274,7 +2077,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_11),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_11),
.up_rx_out_clk_sel (up_rx_out_clk_sel_11),
.up_rx_sel (up_rx_sel_11),
.up_rx_enb (up_rx_enb_11),
.up_rx_addr (up_rx_addr_11),
.up_rx_wr (up_rx_wr_11),
@ -2289,7 +2091,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_11),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_11),
.up_tx_out_clk_sel (up_tx_out_clk_sel_11),
.up_tx_sel (up_tx_sel_11),
.up_tx_enb (up_tx_enb_11),
.up_tx_addr (up_tx_addr_11),
.up_tx_wr (up_tx_wr_11),
@ -2321,7 +2122,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 13) begin
util_adxcvr_xcm #(
.XCVR_ID (12),
.XCVR_TYPE (XCVR_TYPE),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
@ -2335,7 +2135,6 @@ module util_adxcvr #(
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_qpll_rst (up_qpll_rst_12),
.up_cm_sel (up_cm_sel_12),
.up_cm_enb (up_cm_enb_12),
.up_cm_addr (up_cm_addr_12),
.up_cm_wr (up_cm_wr_12),
@ -2354,7 +2153,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 13) begin
util_adxcvr_xch #(
.XCVR_ID (12),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -2388,7 +2186,6 @@ module util_adxcvr #(
.tx_data (tx_data_12),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_12),
.up_es_enb (up_es_enb_12),
.up_es_addr (up_es_addr_12),
.up_es_wr (up_es_wr_12),
@ -2403,7 +2200,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_12),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_12),
.up_rx_out_clk_sel (up_rx_out_clk_sel_12),
.up_rx_sel (up_rx_sel_12),
.up_rx_enb (up_rx_enb_12),
.up_rx_addr (up_rx_addr_12),
.up_rx_wr (up_rx_wr_12),
@ -2418,7 +2214,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_12),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_12),
.up_tx_out_clk_sel (up_tx_out_clk_sel_12),
.up_tx_sel (up_tx_sel_12),
.up_tx_enb (up_tx_enb_12),
.up_tx_addr (up_tx_addr_12),
.up_tx_wr (up_tx_wr_12),
@ -2451,7 +2246,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 14) begin
util_adxcvr_xch #(
.XCVR_ID (13),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -2485,7 +2279,6 @@ module util_adxcvr #(
.tx_data (tx_data_13),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_13),
.up_es_enb (up_es_enb_13),
.up_es_addr (up_es_addr_13),
.up_es_wr (up_es_wr_13),
@ -2500,7 +2293,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_13),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_13),
.up_rx_out_clk_sel (up_rx_out_clk_sel_13),
.up_rx_sel (up_rx_sel_13),
.up_rx_enb (up_rx_enb_13),
.up_rx_addr (up_rx_addr_13),
.up_rx_wr (up_rx_wr_13),
@ -2515,7 +2307,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_13),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_13),
.up_tx_out_clk_sel (up_tx_out_clk_sel_13),
.up_tx_sel (up_tx_sel_13),
.up_tx_enb (up_tx_enb_13),
.up_tx_addr (up_tx_addr_13),
.up_tx_wr (up_tx_wr_13),
@ -2548,7 +2339,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 15) begin
util_adxcvr_xch #(
.XCVR_ID (14),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -2582,7 +2372,6 @@ module util_adxcvr #(
.tx_data (tx_data_14),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_14),
.up_es_enb (up_es_enb_14),
.up_es_addr (up_es_addr_14),
.up_es_wr (up_es_wr_14),
@ -2597,7 +2386,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_14),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_14),
.up_rx_out_clk_sel (up_rx_out_clk_sel_14),
.up_rx_sel (up_rx_sel_14),
.up_rx_enb (up_rx_enb_14),
.up_rx_addr (up_rx_addr_14),
.up_rx_wr (up_rx_wr_14),
@ -2612,7 +2400,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_14),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_14),
.up_tx_out_clk_sel (up_tx_out_clk_sel_14),
.up_tx_sel (up_tx_sel_14),
.up_tx_enb (up_tx_enb_14),
.up_tx_addr (up_tx_addr_14),
.up_tx_wr (up_tx_wr_14),
@ -2645,7 +2432,6 @@ module util_adxcvr #(
generate
if (NUM_OF_LANES >= 16) begin
util_adxcvr_xch #(
.XCVR_ID (15),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
@ -2679,7 +2465,6 @@ module util_adxcvr #(
.tx_data (tx_data_15),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_sel (up_es_sel_15),
.up_es_enb (up_es_enb_15),
.up_es_addr (up_es_addr_15),
.up_es_wr (up_es_wr_15),
@ -2694,7 +2479,6 @@ module util_adxcvr #(
.up_rx_rate (up_rx_rate_15),
.up_rx_sys_clk_sel (up_rx_sys_clk_sel_15),
.up_rx_out_clk_sel (up_rx_out_clk_sel_15),
.up_rx_sel (up_rx_sel_15),
.up_rx_enb (up_rx_enb_15),
.up_rx_addr (up_rx_addr_15),
.up_rx_wr (up_rx_wr_15),
@ -2709,7 +2493,6 @@ module util_adxcvr #(
.up_tx_rate (up_tx_rate_15),
.up_tx_sys_clk_sel (up_tx_sys_clk_sel_15),
.up_tx_out_clk_sel (up_tx_out_clk_sel_15),
.up_tx_sel (up_tx_sel_15),
.up_tx_enb (up_tx_enb_15),
.up_tx_addr (up_tx_addr_15),
.up_tx_wr (up_tx_wr_15),

4
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -20,7 +20,6 @@ for {set n 0} {$n < 16} {incr n} {
if {($n%4) == 0} {
adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \
"sel up_cm_sel_${n} "\
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
@ -30,7 +29,6 @@ for {set n 0} {$n < 16} {incr n} {
}
adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \
"sel up_es_sel_${n} "\
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
@ -47,7 +45,6 @@ for {set n 0} {$n < 16} {incr n} {
"rate up_rx_rate_${n} "\
"sys_clk_sel up_rx_sys_clk_sel_${n} "\
"out_clk_sel up_rx_out_clk_sel_${n} "\
"sel up_rx_sel_${n} "\
"enb up_rx_enb_${n} "\
"addr up_rx_addr_${n} "\
"wr up_rx_wr_${n} "\
@ -64,7 +61,6 @@ for {set n 0} {$n < 16} {incr n} {
"rate up_tx_rate_${n} "\
"sys_clk_sel up_tx_sys_clk_sel_${n} "\
"out_clk_sel up_tx_out_clk_sel_${n} "\
"sel up_tx_sel_${n} "\
"enb up_tx_enb_${n} "\
"addr up_tx_addr_${n} "\
"wr up_tx_wr_${n} "\

22
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -39,7 +39,6 @@ module util_adxcvr_xch #(
// parameters
parameter integer XCVR_ID = 0,
parameter integer XCVR_TYPE = 0,
parameter integer CPLL_FBDIV = 2,
@ -89,7 +88,6 @@ module util_adxcvr_xch #(
input up_rstn,
input up_clk,
input [ 7:0] up_es_sel,
input up_es_enb,
input [11:0] up_es_addr,
input up_es_wr,
@ -104,7 +102,6 @@ module util_adxcvr_xch #(
input [ 2:0] up_rx_rate,
input [ 1:0] up_rx_sys_clk_sel,
input [ 2:0] up_rx_out_clk_sel,
input [ 7:0] up_rx_sel,
input up_rx_enb,
input [11:0] up_rx_addr,
input up_rx_wr,
@ -119,7 +116,6 @@ module util_adxcvr_xch #(
input [ 2:0] up_tx_rate,
input [ 1:0] up_tx_sys_clk_sel,
input [ 2:0] up_tx_out_clk_sel,
input [ 7:0] up_tx_sel,
input up_tx_enb,
input [11:0] up_tx_addr,
input up_tx_wr,
@ -151,9 +147,6 @@ module util_adxcvr_xch #(
// internal signals
wire up_es_enb_s;
wire up_rx_enb_s;
wire up_tx_enb_s;
wire [15:0] up_rdata_s;
wire up_ready_s;
wire [ 1:0] rx_sys_clk_sel_s;
@ -184,15 +177,6 @@ module util_adxcvr_xch #(
assign up_tx_rdata = up_tx_rdata_int;
assign up_tx_ready = up_tx_ready_int;
assign up_es_enb_s = ((up_es_sel == XCVR_ID) ||
(up_es_sel == 8'hff)) ? up_es_enb : 1'b0;
assign up_rx_enb_s = ((up_rx_sel == XCVR_ID) ||
(up_rx_sel == 8'hff)) ? up_rx_enb : 1'b0;
assign up_tx_enb_s = ((up_tx_sel == XCVR_ID) ||
(up_tx_sel == 8'hff)) ? up_tx_enb : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_rdata_int <= 15'd0;
@ -236,19 +220,19 @@ module util_adxcvr_xch #(
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
end else if (up_es_enb_s == 1'b1) begin
end else if (up_es_enb == 1'b1) begin
up_sel_int <= 3'b100;
up_enb_int <= 1'b1;
up_addr_int <= up_es_addr;
up_wr_int <= up_es_wr;
up_wdata_int <= up_es_wdata;
end else if (up_rx_enb_s == 1'b1) begin
end else if (up_rx_enb == 1'b1) begin
up_sel_int <= 3'b101;
up_enb_int <= 1'b1;
up_addr_int <= up_rx_addr;
up_wr_int <= up_rx_wr;
up_wdata_int <= up_rx_wdata;
end else if (up_tx_enb_s == 1'b1) begin
end else if (up_tx_enb == 1'b1) begin
up_sel_int <= 3'b110;
up_enb_int <= 1'b1;
up_addr_int <= up_tx_addr;

24
library/xilinx/util_adxcvr/util_adxcvr_xcm.v
View File

@ -39,7 +39,6 @@ module util_adxcvr_xcm #(
// parameters
parameter integer XCVR_ID = 0,
parameter integer XCVR_TYPE = 0,
parameter integer QPLL_REFCLK_DIV = 1,
parameter integer QPLL_FBDIV_RATIO = 1,
@ -58,7 +57,6 @@ module util_adxcvr_xcm #(
input up_rstn,
input up_clk,
input up_qpll_rst,
input [ 7:0] up_cm_sel,
input up_cm_enb,
input [11:0] up_cm_addr,
input up_cm_wr,
@ -74,6 +72,7 @@ module util_adxcvr_xcm #(
reg [15:0] up_wdata_int = 'd0;
reg [15:0] up_rdata_int = 'd0;
reg up_ready_int = 'd0;
reg up_sel_int = 'd0;
// internal signals
@ -93,21 +92,32 @@ module util_adxcvr_xcm #(
up_wdata_int <= 16'd0;
up_rdata_int <= 16'd0;
up_ready_int <= 1'd0;
up_sel_int <= 1'b0;
end else begin
if ((up_cm_sel == XCVR_ID) || (up_cm_sel == 8'hff)) begin
if (up_cm_enb == 1'b1) begin
up_enb_int <= up_cm_enb;
up_addr_int <= up_cm_addr;
up_wr_int <= up_cm_wr;
up_wdata_int <= up_cm_wdata;
up_rdata_int <= up_rdata_s;
up_ready_int <= up_ready_s;
end else begin
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 16'd0;
up_rdata_int <= 16'd0;
up_ready_int <= 1'd0;
end
if (up_cm_enb == 1'b1) begin
up_sel_int <= 1'b1;
end else if (up_ready_s == 1'b1) begin
up_sel_int <= 1'b0;
end
if (up_sel_int == 1'b1) begin
up_ready_int <= up_ready_s;
up_rdata_int <= up_rdata_s;
end else begin
up_ready_int <= 1'b0;
up_rdata_int <= 'h00;
end
end
end