zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

dac_fmc_ebz: Add initial Arria10 SoC support 

Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.

This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:

  LA01_P_CC
    R612: R0 -> DNI
    R610: DNI -> R0
  LA01_N_CC
    R613: R0 -> DNI
    R611: DNI -> R0
  LA05_P
    R621: R0 -> DNI
    R620: DNI -> R0
  LA05_N
    R633: R0 -> DNI
    R632: DNI -> R0

The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * A10SoC: 14.2 Gbps
main
Lars-Peter Clausen 2018-03-20 14:43:36 +01:00 committed by Laszlo Nagy
parent c2c78b1b73
commit 6d31a437aa
6 changed files with 722 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
projects/dac_fmc_ebz/a10soc/Makefile Normal file
View File

@ -0,0 +1,20 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := dac_fmc_ebz_a10soc
M_DEPS += ../common/dac_fmc_ebz_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl
LIB_DEPS += altera/adi_jesd204
LIB_DEPS += altera/avl_dacfifo
LIB_DEPS += axi_dmac
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += util_pack/util_upack2
include ../../scripts/project-altera.mk

48
projects/dac_fmc_ebz/a10soc/system_constr.sdc Normal file
View File

@ -0,0 +1,48 @@
#
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# In this HDL repository, there are many different and unique modules, consisting
# of various HDL (Verilog or VHDL) components. The individual modules are
# developed independently, and may be accompanied by separate and unique license
# terms.
#
# The user should read each of these license terms, and understand the
# freedoms and responsibilities that he or she has by using this source/core.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE.
#
# Redistribution and use of source or resulting binaries, with or without modification
# of this file, are permitted under one of the following two license terms:
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory
# of this repository (LICENSE_GPL2), and also online at:
# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
#
# OR
#
# 2. An ADI specific BSD license, which can be found in the top level directory
# of this repository (LICENSE_ADIBSD), and also on-line at:
# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
# This will allow to generate bit files and not release the source code,
# as long as it attaches to an ADI device.
#
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
# Maximum lane rate of 14.2 Gbps however the dacfifo does not meet the 355 MHz requirement, reducing it to 333MHz
create_clock -period "3 ns" -name tx_ref_clk [get_ports {tx_ref_clk}]
# Asynchronous GPIOs
foreach async_input {gpio_bd_i[*]} {
set_false_path -from [get_ports $async_input]
}
foreach async_output {gpio_bd_o[*] txen_0 txen_1 spi_en_n} {
set_false_path -to [get_ports $async_output]
}
derive_pll_clocks
derive_clock_uncertainty

142
projects/dac_fmc_ebz/a10soc/system_project.tcl Normal file
View File

@ -0,0 +1,142 @@
#
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# In this HDL repository, there are many different and unique modules, consisting
# of various HDL (Verilog or VHDL) components. The individual modules are
# developed independently, and may be accompanied by separate and unique license
# terms.
#
# The user should read each of these license terms, and understand the
# freedoms and responsibilities that he or she has by using this source/core.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE.
#
# Redistribution and use of source or resulting binaries, with or without modification
# of this file, are permitted under one of the following two license terms:
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory
# of this repository (LICENSE_GPL2), and also online at:
# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
#
# OR
#
# 2. An ADI specific BSD license, which can be found in the top level directory
# of this repository (LICENSE_ADIBSD), and also on-line at:
# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
# This will allow to generate bit files and not release the source code,
# as long as it attaches to an ADI device.
#
source ../../scripts/adi_env.tcl
source ../../scripts/adi_project_alt.tcl
source ../common/config.tcl
adi_project_altera dac_fmc_ebz_a10soc [list \
JESD_L [get_config_param L] \
MODE $mode \
DEVICE $device \
]
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl
# Note: This projects requires a hardware rework to function correctly.
# The rework connects FMC header pins directly to the FPGA so that they can be
# accessed by the fabric.
#
# Changes required:
# LA01_P_CC
# R612: R0 -> DNI
# R610: DNI -> R0
# LA01_N_CC
# R613: R0 -> DNI
# R611: DNI -> R0
# LA05_P
# R621: R0 -> DNI
# R620: DNI -> R0
# LA05_N
# R633: R0 -> DNI
# R632: DNI -> R0
set_location_assignment PIN_N29 -to tx_ref_clk ; ## D04 FMCA_HPC_GBTCLK0_M2C_P
set_location_assignment PIN_N28 -to "tx_ref_clk(n)" ; ## D05 FMCA_HPC_GBTCLK0_M2C_N
set_location_assignment PIN_N37 -to tx_serial_data[0] ; ## C02 FMCA_HPC_DP0_C2M_P SERDIN7_P
set_location_assignment PIN_N36 -to "tx_serial_data[0](n)"; ## C03 FMCA_HPC_DP0_C2M_N
set_location_assignment PIN_M39 -to tx_serial_data[1] ; ## A22 FMCA_HPC_DP1_C2M_P SERDIN6_P
set_location_assignment PIN_M38 -to "tx_serial_data[1](n)"; ## A23 FMCA_HPC_DP1_C2M_N
set_location_assignment PIN_L37 -to tx_serial_data[2] ; ## A26 FMCA_HPC_DP2_C2M_P SERDIN5_P
set_location_assignment PIN_L36 -to "tx_serial_data[2](n)"; ## A27 FMCA_HPC_DP2_C2M_N
set_location_assignment PIN_K39 -to tx_serial_data[3] ; ## A30 FMCA_HPC_DP3_C2M_P SERDIN4_P
set_location_assignment PIN_K38 -to "tx_serial_data[3](n)"; ## A31 FMCA_HPC_DP3_C2M_N
set_location_assignment PIN_J37 -to tx_serial_data[4] ; ## A34 FMCA_HPC_DP4_C2M_P SERDIN2_N
set_location_assignment PIN_J36 -to "tx_serial_data[4](n)"; ## A35 FMCA_HPC_DP4_C2M_N
set_location_assignment PIN_H39 -to tx_serial_data[5] ; ## A38 FMCA_HPC_DP5_C2M_P SERDIN0_N
set_location_assignment PIN_H38 -to "tx_serial_data[5](n)"; ## A39 FMCA_HPC_DP5_C2M_N
set_location_assignment PIN_G37 -to tx_serial_data[6] ; ## B36 FMCA_HPC_DP6_C2M_P SERDIN1_N
set_location_assignment PIN_G36 -to "tx_serial_data[6](n)"; ## B37 FMCA_HPC_DP6_C2M_N
set_location_assignment PIN_F39 -to tx_serial_data[7] ; ## B32 FMCA_HPC_DP7_C2M_P SERDIN3_N
set_location_assignment PIN_F38 -to "tx_serial_data[7](n)"; ## B33 FMCA_HPC_DP7_C2M_N
set_location_assignment PIN_E12 -to tx_sync ; ## D08 FMCA_HPC_LA01_P
set_location_assignment PIN_E13 -to "tx_sync(n)" ; ## D09 FMCA_HPC_LA01_N
# For AD9161/2/4-FMC-EBZ SYSREF is placed in other place
if {$device_code == 3} {
set_location_assignment PIN_C13 -to tx_sysref ; ## H07 FMCA_HPC_LA02_P
set_location_assignment PIN_D13 -to "tx_sysref(n)" ; ## H08 FMCA_HPC_LA02_N
} else {
set_location_assignment PIN_G14 -to tx_sysref ; ## G06 FMCA_HPC_LA00_P
set_location_assignment PIN_H14 -to "tx_sysref(n)" ; ## G07 FMCA_HPC_LA00_N
}
set_instance_assignment -name IO_STANDARD LVDS -to tx_ref_clk0
set_instance_assignment -name IO_STANDARD LVDS -to "tx_ref_clk0(n)"
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_serial_data
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_serial_data
set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
set_instance_assignment -name IO_STANDARD LVDS -to "tx_sync(n)"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "tx_sync(n)"
set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
set_instance_assignment -name IO_STANDARD LVDS -to "tx_sysref(n)"
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to "tx_sysref(n)"
# gpio
# For AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ, AD9152-FMC-EBZ, AD9154-FMC-EBZ
set_location_assignment PIN_A9 -to dac_txen[0] ; ## H13 FMCA_LA07_P
set_location_assignment PIN_B9 -to dac_txen[1] ; ## H14 FMCA_LA07_N
# For AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
set_location_assignment PIN_A10 -to dac_txen[2] ; ## C10 FMCA_LA06_P
set_location_assignment PIN_B10 -to dac_txen[3] ; ## C11 FMCA_LA06_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_txen[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_txen[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_txen[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to dac_txen[3]
# spi
set_location_assignment PIN_F14 -to spi_en ; ## D12 FMCA_LA05_N
set_location_assignment PIN_C14 -to spi_clk ; ## G09 FMCA_LA03_P
set_location_assignment PIN_D14 -to spi_mosi ; ## G10 FMCA_LA03_N
set_location_assignment PIN_H12 -to spi_miso ; ## H10 FMCA_LA04_P
set_location_assignment PIN_H13 -to spi_csn_dac ; ## H11 FMCA_LA04_N
set_location_assignment PIN_F13 -to spi_csn_clk ; ## D11 FMCA_LA05_P
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_en_n
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_dac
execute_flow -compile

37
projects/dac_fmc_ebz/a10soc/system_qsys.tcl Normal file
View File

@ -0,0 +1,37 @@
#
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# In this HDL repository, there are many different and unique modules, consisting
# of various HDL (Verilog or VHDL) components. The individual modules are
# developed independently, and may be accompanied by separate and unique license
# terms.
#
# The user should read each of these license terms, and understand the
# freedoms and responsibilities that he or she has by using this source/core.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE.
#
# Redistribution and use of source or resulting binaries, with or without modification
# of this file, are permitted under one of the following two license terms:
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory
# of this repository (LICENSE_GPL2), and also online at:
# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
#
# OR
#
# 2. An ADI specific BSD license, which can be found in the top level directory
# of this repository (LICENSE_ADIBSD), and also on-line at:
# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
# This will allow to generate bit files and not release the source code,
# as long as it attaches to an ADI device.
#
set dac_fifo_address_width 13
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
source ../common/dac_fmc_ebz_qsys.tcl

303
projects/dac_fmc_ebz/a10soc/system_top.v Normal file
View File

@ -0,0 +1,303 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top #(
parameter JESD_L = 4
) (
// clock and resets
input sys_clk,
input sys_resetn,
// hps-ddr4 (32)
input hps_ddr_ref_clk,
output [ 0:0] hps_ddr_clk_p,
output [ 0:0] hps_ddr_clk_n,
output [ 16:0] hps_ddr_a,
output [ 1:0] hps_ddr_ba,
output [ 0:0] hps_ddr_bg,
output [ 0:0] hps_ddr_cke,
output [ 0:0] hps_ddr_cs_n,
output [ 0:0] hps_ddr_odt,
output [ 0:0] hps_ddr_reset_n,
output [ 0:0] hps_ddr_act_n,
output [ 0:0] hps_ddr_par,
input [ 0:0] hps_ddr_alert_n,
inout [ 3:0] hps_ddr_dqs_p,
inout [ 3:0] hps_ddr_dqs_n,
inout [ 31:0] hps_ddr_dq,
inout [ 3:0] hps_ddr_dbi_n,
input hps_ddr_rzq,
// pl-ddr4
input sys_ddr_ref_clk,
output [ 0:0] sys_ddr_clk_p,
output [ 0:0] sys_ddr_clk_n,
output [ 16:0] sys_ddr_a,
output [ 1:0] sys_ddr_ba,
output [ 0:0] sys_ddr_bg,
output [ 0:0] sys_ddr_cke,
output [ 0:0] sys_ddr_cs_n,
output [ 0:0] sys_ddr_odt,
output [ 0:0] sys_ddr_reset_n,
output [ 0:0] sys_ddr_act_n,
output [ 0:0] sys_ddr_par,
input [ 0:0] sys_ddr_alert_n,
inout [ 7:0] sys_ddr_dqs_p,
inout [ 7:0] sys_ddr_dqs_n,
inout [ 63:0] sys_ddr_dq,
inout [ 7:0] sys_ddr_dbi_n,
input sys_ddr_rzq,
// hps-ethernet
input [ 0:0] hps_eth_rxclk,
input [ 0:0] hps_eth_rxctl,
input [ 3:0] hps_eth_rxd,
output [ 0:0] hps_eth_txclk,
output [ 0:0] hps_eth_txctl,
output [ 3:0] hps_eth_txd,
output [ 0:0] hps_eth_mdc,
inout [ 0:0] hps_eth_mdio,
// hps-sdio
output [ 0:0] hps_sdio_clk,
inout [ 0:0] hps_sdio_cmd,
inout [ 7:0] hps_sdio_d,
// hps-usb
input [ 0:0] hps_usb_clk,
input [ 0:0] hps_usb_dir,
input [ 0:0] hps_usb_nxt,
output [ 0:0] hps_usb_stp,
inout [ 7:0] hps_usb_d,
// hps-uart
input [ 0:0] hps_uart_rx,
output [ 0:0] hps_uart_tx,
// hps-i2c (shared w fmc-a, fmc-b)
inout [ 0:0] hps_i2c_sda,
inout [ 0:0] hps_i2c_scl,
// hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio,
// gpio (max-v-u21)
input [ 7:0] gpio_bd_i,
output [ 3:0] gpio_bd_o,
// lane interface
input tx_ref_clk,
input tx_sysref,
input tx_sync,
output [JESD_L-1:0] tx_serial_data,
// gpio
output [ 3:0] dac_txen,
// spi
output spi_en,
output spi_csn_clk,
output spi_csn_dac,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire sys_ddr_cal_success;
wire sys_ddr_cal_fail;
wire sys_hps_resetn;
wire sys_resetn_s;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 7:0] spi_csn_s;
wire dac_fifo_bypass;
// assignments
// spi_en is active ...
// ... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
// ... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
// If you are planning to build a bitstream for just one of those boards you
// can hardwire the logic level here.
//
// assign spi_en = 1'bz;
assign spi_csn_clk = spi_csn_s[0];
assign spi_csn_dac = spi_csn_s[1];
// gpio in & out are separate cores
assign dac_fifo_bypass = gpio_o[40];
assign spi_en = gpio_o[36];
assign dac_txen = gpio_o[35:32];
assign gpio_i[63:32] = 'h0;
// board stuff (max-v-u21)
assign gpio_i[31:12] = gpio_o[31:12];
assign gpio_i[11: 4] = gpio_bd_i;
assign gpio_i[ 3: 0] = gpio_o[3:0];
assign gpio_bd_o = gpio_o[3:0];
// peripheral reset
assign sys_resetn_s = sys_resetn & sys_hps_resetn;
// instantiations
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_ddr_mem_mem_ck (sys_ddr_clk_p),
.sys_ddr_mem_mem_ck_n (sys_ddr_clk_n),
.sys_ddr_mem_mem_a (sys_ddr_a),
.sys_ddr_mem_mem_act_n (sys_ddr_act_n),
.sys_ddr_mem_mem_ba (sys_ddr_ba),
.sys_ddr_mem_mem_bg (sys_ddr_bg),
.sys_ddr_mem_mem_cke (sys_ddr_cke),
.sys_ddr_mem_mem_cs_n (sys_ddr_cs_n),
.sys_ddr_mem_mem_odt (sys_ddr_odt),
.sys_ddr_mem_mem_reset_n (sys_ddr_reset_n),
.sys_ddr_mem_mem_par (sys_ddr_par),
.sys_ddr_mem_mem_alert_n (sys_ddr_alert_n),
.sys_ddr_mem_mem_dqs (sys_ddr_dqs_p),
.sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n),
.sys_ddr_mem_mem_dq (sys_ddr_dq),
.sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n),
.sys_ddr_oct_oct_rzqin (sys_ddr_rzq),
.sys_ddr_ref_clk_clk (sys_ddr_ref_clk),
.sys_ddr_status_local_cal_success (sys_ddr_cal_success),
.sys_ddr_status_local_cal_fail (sys_ddr_cal_fail),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
.sys_hps_ddr_mem_a (hps_ddr_a),
.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
.sys_hps_ddr_mem_ba (hps_ddr_ba),
.sys_hps_ddr_mem_bg (hps_ddr_bg),
.sys_hps_ddr_mem_cke (hps_ddr_cke),
.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
.sys_hps_ddr_mem_odt (hps_ddr_odt),
.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
.sys_hps_ddr_mem_par (hps_ddr_par),
.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
.sys_hps_ddr_mem_dq (hps_ddr_dq),
.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
.sys_hps_ddr_rstn_reset_n (sys_resetn),
.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
.sys_hps_out_rstn_reset_n (sys_hps_resetn),
.sys_hps_rstn_reset_n (sys_resetn),
.sys_rstn_reset_n (sys_resetn_s),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
.dac_fifo_bypass_bypass (dac_fifo_bypass),
.tx_serial_data_tx_serial_data (tx_serial_data),
.tx_ref_clk_clk (tx_ref_clk),
.tx_sync_export (tx_sync),
.tx_sysref_export (tx_sysref));
endmodule
// ***************************************************************************
// ***************************************************************************

172
projects/dac_fmc_ebz/common/dac_fmc_ebz_qsys.tcl Normal file
View File

@ -0,0 +1,172 @@
#
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# In this HDL repository, there are many different and unique modules, consisting
# of various HDL (Verilog or VHDL) components. The individual modules are
# developed independently, and may be accompanied by separate and unique license
# terms.
#
# The user should read each of these license terms, and understand the
# freedoms and responsibilities that he or she has by using this source/core.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE.
#
# Redistribution and use of source or resulting binaries, with or without modification
# of this file, are permitted under one of the following two license terms:
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory
# of this repository (LICENSE_GPL2), and also online at:
# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
#
# OR
#
# 2. An ADI specific BSD license, which can be found in the top level directory
# of this repository (LICENSE_ADIBSD), and also on-line at:
# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
# This will allow to generate bit files and not release the source code,
# as long as it attaches to an ADI device.
#
# This design supports multiple device in multiple modes. Some of them have a
# higher lane rate, some of htem have a lower lane rate.
#
# If you are building the design for a specific part in a specific mode and the
# lane rate is less than the maximum specified here you can reduce it, which
# might improve timing closure.
set MODE $ad_project_params(MODE)
set DEVICE $ad_project_params(DEVICE)
set NUM_OF_LANES $ad_project_params(JESD_L)
set DAC_DATA_WIDTH [expr $NUM_OF_LANES * 32]
set MAX_LANE_RATE 14200
set MAX_DEVICE_CLOCK [expr $MAX_LANE_RATE / 40]
proc set_instance_parameter_values {inst values} {
foreach {k v} $values {
set_instance_parameter_value $inst $k $v
}
}
proc export_interface {name export_of {type conduit} {direction end}} {
add_interface $name $type $direction
set_interface_property $name EXPORT_OF $export_of
}
# DAC JESD204 Link + PHY Layer Core
add_instance dac_jesd204_link adi_jesd204
set_instance_parameter_values dac_jesd204_link [list \
ID 0 \
TX_OR_RX_N 1 \
NUM_OF_LANES $NUM_OF_LANES \
LANE_RATE $MAX_LANE_RATE \
REFCLK_FREQUENCY $MAX_DEVICE_CLOCK \
SOFT_PCS true \
LANE_INVERT 0xf0 \
]
add_connection sys_clk.clk dac_jesd204_link.sys_clk
add_connection sys_clk.clk_reset dac_jesd204_link.sys_resetn
export_interface tx_ref_clk dac_jesd204_link.ref_clk clock source
export_interface tx_serial_data dac_jesd204_link.serial_data
export_interface tx_sysref dac_jesd204_link.sysref
export_interface tx_sync dac_jesd204_link.sync
# DAC Transport Layer Core
add_instance dac_jesd204_transport ad_ip_jesd204_tpl_dac
apply_preset dac_jesd204_transport "${DEVICE} Mode ${MODE}"
add_connection dac_jesd204_link.link_clk dac_jesd204_transport.link_clk
add_connection dac_jesd204_transport.link_data dac_jesd204_link.link_data
add_connection sys_clk.clk_reset dac_jesd204_transport.s_axi_reset
add_connection sys_clk.clk dac_jesd204_transport.s_axi_clock
# DAC channel unpack
# Propagate framer configuration to upack core
set NUM_OF_CHANNELS [get_instance_parameter_value dac_jesd204_transport NUM_CHANNELS]
set SAMPLE_DATA_WIDTH [get_instance_parameter_value dac_jesd204_transport BITS_PER_SAMPLE]
set SAMPLES_PER_CHANNEL [get_instance_parameter_value dac_jesd204_transport SAMPLES_PER_CHANNEL]
add_instance dac_upack util_upack2
set_instance_parameter_values dac_upack [list \
NUM_OF_CHANNELS $NUM_OF_CHANNELS \
SAMPLES_PER_CHANNEL $SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $SAMPLE_DATA_WIDTH \
INTERFACE_TYPE 1 \
]
add_connection dac_jesd204_link.link_clk dac_upack.clk
add_connection dac_jesd204_link.link_reset dac_upack.reset
for {set i 0} {$i < $NUM_OF_CHANNELS} {incr i} {
add_connection dac_jesd204_transport.dac_ch_$i dac_upack.dac_ch_$i
}
# DAC offload memory
ad_dacfifo_create avl_dac_fifo \
$DAC_DATA_WIDTH \
$DAC_DATA_WIDTH \
$dac_fifo_address_width
set_instance_parameter_value avl_dac_fifo DAC_DATA_WIDTH \
[expr $NUM_OF_CHANNELS * $SAMPLE_DATA_WIDTH * $SAMPLES_PER_CHANNEL]
export_interface dac_fifo_bypass avl_dac_fifo.if_bypass
add_connection dac_jesd204_link.link_clk avl_dac_fifo.if_dac_clk
add_connection dac_jesd204_link.link_reset avl_dac_fifo.if_dac_rst
add_connection dac_upack.if_packed_fifo_rd_en avl_dac_fifo.if_dac_valid
add_connection avl_dac_fifo.if_dac_data dac_upack.if_packed_fifo_rd_data
add_connection avl_dac_fifo.if_dac_dunf dac_jesd204_transport.if_dac_dunf
# DAC DMA
add_instance dac_dma axi_dmac
set_instance_parameter_values dac_dma [list \
DMA_DATA_WIDTH_SRC 128 \
DMA_DATA_WIDTH_DEST $DAC_DATA_WIDTH \
CYCLIC 1 \
DMA_TYPE_DEST 1 \
DMA_TYPE_SRC 0 \
FIFO_SIZE 16 \
HAS_AXIS_TLAST 1 \
AXI_SLICE_DEST 1 \
AXI_SLICE_SRC 1 \
]
add_connection sys_dma_clk.clk avl_dac_fifo.if_dma_clk
add_connection sys_dma_clk.clk_reset avl_dac_fifo.if_dma_rst
add_connection sys_dma_clk.clk dac_dma.if_m_axis_aclk
add_connection dac_dma.m_axis avl_dac_fifo.s_axis
add_connection dac_dma.if_m_axis_xfer_req avl_dac_fifo.if_dma_xfer_req
add_connection sys_clk.clk_reset dac_dma.s_axi_reset
add_connection sys_clk.clk dac_dma.s_axi_clock
add_connection sys_dma_clk.clk_reset dac_dma.m_src_axi_reset
add_connection sys_dma_clk.clk dac_dma.m_src_axi_clock
# addresses
ad_cpu_interconnect 0x00020000 dac_jesd204_link.link_reconfig
ad_cpu_interconnect 0x00024000 dac_jesd204_link.link_management
ad_cpu_interconnect 0x00025000 dac_jesd204_link.link_pll_reconfig
ad_cpu_interconnect 0x00026000 dac_jesd204_link.lane_pll_reconfig
for {set i 0} {$i < $NUM_OF_LANES} {incr i} {
ad_cpu_interconnect [expr 0x00028000 + $i * 0x1000] dac_jesd204_link.phy_reconfig_${i}
}
ad_cpu_interconnect 0x00030000 dac_jesd204_transport.s_axi
ad_cpu_interconnect 0x00040000 dac_dma.s_axi
# dma interconnects
ad_dma_interconnect dac_dma.m_src_axi
# interrupts
ad_cpu_interrupt 9 dac_jesd204_link.interrupt
ad_cpu_interrupt 11 dac_dma.interrupt_sender