axi_mc_current_monitor: Added CDC and reset constraints
parent
d0b2d531bc
commit
6d28d217f1
|
@ -0,0 +1,44 @@
|
|||
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set current_monitor_clk [get_clocks -of_objects [get_ports adc_clk_i]]
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *toggle_m1_reg*] \
|
||||
[get_cells -hier *toggle_m2_reg*] \
|
||||
[get_cells -hier *state_m1_reg*] \
|
||||
[get_cells -hier *state_m2_reg*]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $current_monitor_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $up_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $up_clk]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
|
|
@ -16,10 +16,14 @@ adi_ip_files axi_mc_current_monitor [list \
|
|||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"dec256sinc24b.v" \
|
||||
"ad7401.v" \
|
||||
"axi_mc_current_monitor_constr.xdc" \
|
||||
"axi_mc_current_monitor.v" ]
|
||||
|
||||
adi_ip_properties axi_mc_current_monitor
|
||||
|
||||
adi_ip_constraints axi_mc_current_monitor [list \
|
||||
"axi_mc_current_monitor_constr.xdc" ]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
|
|
Loading…
Reference in New Issue