axi_mc_current_monitor: Added CDC and reset constraints
parent
d0b2d531bc
commit
6d28d217f1
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@ -0,0 +1,44 @@
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set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set current_monitor_clk [get_clocks -of_objects [get_ports adc_clk_i]]
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set_property ASYNC_REG TRUE \
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[get_cells -hier *toggle_m1_reg*] \
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[get_cells -hier *toggle_m2_reg*] \
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[get_cells -hier *state_m1_reg*] \
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[get_cells -hier *state_m2_reg*]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $current_monitor_clk]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
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@ -16,10 +16,14 @@ adi_ip_files axi_mc_current_monitor [list \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"dec256sinc24b.v" \
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"dec256sinc24b.v" \
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"ad7401.v" \
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"ad7401.v" \
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"axi_mc_current_monitor_constr.xdc" \
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"axi_mc_current_monitor.v" ]
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"axi_mc_current_monitor.v" ]
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adi_ip_properties axi_mc_current_monitor
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adi_ip_properties axi_mc_current_monitor
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adi_ip_constraints axi_mc_current_monitor [list \
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"axi_mc_current_monitor_constr.xdc" ]
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ipx::save_core [ipx::current_core]
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ipx::save_core [ipx::current_core]
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