From 6c986d9b6a4386cd90337b60de386865e2f09772 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 20 Jul 2017 14:07:19 -0400 Subject: [PATCH] hdl/library- fix syntax errors/synthesis warnings --- library/altera/common/ad_mul.v | 1 + library/axi_ad9361/axi_ad9361.v | 1 + library/axi_ad9361/axi_ad9361_tx.v | 1 + library/axi_ad9361/axi_ad9361_tx_channel.v | 12 +- library/common/ad_dds_sine.v | 87 +++++----- library/common/ad_pnmon.v | 45 ++--- library/common/up_axi.v | 183 ++++++++++++--------- library/common/up_xfer_cntrl.v | 52 +++--- library/common/up_xfer_status.v | 46 +++--- 9 files changed, 229 insertions(+), 199 deletions(-) diff --git a/library/altera/common/ad_mul.v b/library/altera/common/ad_mul.v index 65f24e445..f479a26ca 100644 --- a/library/altera/common/ad_mul.v +++ b/library/altera/common/ad_mul.v @@ -75,6 +75,7 @@ module ad_mul #( i_lpm_mult ( .clken (1'b1), .aclr (1'b0), + .sclr (1'b0), .sum (1'b0), .clock (clk), .dataa (data_a), diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index e96c32a26..1be238c99 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -404,6 +404,7 @@ module axi_ad9361 #( .tdd_mode (tdd_mode_s), .mmcm_rst (mmcm_rst), .up_clk (up_clk), + .up_rstn (up_rstn), .up_enable (up_enable), .up_txnrx (up_txnrx), .up_adc_dld (up_adc_dld_s[6:0]), diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index d7e489aee..74f7166bc 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -344,6 +344,7 @@ module axi_ad9361_tx #( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd1), + .up_dac_ce (), .up_drp_sel (), .up_drp_wr (), .up_drp_addr (), diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v index 745d35d84..f444873b3 100644 --- a/library/axi_ad9361/axi_ad9361_tx_channel.v +++ b/library/axi_ad9361/axi_ad9361_tx_channel.v @@ -248,8 +248,8 @@ module axi_ad9361_tx_channel #( // dac iq correction - assign dac_enable = (DISABLE == 1) ? 'd0 : dac_enable_int; - assign dac_data = (DISABLE == 1) ? 'd0 : dac_data_int; + assign dac_enable = (DISABLE == 1) ? 1'd0 : dac_enable_int; + assign dac_data = (DISABLE == 1) ? 12'd0 : dac_data_int; always @(posedge dac_clk) begin dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; @@ -274,7 +274,7 @@ module axi_ad9361_tx_channel #( // dac mux - assign dac_data_out = (DISABLE == 1) ? 'd0 : dac_data_out_int; + assign dac_data_out = (DISABLE == 1) ? 12'd0 : dac_data_out_int; always @(posedge dac_clk) begin case (dac_data_sel_s) @@ -349,9 +349,9 @@ module axi_ad9361_tx_channel #( // single channel processor - assign up_wack = (DISABLE == 1) ? 'd0 : up_wack_s; - assign up_rack = (DISABLE == 1) ? 'd0 : up_rack_s; - assign up_rdata = (DISABLE == 1) ? 'd0 : up_rdata_s; + assign up_wack = (DISABLE == 1) ? 1'd0 : up_wack_s; + assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_s; + assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_s; up_dac_channel #( .CHANNEL_ID (CHANNEL_ID), diff --git a/library/common/ad_dds_sine.v b/library/common/ad_dds_sine.v index 190a9a41d..8e7a4aee4 100644 --- a/library/common/ad_dds_sine.v +++ b/library/common/ad_dds_sine.v @@ -43,52 +43,52 @@ module ad_dds_sine #( // sine = sin(angle) - input clk, - input [ 15:0] angle, - output reg [ 15:0] sine, - input [ DW:0] ddata_in, - output reg [ DW:0] ddata_out); - - localparam DW = DELAY_DATA_WIDTH - 1; + input clk, + input [15:0] angle, + output [15:0] sine, + input [(DELAY_DATA_WIDTH-1):0] ddata_in, + output [(DELAY_DATA_WIDTH-1):0] ddata_out); // internal registers - reg [ 33:0] s1_data_p = 'd0; - reg [ 33:0] s1_data_n = 'd0; - reg [ 15:0] s1_angle = 'd0; - reg [ DW:0] s1_ddata = 'd0; - reg [ 18:0] s2_data_0 = 'd0; - reg [ 18:0] s2_data_1 = 'd0; - reg [ DW:0] s2_ddata = 'd0; - reg [ 18:0] s3_data = 'd0; - reg [ DW:0] s3_ddata = 'd0; - reg [ 33:0] s4_data2_p = 'd0; - reg [ 33:0] s4_data2_n = 'd0; - reg [ 16:0] s4_data1_p = 'd0; - reg [ 16:0] s4_data1_n = 'd0; - reg [ DW:0] s4_ddata = 'd0; - reg [ 16:0] s5_data2_0 = 'd0; - reg [ 16:0] s5_data2_1 = 'd0; - reg [ 16:0] s5_data1 = 'd0; - reg [ DW:0] s5_ddata = 'd0; - reg [ 16:0] s6_data2 = 'd0; - reg [ 16:0] s6_data1 = 'd0; - reg [ DW:0] s6_ddata = 'd0; - reg [ 33:0] s7_data = 'd0; - reg [ DW:0] s7_ddata = 'd0; + reg [33:0] s1_data_p = 'd0; + reg [33:0] s1_data_n = 'd0; + reg [15:0] s1_angle = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s1_ddata = 'd0; + reg [18:0] s2_data_0 = 'd0; + reg [18:0] s2_data_1 = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s2_ddata = 'd0; + reg [18:0] s3_data = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s3_ddata = 'd0; + reg [33:0] s4_data2_p = 'd0; + reg [33:0] s4_data2_n = 'd0; + reg [16:0] s4_data1_p = 'd0; + reg [16:0] s4_data1_n = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s4_ddata = 'd0; + reg [16:0] s5_data2_0 = 'd0; + reg [16:0] s5_data2_1 = 'd0; + reg [16:0] s5_data1 = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s5_ddata = 'd0; + reg [16:0] s6_data2 = 'd0; + reg [16:0] s6_data1 = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s6_ddata = 'd0; + reg [33:0] s7_data = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s7_ddata = 'd0; + reg [15:0] sine_int = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] ddata_out_int = 'd0; // internal signals - wire [ 15:0] angle_s; - wire [ 33:0] s1_data_s; - wire [ DW:0] s1_ddata_s; - wire [ 15:0] s1_angle_s; - wire [ 33:0] s4_data2_s; - wire [ DW:0] s4_ddata_s; - wire [ 16:0] s4_data1_s; - wire [ 33:0] s7_data2_s; - wire [ 33:0] s7_data1_s; - wire [ DW:0] s7_ddata_s; + wire [15:0] angle_s; + wire [33:0] s1_data_s; + wire [(DELAY_DATA_WIDTH-1):0] s1_ddata_s; + wire [15:0] s1_angle_s; + wire [33:0] s4_data2_s; + wire [(DELAY_DATA_WIDTH-1):0] s4_ddata_s; + wire [16:0] s4_data1_s; + wire [33:0] s7_data2_s; + wire [33:0] s7_data1_s; + wire [(DELAY_DATA_WIDTH-1):0] s7_ddata_s; // make angle 2's complement @@ -192,9 +192,12 @@ module ad_dds_sine #( // output registers + assign sine = sine_int; + assign ddata_out = ddata_out_int; + always @(posedge clk) begin - sine <= s7_data[30:15]; - ddata_out <= s7_ddata; + sine_int <= s7_data[30:15]; + ddata_out_int <= s7_ddata; end endmodule diff --git a/library/common/ad_pnmon.v b/library/common/ad_pnmon.v index b57372991..f413dab93 100644 --- a/library/common/ad_pnmon.v +++ b/library/common/ad_pnmon.v @@ -42,51 +42,54 @@ module ad_pnmon #( // adc interface - input adc_clk, - input adc_valid_in, - input [DW:0] adc_data_in, - input [DW:0] adc_data_pn, + input adc_clk, + input adc_valid_in, + input [(DATA_WIDTH-1):0] adc_data_in, + input [(DATA_WIDTH-1):0] adc_data_pn, // pn out of sync and error - output reg adc_pn_oos, - output reg adc_pn_err); - - localparam DW = DATA_WIDTH - 1; + output adc_pn_oos, + output adc_pn_err); // internal registers - reg adc_valid_d = 'd0; - reg adc_pn_match_d = 'd0; - reg adc_pn_match_z = 'd0; - reg [ 3:0] adc_pn_oos_count = 'd0; + reg adc_valid_d = 'd0; + reg adc_pn_match_d = 'd0; + reg adc_pn_match_z = 'd0; + reg adc_pn_oos_int = 'd0; + reg adc_pn_err_int = 'd0; + reg [ 3:0] adc_pn_oos_count = 'd0; // internal signals - wire adc_pn_match_d_s; - wire adc_pn_match_z_s; - wire adc_pn_match_s; - wire adc_pn_update_s; - wire adc_pn_err_s; + wire adc_pn_match_d_s; + wire adc_pn_match_z_s; + wire adc_pn_match_s; + wire adc_pn_update_s; + wire adc_pn_err_s; // make sure data is not 0, sequence will fail. assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0; assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1; assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z; - assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s); - assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s); + assign adc_pn_update_s = ~(adc_pn_oos_int ^ adc_pn_match_s); + assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s); // pn oos and counters (16 to clear and set). + assign adc_pn_oos = adc_pn_oos_int; + assign adc_pn_err = adc_pn_err_int; + always @(posedge adc_clk) begin adc_valid_d <= adc_valid_in; adc_pn_match_d <= adc_pn_match_d_s; adc_pn_match_z <= adc_pn_match_z_s; if (adc_valid_d == 1'b1) begin - adc_pn_err <= adc_pn_err_s; + adc_pn_err_int <= adc_pn_err_s; if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin - adc_pn_oos <= ~adc_pn_oos; + adc_pn_oos_int <= ~adc_pn_oos_int; end if (adc_pn_update_s == 1'b1) begin adc_pn_oos_count <= adc_pn_oos_count + 1'b1; diff --git a/library/common/up_axi.v b/library/common/up_axi.v index df2f01eca..d7dad927f 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -42,117 +42,131 @@ module up_axi #( // reset and clocks - input up_rstn, - input up_clk, + input up_rstn, + input up_clk, // axi4 interface - input up_axi_awvalid, - input [AXI_AW:0] up_axi_awaddr, - output reg up_axi_awready, - input up_axi_wvalid, - input [31:0] up_axi_wdata, - input [ 3:0] up_axi_wstrb, - output reg up_axi_wready, - output reg up_axi_bvalid, - output [ 1:0] up_axi_bresp, - input up_axi_bready, - input up_axi_arvalid, - input [AXI_AW:0] up_axi_araddr, - output reg up_axi_arready, - output reg up_axi_rvalid, - output [ 1:0] up_axi_rresp, - output reg [31:0] up_axi_rdata, - input up_axi_rready, + input up_axi_awvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr, + output up_axi_awready, + input up_axi_wvalid, + input [31:0] up_axi_wdata, + input [ 3:0] up_axi_wstrb, + output up_axi_wready, + output up_axi_bvalid, + output [ 1:0] up_axi_bresp, + input up_axi_bready, + input up_axi_arvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr, + output up_axi_arready, + output up_axi_rvalid, + output [ 1:0] up_axi_rresp, + output [31:0] up_axi_rdata, + input up_axi_rready, // pcore interface - output reg up_wreq, - output reg [AW:0] up_waddr, - output reg [31:0] up_wdata, - input up_wack, - output reg up_rreq, - output reg [AW:0] up_raddr, - input [31:0] up_rdata, - input up_rack); - - localparam AXI_AW = AXI_ADDRESS_WIDTH - 1; - localparam AW = ADDRESS_WIDTH - 1; + output up_wreq, + output [(ADDRESS_WIDTH-1):0] up_waddr, + output [31:0] up_wdata, + input up_wack, + output up_rreq, + output [(ADDRESS_WIDTH-1):0] up_raddr, + input [31:0] up_rdata, + input up_rack); // internal registers - reg up_wack_d = 'd0; - reg up_wsel = 'd0; - reg [ 4:0] up_wcount = 'd0; - reg up_rack_d = 'd0; - reg [31:0] up_rdata_d = 'd0; - reg up_rsel = 'd0; - reg [ 4:0] up_rcount = 'd0; + reg up_axi_awready_int = 'd0; + reg up_axi_wready_int = 'd0; + reg up_axi_bvalid_int = 'd0; + reg up_wack_d = 'd0; + reg up_wsel = 'd0; + reg up_wreq_int = 'd0; + reg [(ADDRESS_WIDTH-1):0] up_waddr_int = 'd0; + reg [31:0] up_wdata_int = 'd0; + reg [ 4:0] up_wcount = 'd0; + reg up_axi_arready_int = 'd0; + reg up_axi_rvalid_int = 'd0; + reg [31:0] up_axi_rdata_int = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg up_rsel = 'd0; + reg up_rreq_int = 'd0; + reg [(ADDRESS_WIDTH-1):0] up_raddr_int = 'd0; + reg [ 4:0] up_rcount = 'd0; // internal signals - wire up_wack_s; - wire up_rack_s; - wire [31:0] up_rdata_s; + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; // write channel interface + assign up_axi_awready = up_axi_awready_int; + assign up_axi_wready = up_axi_wready_int; + assign up_axi_bvalid = up_axi_bvalid_int; assign up_axi_bresp = 2'd0; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin - up_axi_awready <= 'd0; - up_axi_wready <= 'd0; - up_axi_bvalid <= 'd0; + up_axi_awready_int <= 'd0; + up_axi_wready_int <= 'd0; + up_axi_bvalid_int <= 'd0; end else begin - if (up_axi_awready == 1'b1) begin - up_axi_awready <= 1'b0; + if (up_axi_awready_int == 1'b1) begin + up_axi_awready_int <= 1'b0; end else if (up_wack_s == 1'b1) begin - up_axi_awready <= 1'b1; + up_axi_awready_int <= 1'b1; end - if (up_axi_wready == 1'b1) begin - up_axi_wready <= 1'b0; + if (up_axi_wready_int == 1'b1) begin + up_axi_wready_int <= 1'b0; end else if (up_wack_s == 1'b1) begin - up_axi_wready <= 1'b1; + up_axi_wready_int <= 1'b1; end - if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin - up_axi_bvalid <= 1'b0; + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_axi_bvalid_int <= 1'b0; end else if (up_wack_d == 1'b1) begin - up_axi_bvalid <= 1'b1; + up_axi_bvalid_int <= 1'b1; end end end + assign up_wreq = up_wreq_int; + assign up_waddr = up_waddr_int; + assign up_wdata = up_wdata_int; assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin up_wack_d <= 'd0; up_wsel <= 'd0; - up_wreq <= 'd0; - up_waddr <= 'd0; - up_wdata <= 'd0; + up_wreq_int <= 'd0; + up_waddr_int <= 'd0; + up_wdata_int <= 'd0; up_wcount <= 'd0; end else begin up_wack_d <= up_wack_s; if (up_wsel == 1'b1) begin - if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin up_wsel <= 1'b0; end - up_wreq <= 1'b0; - up_waddr <= up_waddr; - up_wdata <= up_wdata; + up_wreq_int <= 1'b0; + up_waddr_int <= up_waddr_int; + up_wdata_int <= up_wdata_int; end else begin up_wsel <= up_axi_awvalid & up_axi_wvalid; - up_wreq <= up_axi_awvalid & up_axi_wvalid; - up_waddr <= up_axi_awaddr[AW+2:2]; - up_wdata <= up_axi_wdata; + up_wreq_int <= up_axi_awvalid & up_axi_wvalid; + up_waddr_int <= up_axi_awaddr[(ADDRESS_WIDTH+1):2]; + up_wdata_int <= up_axi_wdata; end if (up_wack_s == 1'b1) begin up_wcount <= 5'h00; end else if (up_wcount[4] == 1'b1) begin up_wcount <= up_wcount + 1'b1; - end else if (up_wreq == 1'b1) begin + end else if (up_wreq_int == 1'b1) begin up_wcount <= 5'h10; end end @@ -160,29 +174,34 @@ module up_axi #( // read channel interface + assign up_axi_arready = up_axi_arready_int; + assign up_axi_rvalid = up_axi_rvalid_int; + assign up_axi_rdata = up_axi_rdata_int; assign up_axi_rresp = 2'd0; always @(negedge up_rstn or posedge up_clk) begin if (up_rstn == 1'b0) begin - up_axi_arready <= 'd0; - up_axi_rvalid <= 'd0; - up_axi_rdata <= 'd0; + up_axi_arready_int <= 'd0; + up_axi_rvalid_int <= 'd0; + up_axi_rdata_int <= 'd0; end else begin - if (up_axi_arready == 1'b1) begin - up_axi_arready <= 1'b0; + if (up_axi_arready_int == 1'b1) begin + up_axi_arready_int <= 1'b0; end else if (up_rack_s == 1'b1) begin - up_axi_arready <= 1'b1; + up_axi_arready_int <= 1'b1; end - if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin - up_axi_rvalid <= 1'b0; - up_axi_rdata <= 32'd0; + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_axi_rvalid_int <= 1'b0; + up_axi_rdata_int <= 32'd0; end else if (up_rack_d == 1'b1) begin - up_axi_rvalid <= 1'b1; - up_axi_rdata <= up_rdata_d; + up_axi_rvalid_int <= 1'b1; + up_axi_rdata_int <= up_rdata_d; end end end + assign up_rreq = up_rreq_int; + assign up_raddr = up_raddr_int; assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; @@ -191,28 +210,28 @@ module up_axi #( up_rack_d <= 'd0; up_rdata_d <= 'd0; up_rsel <= 'd0; - up_rreq <= 'd0; - up_raddr <= 'd0; + up_rreq_int <= 'd0; + up_raddr_int <= 'd0; up_rcount <= 'd0; end else begin up_rack_d <= up_rack_s; up_rdata_d <= up_rdata_s; if (up_rsel == 1'b1) begin - if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin up_rsel <= 1'b0; end - up_rreq <= 1'b0; - up_raddr <= up_raddr; + up_rreq_int <= 1'b0; + up_raddr_int <= up_raddr_int; end else begin up_rsel <= up_axi_arvalid; - up_rreq <= up_axi_arvalid; - up_raddr <= up_axi_araddr[AW+2:2]; + up_rreq_int <= up_axi_arvalid; + up_raddr_int <= up_axi_araddr[(ADDRESS_WIDTH+1):2]; end if (up_rack_s == 1'b1) begin up_rcount <= 5'h00; end else if (up_rcount[4] == 1'b1) begin up_rcount <= up_rcount + 1'b1; - end else if (up_rreq == 1'b1) begin + end else if (up_rreq_int == 1'b1) begin up_rcount <= 5'h10; end end diff --git a/library/common/up_xfer_cntrl.v b/library/common/up_xfer_cntrl.v index 27e607b4f..19dc07d88 100644 --- a/library/common/up_xfer_cntrl.v +++ b/library/common/up_xfer_cntrl.v @@ -41,39 +41,40 @@ module up_xfer_cntrl #( // up interface - input up_rstn, - input up_clk, - input [DW:0] up_data_cntrl, - output reg up_xfer_done, + input up_rstn, + input up_clk, + input [(DATA_WIDTH-1):0] up_data_cntrl, + output up_xfer_done, // device interface - input d_rst, - input d_clk, - output reg [DW:0] d_data_cntrl); - - localparam DW = DATA_WIDTH - 1; + input d_rst, + input d_clk, + output [(DATA_WIDTH-1):0] d_data_cntrl); // internal registers - reg up_xfer_state_m1 = 'd0; - reg up_xfer_state_m2 = 'd0; - reg up_xfer_state = 'd0; - reg [ 5:0] up_xfer_count = 'd0; - reg up_xfer_toggle = 'd0; - reg [DW:0] up_xfer_data = 'd0; - reg d_xfer_toggle_m1 = 'd0; - reg d_xfer_toggle_m2 = 'd0; - reg d_xfer_toggle_m3 = 'd0; - reg d_xfer_toggle = 'd0; + reg up_xfer_state_m1 = 'd0; + reg up_xfer_state_m2 = 'd0; + reg up_xfer_state = 'd0; + reg [ 5:0] up_xfer_count = 'd0; + reg up_xfer_done_int = 'd0; + reg up_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] up_xfer_data = 'd0; + reg d_xfer_toggle_m1 = 'd0; + reg d_xfer_toggle_m2 = 'd0; + reg d_xfer_toggle_m3 = 'd0; + reg d_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] d_data_cntrl_int = 'd0; // internal signals - wire up_xfer_enable_s; - wire d_xfer_toggle_s; + wire up_xfer_enable_s; + wire d_xfer_toggle_s; // device control transfer + assign up_xfer_done = up_xfer_done_int; assign up_xfer_enable_s = up_xfer_state ^ up_xfer_toggle; always @(negedge up_rstn or posedge up_clk) begin @@ -82,7 +83,7 @@ module up_xfer_cntrl #( up_xfer_state_m2 <= 'd0; up_xfer_state <= 'd0; up_xfer_count <= 'd0; - up_xfer_done <= 'd0; + up_xfer_done_int <= 'd0; up_xfer_toggle <= 'd0; up_xfer_data <= 'd0; end else begin @@ -90,7 +91,7 @@ module up_xfer_cntrl #( up_xfer_state_m2 <= up_xfer_state_m1; up_xfer_state <= up_xfer_state_m2; up_xfer_count <= up_xfer_count + 1'd1; - up_xfer_done <= (up_xfer_count == 6'd1) ? ~up_xfer_enable_s : 1'b0; + up_xfer_done_int <= (up_xfer_count == 6'd1) ? ~up_xfer_enable_s : 1'b0; if ((up_xfer_count == 6'd1) && (up_xfer_enable_s == 1'b0)) begin up_xfer_toggle <= ~up_xfer_toggle; up_xfer_data <= up_data_cntrl; @@ -98,6 +99,7 @@ module up_xfer_cntrl #( end end + assign d_data_cntrl = d_data_cntrl_int; assign d_xfer_toggle_s = d_xfer_toggle_m3 ^ d_xfer_toggle_m2; always @(posedge d_clk or posedge d_rst) begin @@ -106,14 +108,14 @@ module up_xfer_cntrl #( d_xfer_toggle_m2 <= 'd0; d_xfer_toggle_m3 <= 'd0; d_xfer_toggle <= 'd0; - d_data_cntrl <= 'd0; + d_data_cntrl_int <= 'd0; end else begin d_xfer_toggle_m1 <= up_xfer_toggle; d_xfer_toggle_m2 <= d_xfer_toggle_m1; d_xfer_toggle_m3 <= d_xfer_toggle_m2; d_xfer_toggle <= d_xfer_toggle_m3; if (d_xfer_toggle_s == 1'b1) begin - d_data_cntrl <= up_xfer_data; + d_data_cntrl_int <= up_xfer_data; end end end diff --git a/library/common/up_xfer_status.v b/library/common/up_xfer_status.v index 047526a7a..85799827f 100644 --- a/library/common/up_xfer_status.v +++ b/library/common/up_xfer_status.v @@ -41,36 +41,35 @@ module up_xfer_status #( // up interface - input up_rstn, - input up_clk, - output reg [DW:0] up_data_status, + input up_rstn, + input up_clk, + output [(DATA_WIDTH-1):0] up_data_status, // device interface - input d_rst, - input d_clk, - input [DW:0] d_data_status); - - localparam DW = DATA_WIDTH - 1; + input d_rst, + input d_clk, + input [(DATA_WIDTH-1):0] d_data_status); // internal registers - reg d_xfer_state_m1 = 'd0; - reg d_xfer_state_m2 = 'd0; - reg d_xfer_state = 'd0; - reg [ 5:0] d_xfer_count = 'd0; - reg d_xfer_toggle = 'd0; - reg [DW:0] d_xfer_data = 'd0; - reg [DW:0] d_acc_data = 'd0; - reg up_xfer_toggle_m1 = 'd0; - reg up_xfer_toggle_m2 = 'd0; - reg up_xfer_toggle_m3 = 'd0; - reg up_xfer_toggle = 'd0; + reg d_xfer_state_m1 = 'd0; + reg d_xfer_state_m2 = 'd0; + reg d_xfer_state = 'd0; + reg [ 5:0] d_xfer_count = 'd0; + reg d_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] d_xfer_data = 'd0; + reg [(DATA_WIDTH-1):0] d_acc_data = 'd0; + reg up_xfer_toggle_m1 = 'd0; + reg up_xfer_toggle_m2 = 'd0; + reg up_xfer_toggle_m3 = 'd0; + reg up_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] up_data_status_int = 'd0; // internal signals - wire d_xfer_enable_s; - wire up_xfer_toggle_s; + wire d_xfer_enable_s; + wire up_xfer_toggle_s; // device status transfer @@ -102,6 +101,7 @@ module up_xfer_status #( end end + assign up_data_status = up_data_status_int; assign up_xfer_toggle_s = up_xfer_toggle_m3 ^ up_xfer_toggle_m2; always @(negedge up_rstn or posedge up_clk) begin @@ -110,14 +110,14 @@ module up_xfer_status #( up_xfer_toggle_m2 <= 'd0; up_xfer_toggle_m3 <= 'd0; up_xfer_toggle <= 'd0; - up_data_status <= 'd0; + up_data_status_int <= 'd0; end else begin up_xfer_toggle_m1 <= d_xfer_toggle; up_xfer_toggle_m2 <= up_xfer_toggle_m1; up_xfer_toggle_m3 <= up_xfer_toggle_m2; up_xfer_toggle <= up_xfer_toggle_m3; if (up_xfer_toggle_s == 1'b1) begin - up_data_status <= d_xfer_data; + up_data_status_int <= d_xfer_data; end end end