daq3: Drop explicit axi_dmac clock synchronicity configuration
The axi_dmac core is now capable of detecting whether its different parts run in different clock domains or not. No need to configure it manually any more. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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7184827d68
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6c7316fbd0
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@ -27,7 +27,6 @@ set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.ID {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma
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@ -52,7 +51,6 @@ set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.ID {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
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