From 6c58a8d1abf9b0fbff05b57cead8e387e35e851f Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 30 Sep 2021 13:45:30 +0100 Subject: [PATCH] ad9081_fmca_ebz/common: Add Versal transceiver support --- .../common/ad9081_fmca_ebz_bd.tcl | 159 ++++++++++++---- .../common/versal_transceiver.tcl | 174 ++++++++++++++++++ 2 files changed, 297 insertions(+), 36 deletions(-) create mode 100644 projects/ad9081_fmca_ebz/common/versal_transceiver.tcl diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl index e7445d806..95c7e27dc 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl @@ -11,8 +11,11 @@ # [RX/TX]_JESD_NP : Number of bits per sample # [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices # +if {![info exists ADI_PHY_SEL]} { + set ADI_PHY_SEL 1 +} -source ../../common/xilinx/data_offload_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl # Common parameter for TX and RX set JESD_MODE $ad_project_params(JESD_MODE) @@ -120,15 +123,23 @@ create_bd_port -dir I rx_device_clk create_bd_port -dir I tx_device_clk # common xcvr -ad_ip_instance util_adxcvr util_mxfe_xcvr -ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV_4_5 5 -ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES -ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES -ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1 -ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL -ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE -ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE +if {$ADI_PHY_SEL == 1} { + ad_ip_instance util_adxcvr util_mxfe_xcvr + ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV_4_5 5 + ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1 + ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE + ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE +} else { + source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl + create_bd_cell -type container -reference jesd_phy jesd204_phy + +} + +if {$ADI_PHY_SEL == 1} { ad_ip_instance axi_adxcvr axi_mxfe_rx_xcvr ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.ID 0 ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL @@ -145,6 +156,18 @@ ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_OR_RX_N 1 ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.QPLL_ENABLE 1 ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 +} + +if {$ADI_PHY_SEL == 0} { + # reset generator + ad_ip_instance proc_sys_reset rx_device_clk_rstgen + ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn rx_device_clk_rstgen/ext_reset_in + + ad_ip_instance proc_sys_reset tx_device_clk_rstgen + ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk + ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in +} # adc peripherals @@ -243,27 +266,83 @@ ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width create_bd_port -dir I ref_clk_q0 create_bd_port -dir I ref_clk_q1 -for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} { - set quad_index [expr int($i / 4)] - ad_xcvrpll ref_clk_q$quad_index util_mxfe_xcvr/cpll_ref_clk_$i - if {[expr $i % 4] == 0} { - ad_xcvrpll ref_clk_q$quad_index util_mxfe_xcvr/qpll_ref_clk_$i +if {$ADI_PHY_SEL == 1} { + for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} { + set quad_index [expr int($i / 4)] + ad_xcvrpll ref_clk_q$quad_index util_mxfe_xcvr/cpll_ref_clk_$i + if {[expr $i % 4] == 0} { + ad_xcvrpll ref_clk_q$quad_index util_mxfe_xcvr/qpll_ref_clk_$i + } } + + ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_* + ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_* + + ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn + ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk + + # connections (adc) + + ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk + + # connections (dac) + ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk +} else { + + make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/gt_bridge_ip_0_diff_gt_ref_clock] + + + set rx_link_clock jesd204_phy/rxusrclk_gt_bridge_ip_0 + set tx_link_clock jesd204_phy/txusrclk_gt_bridge_ip_0 + + # Connect PHY to Link Layer + for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} { + ad_ip_instance jesd204_versal_gt_adapter_tx tx_adapt_${j} + ad_connect axi_mxfe_tx_jesd/tx_phy${j} tx_adapt_${j}/TX + ad_connect tx_adapt_${j}/txdata jesd204_phy/ch${j}_txdata_ext + ad_connect tx_adapt_${j}/txheader jesd204_phy/ch${j}_txheader_ext + + ad_ip_instance jesd204_versal_gt_adapter_rx rx_adapt_${j} + ad_connect axi_mxfe_rx_jesd/rx_phy${j} rx_adapt_${j}/RX + ad_connect rx_adapt_${j}/rxdata jesd204_phy/ch${j}_rxdata_ext + ad_connect rx_adapt_${j}/rxheader jesd204_phy/ch${j}_rxheader_ext + ad_connect rx_adapt_${j}/rxheadervalid jesd204_phy/ch${j}_rxheadervalid_ext + ad_connect rx_adapt_${j}/rxgearboxslip jesd204_phy/ch${j}_rxgearboxslip_ext + + # link clock to adapter + ad_connect $rx_link_clock rx_adapt_${j}/usr_clk + ad_connect $tx_link_clock tx_adapt_${j}/usr_clk + } + + ad_connect $sys_cpu_clk jesd204_phy/apb3clk_quad + ad_connect $sys_cpu_clk jesd204_phy/apb3clk_gt_bridge_ip_0 + + ad_connect GND jesd204_phy/rate_sel_gt_bridge_ip_0 + + ad_connect GND jesd204_phy/reset_rx_pll_and_datapath_in + ad_connect GND jesd204_phy/reset_tx_pll_and_datapath_in + + ad_connect GND jesd204_phy/gt_reset_gt_bridge_ip_0 + + ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_datapath_in + ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_datapath_in + + ad_connect $rx_link_clock /axi_mxfe_rx_jesd/link_clk + ad_connect rx_device_clk /axi_mxfe_rx_jesd/device_clk + ad_connect $tx_link_clock /axi_mxfe_tx_jesd/link_clk + ad_connect tx_device_clk /axi_mxfe_tx_jesd/device_clk + + create_bd_port -dir I rx_sysref_0 + create_bd_port -dir I tx_sysref_0 + + ad_connect axi_mxfe_rx_jesd/sysref rx_sysref_0 + ad_connect axi_mxfe_tx_jesd/sysref tx_sysref_0 + + create_bd_port -dir O rx_sync_0 + create_bd_port -dir I tx_sync_0 + } -ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_* -ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_* - -ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn -ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk - -# connections (adc) - -ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk - -# connections (dac) -ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk - # device clock domain ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk ad_connect rx_device_clk util_mxfe_cpack/clk @@ -340,8 +419,10 @@ ad_connect $adc_data_offload_name/init_req axi_mxfe_rx_dma/s_axis_xfer_req ad_connect tx_mxfe_tpl_core/dac_dunf GND # interconnect (cpu) +if {$ADI_PHY_SEL == 1} { ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr ad_cpu_interconnect 0x44b60000 axi_mxfe_tx_xcvr +} ad_cpu_interconnect 0x44a10000 rx_mxfe_tpl_core ad_cpu_interconnect 0x44b10000 tx_mxfe_tpl_core ad_cpu_interconnect 0x44a90000 axi_mxfe_rx_jesd @@ -354,7 +435,9 @@ ad_cpu_interconnect 0x7c450000 $adc_data_offload_name # interconnect (gt/adc) +if {$ADI_PHY_SEL == 1} { ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi +} ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect $sys_cpu_clk axi_mxfe_rx_dma/m_dest_axi ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 @@ -367,15 +450,19 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq -# Create dummy outputs for unused Tx lanes -for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} { - create_bd_port -dir O tx_data_${i}_n - create_bd_port -dir O tx_data_${i}_p -} -# Create dummy outputs for unused Rx lanes -for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} { - create_bd_port -dir I rx_data_${i}_n - create_bd_port -dir I rx_data_${i}_p +if {$ADI_PHY_SEL == 1} { + # Create dummy outputs for unused Tx lanes + for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} { + create_bd_port -dir O tx_data_${i}_n + create_bd_port -dir O tx_data_${i}_p + } + # Create dummy outputs for unused Rx lanes + for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} { + create_bd_port -dir I rx_data_${i}_n + create_bd_port -dir I rx_data_${i}_p + } +} else { + make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial] } if {$TDD_SUPPORT} { diff --git a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl new file mode 100644 index 000000000..79423d37d --- /dev/null +++ b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl @@ -0,0 +1,174 @@ + +set top_design [current_bd_design] + +create_bd_design "jesd_phy" + +create_bd_cell -type ip -vlnv xilinx.com:ip:gt_bridge_ip:1.1 gt_bridge_ip_0 + +set_property -dict [list \ + CONFIG.BYPASS_MODE {true} \ + CONFIG.IP_PRESET {GTY-JESD204_64B66B} \ + CONFIG.IP_LR0_SETTINGS { \ + PRESET GTY-JESD204_64B66B \ + INTERNAL_PRESET JESD204_64B66B \ + GT_TYPE GTY \ + GT_DIRECTION DUPLEX \ + TX_LINE_RATE 24.75 \ + TX_PLL_TYPE LCPLL \ + TX_REFCLK_FREQUENCY 375 \ + TX_ACTUAL_REFCLK_FREQUENCY 375.000000000000 \ + TX_FRACN_ENABLED true \ + TX_FRACN_NUMERATOR 0 \ + TX_REFCLK_SOURCE R0 \ + TX_DATA_ENCODING 64B66B_ASYNC \ + TX_USER_DATA_WIDTH 64 \ + TX_INT_DATA_WIDTH 64 \ + TX_BUFFER_MODE 1 \ + TX_BUFFER_BYPASS_MODE Fast_Sync \ + TX_PIPM_ENABLE false \ + TX_OUTCLK_SOURCE TXPROGDIVCLK \ + TXPROGDIV_FREQ_ENABLE true \ + TXPROGDIV_FREQ_SOURCE LCPLL \ + TXPROGDIV_FREQ_VAL 375.000 \ + TX_DIFF_SWING_EMPH_MODE CUSTOM \ + TX_64B66B_SCRAMBLER false \ + TX_64B66B_ENCODER false \ + TX_64B66B_CRC false \ + TX_RATE_GROUP A \ + RX_LINE_RATE 24.75 \ + RX_PLL_TYPE LCPLL \ + RX_REFCLK_FREQUENCY 375 \ + RX_ACTUAL_REFCLK_FREQUENCY 375.000000000000 \ + RX_FRACN_ENABLED true \ + RX_FRACN_NUMERATOR 0 \ + RX_REFCLK_SOURCE R0 \ + RX_DATA_DECODING 64B66B_ASYNC \ + RX_USER_DATA_WIDTH 64 \ + RX_INT_DATA_WIDTH 64 \ + RX_BUFFER_MODE 1 \ + RX_OUTCLK_SOURCE RXPROGDIVCLK \ + RXPROGDIV_FREQ_ENABLE true \ + RXPROGDIV_FREQ_SOURCE LCPLL \ + RXPROGDIV_FREQ_VAL 375.000 \ + INS_LOSS_NYQ 12 \ + RX_EQ_MODE LPM \ + RX_COUPLING AC \ + RX_TERMINATION PROGRAMMABLE \ + RX_RATE_GROUP A \ + RX_TERMINATION_PROG_VALUE 800 \ + RX_PPM_OFFSET 0 \ + RX_64B66B_DESCRAMBLER false \ + RX_64B66B_DECODER false \ + RX_64B66B_CRC false \ + OOB_ENABLE false \ + RX_COMMA_ALIGN_WORD 1 \ + RX_COMMA_SHOW_REALIGN_ENABLE true \ + PCIE_ENABLE false \ + RX_COMMA_P_ENABLE false \ + RX_COMMA_M_ENABLE false \ + RX_COMMA_DOUBLE_ENABLE false \ + RX_COMMA_P_VAL 0101111100 \ + RX_COMMA_M_VAL 1010000011 \ + RX_COMMA_MASK 0000000000 \ + RX_SLIDE_MODE OFF \ + RX_SSC_PPM 0 \ + RX_CB_NUM_SEQ 0 \ + RX_CB_LEN_SEQ 1 \ + RX_CB_MAX_SKEW 1 \ + RX_CB_MAX_LEVEL 1 \ + RX_CB_MASK_0_0 false \ + RX_CB_VAL_0_0 00000000 \ + RX_CB_K_0_0 false \ + RX_CB_DISP_0_0 false \ + RX_CB_MASK_0_1 false \ + RX_CB_VAL_0_1 00000000 \ + RX_CB_K_0_1 false \ + RX_CB_DISP_0_1 false \ + RX_CB_MASK_0_2 false \ + RX_CB_VAL_0_2 00000000 \ + RX_CB_K_0_2 false \ + RX_CB_DISP_0_2 false \ + RX_CB_MASK_0_3 false \ + RX_CB_VAL_0_3 00000000 \ + RX_CB_K_0_3 false \ + RX_CB_DISP_0_3 false \ + RX_CB_MASK_1_0 false \ + RX_CB_VAL_1_0 00000000 \ + RX_CB_K_1_0 false \ + RX_CB_DISP_1_0 false \ + RX_CB_MASK_1_1 false \ + RX_CB_VAL_1_1 00000000 \ + RX_CB_K_1_1 false \ + RX_CB_DISP_1_1 false \ + RX_CB_MASK_1_2 false \ + RX_CB_VAL_1_2 00000000 \ + RX_CB_K_1_2 false \ + RX_CB_DISP_1_2 false \ + RX_CB_MASK_1_3 false \ + RX_CB_VAL_1_3 00000000 \ + RX_CB_K_1_3 false \ + RX_CB_DISP_1_3 false \ + RX_CC_NUM_SEQ 0 \ + RX_CC_LEN_SEQ 1 \ + RX_CC_PERIODICITY 5000 \ + RX_CC_KEEP_IDLE DISABLE \ + RX_CC_PRECEDENCE ENABLE \ + RX_CC_REPEAT_WAIT 0 \ + RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \ + RX_CC_MASK_0_0 false \ + RX_CC_VAL_0_0 00000000 \ + RX_CC_K_0_0 false \ + RX_CC_DISP_0_0 false \ + RX_CC_MASK_0_1 false \ + RX_CC_VAL_0_1 00000000 \ + RX_CC_K_0_1 false \ + RX_CC_DISP_0_1 false \ + RX_CC_MASK_0_2 false \ + RX_CC_VAL_0_2 00000000 \ + RX_CC_K_0_2 false \ + RX_CC_DISP_0_2 false \ + RX_CC_MASK_0_3 false \ + RX_CC_VAL_0_3 00000000 \ + RX_CC_K_0_3 false \ + RX_CC_DISP_0_3 false \ + RX_CC_MASK_1_0 false \ + RX_CC_VAL_1_0 00000000 \ + RX_CC_K_1_0 false \ + RX_CC_DISP_1_0 false \ + RX_CC_MASK_1_1 false \ + RX_CC_VAL_1_1 00000000 \ + RX_CC_K_1_1 false \ + RX_CC_DISP_1_1 false \ + RX_CC_MASK_1_2 false \ + RX_CC_VAL_1_2 00000000 \ + RX_CC_K_1_2 false \ + RX_CC_DISP_1_2 false \ + RX_CC_MASK_1_3 false \ + RX_CC_VAL_1_3 00000000 \ + RX_CC_K_1_3 false \ + RX_CC_DISP_1_3 false \ + PCIE_USERCLK2_FREQ 250 \ + PCIE_USERCLK_FREQ 250 \ + RX_JTOL_FC 10 \ + RX_JTOL_LF_SLOPE -20 \ + RX_BUFFER_BYPASS_MODE Fast_Sync \ + RX_BUFFER_BYPASS_MODE_LANE MULTI \ + RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \ + RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \ + RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \ + RESET_SEQUENCE_INTERVAL 0 \ + RX_COMMA_PRESET NONE \ + RX_COMMA_VALID_ONLY 0 \ + } \ +] [get_bd_cells gt_bridge_ip_0] + +apply_bd_automation -rule xilinx.com:bd_rule:gt_ips -config { DataPath_Interface_Connection {Auto} Lane0_selection {NULL} Lane10_selection {NULL} Lane11_selection {NULL} Lane12_selection {NULL} Lane13_selection {NULL} Lane14_selection {NULL} Lane15_selection {NULL} Lane16_selection {NULL} Lane17_selection {NULL} Lane18_selection {NULL} Lane19_selection {NULL} Lane1_selection {NULL} Lane2_selection {NULL} Lane3_selection {NULL} Lane4_selection {NULL} Lane5_selection {NULL} Lane6_selection {NULL} Lane7_selection {NULL} Lane8_selection {NULL} Lane9_selection {NULL} Quad0_selection {NULL} Quad10_selection {NULL} Quad11_selection {NULL} Quad12_selection {NULL} Quad13_selection {NULL} Quad14_selection {NULL} Quad15_selection {NULL} Quad16_selection {NULL} Quad17_selection {NULL} Quad18_selection {NULL} Quad19_selection {NULL} Quad1_selection {NULL} Quad2_selection {NULL} Quad3_selection {NULL} Quad4_selection {NULL} Quad5_selection {NULL} Quad6_selection {NULL} Quad7_selection {NULL} Quad8_selection {NULL} Quad9_selection {NULL}} [get_bd_cells gt_bridge_ip_0] + +validate_bd_design + +save_bd_design +close_bd_design [current_bd_design] + +current_bd_design [get_bd_designs $top_design] +