daq3: bsplit/ccat -- removed
Rejeesh Kutty
parent
29c6e90d38
commit
6c0ad6ede8
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@ -13,27 +13,6 @@ create_bd_port -dir I tx_sysref
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create_bd_port -dir O -from 3 -to 0 tx_data_p
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create_bd_port -dir O -from 3 -to 0 tx_data_n
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create_bd_port -dir O dac_clk
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create_bd_port -dir O dac_valid_0
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create_bd_port -dir O dac_enable_0
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create_bd_port -dir I -from 63 -to 0 dac_ddata_0
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create_bd_port -dir O dac_valid_1
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create_bd_port -dir O dac_enable_1
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create_bd_port -dir I -from 63 -to 0 dac_ddata_1
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create_bd_port -dir I dac_drd
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create_bd_port -dir O -from 127 -to 0 dac_ddata
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_enable_0
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create_bd_port -dir O adc_valid_0
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create_bd_port -dir O -from 63 -to 0 adc_data_0
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create_bd_port -dir O adc_enable_1
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create_bd_port -dir O adc_valid_1
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create_bd_port -dir O -from 63 -to 0 adc_data_1
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create_bd_port -dir I adc_dwr
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create_bd_port -dir I adc_dsync
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create_bd_port -dir I -from 127 -to 0 adc_ddata
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# dac peripherals
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set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core]
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@ -44,17 +23,21 @@ set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9152_jesd
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set axi_ad9152_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9152_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
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set axi_ad9152_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 axi_ad9152_upack]
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set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9152_upack
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set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9152_upack
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# adc peripherals
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set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
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@ -77,6 +60,10 @@ set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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set axi_ad9680_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad9680_cpack]
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set_property -dict [list CONFIG.CH_DW {64}] $axi_ad9680_cpack
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set_property -dict [list CONFIG.CH_CNT {2}] $axi_ad9680_cpack
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# dac/adc common gt
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set axi_daq3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq3_gt]
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@ -102,116 +89,86 @@ ad_connect axi_daq3_gt/tx_ext_sysref tx_sysref
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# connections (dac)
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ad_connect axi_daq3_gt/tx_clk_g dac_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_daq3_gt/tx_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_core/tx_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_jesd/tx_core_clk
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ad_connect axi_daq3_gt/tx_clk_g axi_ad9152_upack/dac_clk
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ad_connect axi_daq3_gt/tx_rst axi_ad9152_jesd/tx_reset
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ad_connect axi_daq3_gt/tx_sysref axi_ad9152_jesd/tx_sysref
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create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_charisk
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_ccat_tx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_ccat_tx_gt_charisk]
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ad_connect util_ccat_tx_gt_charisk/ccat_data axi_daq3_gt/tx_gt_charisk
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ad_connect util_ccat_tx_gt_charisk/data_0 axi_ad9152_jesd/gt0_txcharisk
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ad_connect util_ccat_tx_gt_charisk/data_1 axi_ad9152_jesd/gt1_txcharisk
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ad_connect util_ccat_tx_gt_charisk/data_2 axi_ad9152_jesd/gt2_txcharisk
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ad_connect util_ccat_tx_gt_charisk/data_3 axi_ad9152_jesd/gt3_txcharisk
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create_bd_cell -type ip -vlnv analog.com:user:util_ccat:1.0 util_ccat_tx_gt_data
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set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_ccat_tx_gt_data]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_ccat_tx_gt_data]
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ad_connect util_ccat_tx_gt_data/ccat_data axi_daq3_gt/tx_gt_data
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ad_connect util_ccat_tx_gt_data/data_0 axi_ad9152_jesd/gt0_txdata
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ad_connect util_ccat_tx_gt_data/data_1 axi_ad9152_jesd/gt1_txdata
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ad_connect util_ccat_tx_gt_data/data_2 axi_ad9152_jesd/gt2_txdata
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ad_connect util_ccat_tx_gt_data/data_3 axi_ad9152_jesd/gt3_txdata
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ad_connect axi_daq3_gt/tx_gt_charisk_0 axi_ad9152_jesd/gt0_txcharisk
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ad_connect axi_daq3_gt/tx_gt_charisk_1 axi_ad9152_jesd/gt1_txcharisk
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ad_connect axi_daq3_gt/tx_gt_charisk_2 axi_ad9152_jesd/gt2_txcharisk
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ad_connect axi_daq3_gt/tx_gt_charisk_3 axi_ad9152_jesd/gt3_txcharisk
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ad_connect axi_daq3_gt/tx_gt_data_0 axi_ad9152_jesd/gt0_txdata
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ad_connect axi_daq3_gt/tx_gt_data_1 axi_ad9152_jesd/gt1_txdata
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ad_connect axi_daq3_gt/tx_gt_data_2 axi_ad9152_jesd/gt2_txdata
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ad_connect axi_daq3_gt/tx_gt_data_3 axi_ad9152_jesd/gt3_txdata
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ad_connect axi_daq3_gt/tx_rst_done axi_ad9152_jesd/tx_reset_done
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ad_connect axi_daq3_gt/tx_ip_sync axi_ad9152_jesd/tx_sync
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ad_connect axi_daq3_gt/tx_ip_sof axi_ad9152_jesd/tx_start_of_frame
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ad_connect axi_daq3_gt/tx_ip_data axi_ad9152_jesd/tx_tdata
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ad_connect axi_daq3_gt/tx_data axi_ad9152_core/tx_data
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ad_connect axi_ad9152_core/dac_clk axi_ad9152_dma/fifo_rd_clk
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ad_connect axi_ad9152_core/dac_valid_0 dac_valid_0
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ad_connect axi_ad9152_core/dac_enable_0 dac_enable_0
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ad_connect axi_ad9152_core/dac_ddata_0 dac_ddata_0
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ad_connect axi_ad9152_core/dac_valid_1 dac_valid_1
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ad_connect axi_ad9152_core/dac_enable_1 dac_enable_1
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ad_connect axi_ad9152_core/dac_ddata_1 dac_ddata_1
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ad_connect dac_drd axi_ad9152_dma/fifo_rd_en
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ad_connect dac_ddata axi_ad9152_dma/fifo_rd_dout
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ad_connect axi_ad9152_core/dac_dunf axi_ad9152_dma/fifo_rd_underflow
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ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
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ad_connect axi_ad9152_core/dac_enable_0 axi_ad9152_upack/dac_enable_0
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ad_connect axi_ad9152_core/dac_ddata_0 axi_ad9152_upack/dac_data_0
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ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
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ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
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ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
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ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn
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ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk
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ad_connect axi_ad9152_dma/m_axis_xfer_req axi_ad9152_fifo/dma_xfer_req
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ad_connect axi_ad9152_dma/m_axis_aclk axi_ad9152_fifo/dma_clk
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ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst
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ad_connect axi_ad9152_dma/m_axis_ready axi_ad9152_fifo/dma_ready
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ad_connect axi_ad9152_dma/m_axis_data axi_ad9152_fifo/dma_data
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ad_connect axi_ad9152_dma/m_axis_valid axi_ad9152_fifo/dma_valid
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ad_connect axi_ad9152_dma/m_axis_last axi_ad9152_fifo/dma_xfer_last
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ad_connect axi_ad9152_fifo/dac_clk axi_daq3_gt/tx_clk
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ad_connect axi_ad9152_fifo/dac_valid axi_ad9152_upack/dac_valid
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ad_connect axi_ad9152_fifo/dac_data axi_ad9152_upack/dac_data
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# connections (adc)
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ad_connect axi_daq3_gt/rx_clk_g adc_clk
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ad_connect axi_daq3_gt/rx_clk_g axi_daq3_gt/rx_clk
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ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_core/rx_clk
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ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_jesd/rx_core_clk
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ad_connect axi_daq3_gt/rx_rst axi_ad9680_jesd/rx_reset
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ad_connect axi_daq3_gt/rx_jesd_rst axi_ad9680_jesd/rx_reset
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ad_connect axi_daq3_gt/rx_clk_g axi_ad9680_cpack/adc_clk
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ad_connect axi_daq3_gt/rx_sysref axi_ad9680_jesd/rx_sysref
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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ad_connect util_bsplit_rx_gt_charisk/data axi_daq3_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9680_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9680_jesd/gt1_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_2 axi_ad9680_jesd/gt2_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_3 axi_ad9680_jesd/gt3_rxcharisk
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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ad_connect util_bsplit_rx_gt_disperr/data axi_daq3_gt/rx_gt_disperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad9680_jesd/gt0_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad9680_jesd/gt1_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_2 axi_ad9680_jesd/gt2_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_3 axi_ad9680_jesd/gt3_rxdisperr
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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ad_connect util_bsplit_rx_gt_notintable/data axi_daq3_gt/rx_gt_notintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9680_jesd/gt0_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9680_jesd/gt1_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_2 axi_ad9680_jesd/gt2_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_3 axi_ad9680_jesd/gt3_rxnotintable
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
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set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.CH_CNT {4}] [get_bd_cells util_bsplit_rx_gt_data]
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ad_connect util_bsplit_rx_gt_data/data axi_daq3_gt/rx_gt_data
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ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9680_jesd/gt0_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9680_jesd/gt1_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_2 axi_ad9680_jesd/gt2_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_3 axi_ad9680_jesd/gt3_rxdata
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ad_connect axi_daq3_gt/rx_gt_charisk_0 axi_ad9680_jesd/gt0_rxcharisk
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ad_connect axi_daq3_gt/rx_gt_disperr_0 axi_ad9680_jesd/gt0_rxdisperr
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ad_connect axi_daq3_gt/rx_gt_notintable_0 axi_ad9680_jesd/gt0_rxnotintable
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ad_connect axi_daq3_gt/rx_gt_data_0 axi_ad9680_jesd/gt0_rxdata
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ad_connect axi_daq3_gt/rx_gt_charisk_1 axi_ad9680_jesd/gt1_rxcharisk
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ad_connect axi_daq3_gt/rx_gt_disperr_1 axi_ad9680_jesd/gt1_rxdisperr
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ad_connect axi_daq3_gt/rx_gt_notintable_1 axi_ad9680_jesd/gt1_rxnotintable
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ad_connect axi_daq3_gt/rx_gt_data_1 axi_ad9680_jesd/gt1_rxdata
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ad_connect axi_daq3_gt/rx_gt_charisk_2 axi_ad9680_jesd/gt2_rxcharisk
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ad_connect axi_daq3_gt/rx_gt_disperr_2 axi_ad9680_jesd/gt2_rxdisperr
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ad_connect axi_daq3_gt/rx_gt_notintable_2 axi_ad9680_jesd/gt2_rxnotintable
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ad_connect axi_daq3_gt/rx_gt_data_2 axi_ad9680_jesd/gt2_rxdata
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ad_connect axi_daq3_gt/rx_gt_charisk_3 axi_ad9680_jesd/gt3_rxcharisk
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ad_connect axi_daq3_gt/rx_gt_disperr_3 axi_ad9680_jesd/gt3_rxdisperr
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ad_connect axi_daq3_gt/rx_gt_notintable_3 axi_ad9680_jesd/gt3_rxnotintable
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ad_connect axi_daq3_gt/rx_gt_data_3 axi_ad9680_jesd/gt3_rxdata
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ad_connect axi_daq3_gt/rx_rst_done axi_ad9680_jesd/rx_reset_done
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ad_connect axi_daq3_gt/rx_ip_comma_align axi_ad9680_jesd/rxencommaalign_out
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ad_connect axi_daq3_gt/rx_ip_sync axi_ad9680_jesd/rx_sync
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ad_connect axi_daq3_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame
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ad_connect axi_daq3_gt/rx_ip_data axi_ad9680_jesd/rx_tdata
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ad_connect axi_daq3_gt/rx_data axi_ad9680_core/rx_data
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ad_connect axi_ad9680_core/adc_enable_0 adc_enable_0
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ad_connect axi_ad9680_core/adc_valid_0 adc_valid_0
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ad_connect axi_ad9680_core/adc_data_0 adc_data_0
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ad_connect axi_ad9680_core/adc_enable_1 adc_enable_1
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ad_connect axi_ad9680_core/adc_valid_1 adc_valid_1
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ad_connect axi_ad9680_core/adc_data_1 adc_data_1
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ad_connect axi_ad9680_core/adc_enable_0 axi_ad9680_cpack/adc_enable_0
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ad_connect axi_ad9680_core/adc_valid_0 axi_ad9680_cpack/adc_valid_0
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ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
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ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
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ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
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ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
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ad_connect axi_daq3_gt/rx_rst axi_ad9680_fifo/adc_rst
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ad_connect axi_daq3_gt/rx_rst axi_ad9680_cpack/adc_rst
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ad_connect axi_ad9680_core/adc_clk axi_ad9680_fifo/adc_clk
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ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
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ad_connect adc_dwr axi_ad9680_fifo/adc_wr
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ad_connect adc_ddata axi_ad9680_fifo/adc_wdata
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ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
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ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
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ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
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ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
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ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
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@ -1,14 +1,16 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
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||||
|
||||
create_bd_port -dir I -type rst sys_rst
|
||||
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
|
||||
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
|
||||
|
||||
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
|
||||
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
|
||||
|
||||
ad_connect sys_rst axi_ad9680_fifo/sys_rst
|
||||
ad_connect sys_clk axi_ad9680_fifo/sys_clk
|
||||
|
|
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|||
|
|
@ -229,15 +229,6 @@ module system_top (
|
|||
inout spi_sdio;
|
||||
output spi_dir;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_drd = 'd0;
|
||||
reg [63:0] dac_ddata_0 = 'd0;
|
||||
reg [63:0] dac_ddata_1 = 'd0;
|
||||
reg adc_dsync = 'd0;
|
||||
reg adc_dwr = 'd0;
|
||||
reg [127:0] adc_ddata = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire sysref;
|
||||
|
|
@ -259,118 +250,6 @@ module system_top (
|
|||
wire tx_ref_clk;
|
||||
wire tx_sysref;
|
||||
wire tx_sync;
|
||||
wire dac_clk;
|
||||
wire [127:0] dac_ddata;
|
||||
wire dac_enable_0;
|
||||
wire dac_enable_1;
|
||||
wire dac_valid_0;
|
||||
wire dac_valid_1;
|
||||
wire adc_clk;
|
||||
wire [63:0] adc_data_0;
|
||||
wire [63:0] adc_data_1;
|
||||
wire adc_enable_0;
|
||||
wire adc_enable_1;
|
||||
wire adc_valid_0;
|
||||
wire adc_valid_1;
|
||||
|
||||
// adc-dac data
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
case ({dac_enable_1, dac_enable_0})
|
||||
2'b11: begin
|
||||
dac_drd <= dac_valid_0 & dac_valid_1;
|
||||
dac_ddata_0[63:48] <= dac_ddata[111: 96];
|
||||
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
|
||||
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
|
||||
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
|
||||
dac_ddata_1[63:48] <= dac_ddata[127:112];
|
||||
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
|
||||
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
|
||||
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
|
||||
end
|
||||
2'b10: begin
|
||||
dac_drd <= dac_valid_1 & ~dac_drd;
|
||||
dac_ddata_0 <= 64'd0;
|
||||
if (dac_drd == 1'b1) begin
|
||||
dac_ddata_1[63:48] <= dac_ddata[127:112];
|
||||
dac_ddata_1[47:32] <= dac_ddata[111: 96];
|
||||
dac_ddata_1[31:16] <= dac_ddata[ 95: 80];
|
||||
dac_ddata_1[15: 0] <= dac_ddata[ 79: 64];
|
||||
end else begin
|
||||
dac_ddata_1[63:48] <= dac_ddata[ 63: 48];
|
||||
dac_ddata_1[47:32] <= dac_ddata[ 47: 32];
|
||||
dac_ddata_1[31:16] <= dac_ddata[ 31: 16];
|
||||
dac_ddata_1[15: 0] <= dac_ddata[ 15: 0];
|
||||
end
|
||||
end
|
||||
2'b01: begin
|
||||
dac_drd <= dac_valid_0 & ~dac_drd;
|
||||
if (dac_drd == 1'b1) begin
|
||||
dac_ddata_0[63:48] <= dac_ddata[127:112];
|
||||
dac_ddata_0[47:32] <= dac_ddata[111: 96];
|
||||
dac_ddata_0[31:16] <= dac_ddata[ 95: 80];
|
||||
dac_ddata_0[15: 0] <= dac_ddata[ 79: 64];
|
||||
end else begin
|
||||
dac_ddata_0[63:48] <= dac_ddata[ 63: 48];
|
||||
dac_ddata_0[47:32] <= dac_ddata[ 47: 32];
|
||||
dac_ddata_0[31:16] <= dac_ddata[ 31: 16];
|
||||
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
|
||||
end
|
||||
dac_ddata_1 <= 64'd0;
|
||||
end
|
||||
default: begin
|
||||
dac_drd <= 1'b0;
|
||||
dac_ddata_0 <= 64'd0;
|
||||
dac_ddata_1 <= 64'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
case ({adc_enable_1, adc_enable_0})
|
||||
2'b11: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_1 & adc_valid_0;
|
||||
adc_ddata[127:112] <= adc_data_1[63:48];
|
||||
adc_ddata[111: 96] <= adc_data_0[63:48];
|
||||
adc_ddata[ 95: 80] <= adc_data_1[47:32];
|
||||
adc_ddata[ 79: 64] <= adc_data_0[47:32];
|
||||
adc_ddata[ 63: 48] <= adc_data_1[31:16];
|
||||
adc_ddata[ 47: 32] <= adc_data_0[31:16];
|
||||
adc_ddata[ 31: 16] <= adc_data_1[15: 0];
|
||||
adc_ddata[ 15: 0] <= adc_data_0[15: 0];
|
||||
end
|
||||
2'b10: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_1 & ~adc_dwr;
|
||||
adc_ddata[127:112] <= adc_data_1[63:48];
|
||||
adc_ddata[111: 96] <= adc_data_1[47:32];
|
||||
adc_ddata[ 95: 80] <= adc_data_1[31:16];
|
||||
adc_ddata[ 79: 64] <= adc_data_1[15: 0];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
2'b01: begin
|
||||
adc_dsync <= 1'b1;
|
||||
adc_dwr <= adc_valid_0 & ~adc_dwr;
|
||||
adc_ddata[127:112] <= adc_data_0[63:48];
|
||||
adc_ddata[111: 96] <= adc_data_0[47:32];
|
||||
adc_ddata[ 95: 80] <= adc_data_0[31:16];
|
||||
adc_ddata[ 79: 64] <= adc_data_0[15: 0];
|
||||
adc_ddata[ 63: 48] <= adc_ddata[127:112];
|
||||
adc_ddata[ 47: 32] <= adc_ddata[111: 96];
|
||||
adc_ddata[ 31: 16] <= adc_ddata[ 95: 80];
|
||||
adc_ddata[ 15: 0] <= adc_ddata[ 79: 64];
|
||||
end
|
||||
default: begin
|
||||
adc_dsync <= 1'b0;
|
||||
adc_dwr <= 1'b0;
|
||||
adc_ddata <= 128'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// spi
|
||||
|
||||
|
|
@ -453,25 +332,6 @@ module system_top (
|
|||
.dio_p (gpio_bd));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data_0 (adc_data_0),
|
||||
.adc_data_1 (adc_data_1),
|
||||
.adc_ddata (adc_ddata),
|
||||
.adc_dsync (adc_dsync),
|
||||
.adc_dwr (adc_dwr),
|
||||
.adc_enable_0 (adc_enable_0),
|
||||
.adc_enable_1 (adc_enable_1),
|
||||
.adc_valid_0 (adc_valid_0),
|
||||
.adc_valid_1 (adc_valid_1),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_ddata (dac_ddata),
|
||||
.dac_ddata_0 (dac_ddata_0),
|
||||
.dac_ddata_1 (dac_ddata_1),
|
||||
.dac_drd (dac_drd),
|
||||
.dac_enable_0 (dac_enable_0),
|
||||
.dac_enable_1 (dac_enable_1),
|
||||
.dac_valid_0 (dac_valid_0),
|
||||
.dac_valid_1 (dac_valid_1),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
|
|
|
|||
Loading…
Reference in New Issue