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common: Remove deprecated modules

main
Istvan Csomortani 2017-06-26 15:43:57 +01:00
parent 95877fc5ce
commit 6bcb327d5f
5 changed files with 0 additions and 2012 deletions
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409
library/common/ad_gt_channel_1.v
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@ -1,409 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_channel_1 #(
parameter integer ID = 0,
parameter integer GTH_OR_GTX_N = 0,
parameter [31:0] PMA_RSV = 32'h00018480,
parameter integer CPLL_FBDIV = 2,
parameter integer RX_OUT_DIV = 1,
parameter integer RX_CLK25_DIV = 10,
parameter integer RX_CLKBUF_ENABLE = 0,
parameter [72:0] RX_CDR_CFG = 72'h03000023ff20400020,
parameter integer TX_OUT_DIV = 1,
parameter integer TX_CLK25_DIV = 10,
parameter integer TX_CLKBUF_ENABLE = 0) (
// channel interface (pll)
input cpll_rst_m,
input cpll_ref_clk_in,
input qpll_ref_clk,
input qpll_locked,
input qpll_clk,
// channel interface (rx)
input rx_p,
input rx_n,
output rx_out_clk,
input rx_clk,
output rx_rst,
input rx_rst_m,
output rx_sof,
output [31:0] rx_data,
input rx_sysref,
output rx_sync,
output rx_pll_rst,
output rx_gt_rst,
input rx_gt_rst_m,
output [ 3:0] rx_gt_charisk,
output [ 3:0] rx_gt_disperr,
output [ 3:0] rx_gt_notintable,
output [31:0] rx_gt_data,
input rx_gt_comma_align_enb,
output [ 3:0] rx_gt_ilas_f,
output [ 3:0] rx_gt_ilas_q,
output [ 3:0] rx_gt_ilas_a,
output [ 3:0] rx_gt_ilas_r,
output [ 3:0] rx_gt_cgs_k,
output rx_ip_rst,
input [ 3:0] rx_ip_sof,
input [31:0] rx_ip_data,
output rx_ip_sysref,
input rx_ip_sync,
output rx_ip_rst_done,
output rx_pll_locked,
output rx_user_ready,
output rx_rst_done,
input rx_pll_locked_m,
input rx_user_ready_m,
input rx_rst_done_m,
// channel interface (tx)
output tx_p,
output tx_n,
output tx_out_clk,
input tx_clk,
output tx_rst,
input tx_rst_m,
input [31:0] tx_data,
input tx_sysref,
input tx_sync,
output tx_pll_rst,
output tx_gt_rst,
input tx_gt_rst_m,
input [ 3:0] tx_gt_charisk,
input [31:0] tx_gt_data,
output tx_ip_rst,
output [31:0] tx_ip_data,
output tx_ip_sysref,
output tx_ip_sync,
output tx_ip_rst_done,
output tx_pll_locked,
output tx_user_ready,
output tx_rst_done,
input tx_pll_locked_m,
input tx_user_ready_m,
input tx_rst_done_m,
// dma interface
output up_es_dma_req,
output [31:0] up_es_dma_addr,
output [31:0] up_es_dma_data,
input up_es_dma_ack,
input up_es_dma_err,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals
wire lpm_dfe_n_s;
wire cpll_pd_s;
wire [ 1:0] rx_sys_clk_sel_s;
wire [ 2:0] rx_out_clk_sel_s;
wire [ 1:0] tx_sys_clk_sel_s;
wire [ 2:0] tx_out_clk_sel_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire [ 7:0] up_drp_rxrate_s;
wire up_es_drp_sel_s;
wire up_es_drp_wr_s;
wire [11:0] up_es_drp_addr_s;
wire [15:0] up_es_drp_wdata_s;
wire [15:0] up_es_drp_rdata_s;
wire up_es_drp_ready_s;
wire up_es_start_s;
wire up_es_stop_s;
wire up_es_init_s;
wire [ 4:0] up_es_prescale_s;
wire [ 1:0] up_es_voffset_range_s;
wire [ 7:0] up_es_voffset_step_s;
wire [ 7:0] up_es_voffset_max_s;
wire [ 7:0] up_es_voffset_min_s;
wire [11:0] up_es_hoffset_max_s;
wire [11:0] up_es_hoffset_min_s;
wire [11:0] up_es_hoffset_step_s;
wire [31:0] up_es_start_addr_s;
wire [15:0] up_es_sdata0_s;
wire [15:0] up_es_sdata1_s;
wire [15:0] up_es_sdata2_s;
wire [15:0] up_es_sdata3_s;
wire [15:0] up_es_sdata4_s;
wire [15:0] up_es_qdata0_s;
wire [15:0] up_es_qdata1_s;
wire [15:0] up_es_qdata2_s;
wire [15:0] up_es_qdata3_s;
wire [15:0] up_es_qdata4_s;
wire up_es_status_s;
// nothing to do for now
assign tx_ip_data = tx_data;
// instantiations
ad_jesd_align i_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof),
.rx_ip_data (rx_ip_data),
.rx_sof (rx_sof),
.rx_data (rx_data));
ad_gt_channel #(
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.PMA_RSV (PMA_RSV),
.CPLL_FBDIV (CPLL_FBDIV),
.RX_OUT_DIV (RX_OUT_DIV),
.TX_OUT_DIV (TX_OUT_DIV),
.RX_CLK25_DIV (RX_CLK25_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV),
.RX_CLKBUF_ENABLE (RX_CLKBUF_ENABLE),
.TX_CLKBUF_ENABLE (TX_CLKBUF_ENABLE),
.RX_CDR_CFG (RX_CDR_CFG))
i_gt (
.lpm_dfe_n (lpm_dfe_n_s),
.cpll_ref_clk_in (cpll_ref_clk_in),
.cpll_pd (cpll_pd_s),
.cpll_rst (cpll_rst_m),
.qpll_clk (qpll_clk),
.qpll_ref_clk (qpll_ref_clk),
.qpll_locked (qpll_locked),
.rx_gt_rst_m (rx_gt_rst_m),
.rx_p (rx_p),
.rx_n (rx_n),
.rx_sys_clk_sel (rx_sys_clk_sel_s),
.rx_out_clk_sel (rx_out_clk_sel_s),
.rx_out_clk (rx_out_clk),
.rx_rst_done (rx_rst_done),
.rx_pll_locked (rx_pll_locked),
.rx_user_ready_m (rx_user_ready_m),
.rx_clk (rx_clk),
.rx_gt_charisk (rx_gt_charisk),
.rx_gt_disperr (rx_gt_disperr),
.rx_gt_notintable (rx_gt_notintable),
.rx_gt_data (rx_gt_data),
.rx_gt_comma_align_enb (rx_gt_comma_align_enb),
.rx_gt_ilas_f (rx_gt_ilas_f),
.rx_gt_ilas_q (rx_gt_ilas_q),
.rx_gt_ilas_a (rx_gt_ilas_a),
.rx_gt_ilas_r (rx_gt_ilas_r),
.rx_gt_cgs_k (rx_gt_cgs_k),
.tx_gt_rst_m (tx_gt_rst_m),
.tx_p (tx_p),
.tx_n (tx_n),
.tx_sys_clk_sel (tx_sys_clk_sel_s),
.tx_out_clk_sel (tx_out_clk_sel_s),
.tx_out_clk (tx_out_clk),
.tx_rst_done (tx_rst_done),
.tx_pll_locked (tx_pll_locked),
.tx_user_ready_m (tx_user_ready_m),
.tx_clk (tx_clk),
.tx_gt_charisk (tx_gt_charisk),
.tx_gt_data (tx_gt_data),
.up_clk (up_clk),
.up_drp_sel (up_drp_sel_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_rxrate (up_drp_rxrate_s));
ad_gt_es #(
.GTH_OR_GTX_N (GTH_OR_GTX_N))
i_es (
.lpm_dfe_n (lpm_dfe_n_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_es_drp_sel (up_es_drp_sel_s),
.up_es_drp_wr (up_es_drp_wr_s),
.up_es_drp_addr (up_es_drp_addr_s),
.up_es_drp_wdata (up_es_drp_wdata_s),
.up_es_drp_rdata (up_es_drp_rdata_s),
.up_es_drp_ready (up_es_drp_ready_s),
.up_es_dma_req (up_es_dma_req),
.up_es_dma_addr (up_es_dma_addr),
.up_es_dma_data (up_es_dma_data),
.up_es_dma_ack (up_es_dma_ack),
.up_es_start (up_es_start_s),
.up_es_stop (up_es_stop_s),
.up_es_init (up_es_init_s),
.up_es_sdata0 (up_es_sdata0_s),
.up_es_sdata1 (up_es_sdata1_s),
.up_es_sdata2 (up_es_sdata2_s),
.up_es_sdata3 (up_es_sdata3_s),
.up_es_sdata4 (up_es_sdata4_s),
.up_es_qdata0 (up_es_qdata0_s),
.up_es_qdata1 (up_es_qdata1_s),
.up_es_qdata2 (up_es_qdata2_s),
.up_es_qdata3 (up_es_qdata3_s),
.up_es_qdata4 (up_es_qdata4_s),
.up_es_prescale (up_es_prescale_s),
.up_es_hoffset_min (up_es_hoffset_min_s),
.up_es_hoffset_max (up_es_hoffset_max_s),
.up_es_hoffset_step (up_es_hoffset_step_s),
.up_es_voffset_min (up_es_voffset_min_s),
.up_es_voffset_max (up_es_voffset_max_s),
.up_es_voffset_step (up_es_voffset_step_s),
.up_es_voffset_range (up_es_voffset_range_s),
.up_es_start_addr (up_es_start_addr_s),
.up_es_status (up_es_status_s));
up_gt_channel #(
.ID (ID))
i_up (
.lpm_dfe_n (lpm_dfe_n_s),
.cpll_pd (cpll_pd_s),
.rx_pll_rst (rx_pll_rst),
.rx_sys_clk_sel (rx_sys_clk_sel_s),
.rx_out_clk_sel (rx_out_clk_sel_s),
.rx_clk (rx_clk),
.rx_gt_rst (rx_gt_rst),
.rx_rst (rx_rst),
.rx_rst_m (rx_rst_m),
.rx_ip_rst (rx_ip_rst),
.rx_sysref (rx_sysref),
.rx_ip_sysref (rx_ip_sysref),
.rx_ip_sync (rx_ip_sync),
.rx_sync (rx_sync),
.rx_rst_done (rx_rst_done),
.rx_rst_done_m (rx_rst_done_m),
.rx_pll_locked (rx_pll_locked),
.rx_pll_locked_m (rx_pll_locked_m),
.rx_user_ready (rx_user_ready),
.rx_ip_rst_done (rx_ip_rst_done),
.tx_pll_rst (tx_pll_rst),
.tx_sys_clk_sel (tx_sys_clk_sel_s),
.tx_out_clk_sel (tx_out_clk_sel_s),
.tx_clk (tx_clk),
.tx_gt_rst (tx_gt_rst),
.tx_rst (tx_rst),
.tx_rst_m (tx_rst_m),
.tx_ip_rst (tx_ip_rst),
.tx_sysref (tx_sysref),
.tx_ip_sysref (tx_ip_sysref),
.tx_sync (tx_sync),
.tx_ip_sync (tx_ip_sync),
.tx_rst_done (tx_rst_done),
.tx_rst_done_m (tx_rst_done_m),
.tx_pll_locked (tx_pll_locked),
.tx_pll_locked_m (tx_pll_locked_m),
.tx_user_ready (tx_user_ready),
.tx_ip_rst_done (tx_ip_rst_done),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_rxrate (up_drp_rxrate_s),
.up_es_drp_sel (up_es_drp_sel_s),
.up_es_drp_wr (up_es_drp_wr_s),
.up_es_drp_addr (up_es_drp_addr_s),
.up_es_drp_wdata (up_es_drp_wdata_s),
.up_es_drp_rdata (up_es_drp_rdata_s),
.up_es_drp_ready (up_es_drp_ready_s),
.up_es_start (up_es_start_s),
.up_es_stop (up_es_stop_s),
.up_es_init (up_es_init_s),
.up_es_prescale (up_es_prescale_s),
.up_es_voffset_range (up_es_voffset_range_s),
.up_es_voffset_step (up_es_voffset_step_s),
.up_es_voffset_max (up_es_voffset_max_s),
.up_es_voffset_min (up_es_voffset_min_s),
.up_es_hoffset_max (up_es_hoffset_max_s),
.up_es_hoffset_min (up_es_hoffset_min_s),
.up_es_hoffset_step (up_es_hoffset_step_s),
.up_es_start_addr (up_es_start_addr_s),
.up_es_sdata0 (up_es_sdata0_s),
.up_es_sdata1 (up_es_sdata1_s),
.up_es_sdata2 (up_es_sdata2_s),
.up_es_sdata3 (up_es_sdata3_s),
.up_es_sdata4 (up_es_sdata4_s),
.up_es_qdata0 (up_es_qdata0_s),
.up_es_qdata1 (up_es_qdata1_s),
.up_es_qdata2 (up_es_qdata2_s),
.up_es_qdata3 (up_es_qdata3_s),
.up_es_qdata4 (up_es_qdata4_s),
.up_es_dma_err (up_es_dma_err),
.up_es_status (up_es_status_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

285
library/common/ad_gt_common.v
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@ -1,285 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common #(
parameter integer GTH_OR_GTX_N = 0,
parameter integer QPLL_ENABLE = 1,
parameter integer QPLL_REFCLK_DIV = 2,
parameter [26:0] QPLL_CFG = 27'h06801C1,
parameter integer QPLL_FBDIV_RATIO = 1'b1,
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000) (
// reset and clocks
input qpll_ref_clk_in,
input qpll_rst,
output qpll_clk,
output qpll_ref_clk,
output qpll_locked,
// drp interface
input up_clk,
input up_drp_sel,
input [11:0] up_drp_addr,
input up_drp_wr,
input [15:0] up_drp_wdata,
output [15:0] up_drp_rdata,
output up_drp_ready);
// instantiations
generate
if (QPLL_ENABLE == 0) begin
assign qpll_clk = 1'd0;
assign qpll_ref_clk = 1'd0;
assign qpll_locked = 1'd0;
assign up_drp_rdata = 16'd0;
assign up_drp_ready = 1'd0;
end
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 0)) begin
GTXE2_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("3.0"),
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gtxe2_common (
.DRPCLK (up_clk),
.DRPEN (up_drp_sel),
.DRPADDR (up_drp_addr[7:0]),
.DRPWE (up_drp_wr),
.DRPDI (up_drp_wdata),
.DRPDO (up_drp_rdata),
.DRPRDY (up_drp_ready),
.GTGREFCLK (1'd0),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTREFCLK0 (qpll_ref_clk_in),
.GTREFCLK1 (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.QPLLDMONITOR (),
.QPLLOUTCLK (qpll_clk),
.QPLLOUTREFCLK (qpll_ref_clk),
.REFCLKOUTMONITOR (),
.QPLLFBCLKLOST (),
.QPLLLOCK (qpll_locked),
.QPLLLOCKDETCLK (up_clk),
.QPLLLOCKEN (1'd1),
.QPLLOUTRESET (1'd0),
.QPLLPD (1'd0),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (qpll_rst),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (1'd1));
end
if ((QPLL_ENABLE == 1) && (GTH_OR_GTX_N == 1)) begin
GTHE3_COMMON #(
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION (2),
.SARC_EN (1'b1),
.SARC_SEL (1'b0),
.SDM0_DATA_PIN_SEL (1'b0),
.SDM0_WIDTH_PIN_SEL (1'b0),
.SDM1_DATA_PIN_SEL (1'b0),
.SDM1_WIDTH_PIN_SEL (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000000000000),
.BIAS_CFG3 (16'b0000000001000000),
.BIAS_CFG4 (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000100),
.QPLL0_CFG0 (16'b0011000000011100),
.QPLL0_CFG1 (16'b0000000000011000),
.QPLL0_CFG1_G3 (16'b0000000000011000),
.QPLL0_CFG2 (16'b0000000001001000),
.QPLL0_CFG2_G3 (16'b0000000001001000),
.QPLL0_CFG3 (16'b0000000100100000),
.QPLL0_CFG4 (16'b0000000000001001),
.QPLL0_INIT_CFG0 (16'b0000000000000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_SDM_CFG0 (16'b0000000000000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1_CFG0 (16'b0011000000011100),
.QPLL1_CFG1 (16'b0000000000011000),
.QPLL1_CFG1_G3 (16'b0000000000011000),
.QPLL1_CFG2 (16'b0000000001000000),
.QPLL1_CFG2_G3 (16'b0000000001000000),
.QPLL1_CFG3 (16'b0000000100100000),
.QPLL1_CFG4 (16'b0000000000001001),
.QPLL1_INIT_CFG0 (16'b0000000000000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_SDM_CFG0 (16'b0000000000000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.SDM0DATA1_0 (16'b0000000000000000),
.SDM0INITSEED0_0 (16'b0000000000000000),
.SDM1DATA1_0 (16'b0000000000000000),
.SDM1INITSEED0_0 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL1_INIT_CFG1 (8'b00000000),
.SDM0DATA1_1 (9'b000000000),
.SDM0INITSEED0_1 (9'b000000000),
.SDM1DATA1_1 (9'b000000000),
.SDM1INITSEED0_1 (9'b000000000),
.BIAS_CFG_RSVD (10'b0000000000),
.QPLL0_CP (10'b0000011111),
.QPLL0_CP_G3 (10'b1111111111),
.QPLL0_LPF (10'b1111111111),
.QPLL0_LPF_G3 (10'b0000010101),
.QPLL1_CP (10'b0000011111),
.QPLL1_CP_G3 (10'b1111111111),
.QPLL1_LPF (10'b1111111111),
.QPLL1_LPF_G3 (10'b0000010101),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (80),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV))
i_gthe3_common (
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'd1),
.DRPADDR (up_drp_addr[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_drp_wdata),
.DRPEN (up_drp_sel),
.DRPWE (up_drp_wr),
.GTGREFCLK0 (1'd0),
.GTGREFCLK1 (1'd0),
.GTNORTHREFCLK00 (1'd0),
.GTNORTHREFCLK01 (1'd0),
.GTNORTHREFCLK10 (1'd0),
.GTNORTHREFCLK11 (1'd0),
.GTREFCLK00 (qpll_ref_clk_in),
.GTREFCLK01 (1'd0),
.GTREFCLK10 (1'd0),
.GTREFCLK11 (1'd0),
.GTSOUTHREFCLK00 (1'd0),
.GTSOUTHREFCLK01 (1'd0),
.GTSOUTHREFCLK10 (1'd0),
.GTSOUTHREFCLK11 (1'd0),
.PMARSVD0 (8'd0),
.PMARSVD1 (8'd0),
.QPLLRSVD1 (8'd0),
.QPLLRSVD2 (5'd0),
.QPLLRSVD3 (5'd0),
.QPLLRSVD4 (8'd0),
.QPLL0CLKRSVD0 (1'd0),
.QPLL0CLKRSVD1 (1'd0),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'd1),
.QPLL0PD (1'd0),
.QPLL0REFCLKSEL (3'b001),
.QPLL0RESET (qpll_rst),
.QPLL1CLKRSVD0 (1'd0),
.QPLL1CLKRSVD1 (1'd0),
.QPLL1LOCKDETCLK (1'd0),
.QPLL1LOCKEN (1'd0),
.QPLL1PD (1'd1),
.QPLL1REFCLKSEL (3'b001),
.QPLL1RESET (1'd1),
.RCALENB (1'd1),
.DRPDO (up_drp_rdata),
.DRPRDY (up_drp_ready),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLL0FBCLKLOST (),
.QPLL0LOCK (qpll_locked),
.QPLL0OUTCLK (qpll_clk),
.QPLL0OUTREFCLK (qpll_ref_clk),
.QPLL0REFCLKLOST (),
.QPLL1FBCLKLOST (),
.QPLL1LOCK (),
.QPLL1OUTCLK (),
.QPLL1OUTREFCLK (),
.QPLL1REFCLKLOST (),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0_SEL (),
.RXRECCLK1_SEL ());
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

193
library/common/ad_gt_common_1.v
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@ -1,193 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_gt_common_1 #(
parameter integer ID = 0,
parameter integer GTH_OR_GTX_N = 0,
parameter integer QPLL0_ENABLE = 1,
parameter integer QPLL0_REFCLK_DIV = 2,
parameter [26:0] QPLL0_CFG = 27'h06801C1,
parameter integer QPLL0_FBDIV_RATIO = 1'b1,
parameter [ 9:0] QPLL0_FBDIV = 10'b0000110000,
parameter integer QPLL1_ENABLE = 1,
parameter integer QPLL1_REFCLK_DIV = 2,
parameter [26:0] QPLL1_CFG = 27'h06801C1,
parameter integer QPLL1_FBDIV_RATIO = 1'b1,
parameter [ 9:0] QPLL1_FBDIV = 10'b0000110000) (
// reset and clocks
input qpll0_rst,
input qpll0_ref_clk_in,
input qpll1_rst,
input qpll1_ref_clk_in,
output [ 7:0] qpll_clk,
output [ 7:0] qpll_ref_clk,
output [ 7:0] qpll_locked,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals
wire up_drp_qpll0_sel_s;
wire up_drp_qpll0_wr_s;
wire [11:0] up_drp_qpll0_addr_s;
wire [15:0] up_drp_qpll0_wdata_s;
wire [15:0] up_drp_qpll0_rdata_s;
wire up_drp_qpll0_ready_s;
wire up_drp_qpll1_sel_s;
wire up_drp_qpll1_wr_s;
wire [11:0] up_drp_qpll1_addr_s;
wire [15:0] up_drp_qpll1_wdata_s;
wire [15:0] up_drp_qpll1_rdata_s;
wire up_drp_qpll1_ready_s;
// replicate to match channels
assign qpll_clk[1] = qpll_clk[0];
assign qpll_ref_clk[1] = qpll_ref_clk[0];
assign qpll_locked[1] = qpll_locked[0];
assign qpll_clk[2] = qpll_clk[0];
assign qpll_ref_clk[2] = qpll_ref_clk[0];
assign qpll_locked[2] = qpll_locked[0];
assign qpll_clk[3] = qpll_clk[0];
assign qpll_ref_clk[3] = qpll_ref_clk[0];
assign qpll_locked[3] = qpll_locked[0];
assign qpll_clk[5] = qpll_clk[4];
assign qpll_ref_clk[5] = qpll_ref_clk[4];
assign qpll_locked[5] = qpll_locked[4];
assign qpll_clk[6] = qpll_clk[4];
assign qpll_ref_clk[6] = qpll_ref_clk[4];
assign qpll_locked[6] = qpll_locked[4];
assign qpll_clk[7] = qpll_clk[4];
assign qpll_ref_clk[7] = qpll_ref_clk[4];
assign qpll_locked[7] = qpll_locked[4];
// instantiations
ad_gt_common #(
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL_ENABLE (QPLL0_ENABLE),
.QPLL_REFCLK_DIV (QPLL0_REFCLK_DIV),
.QPLL_CFG (QPLL0_CFG),
.QPLL_FBDIV_RATIO (QPLL0_FBDIV_RATIO),
.QPLL_FBDIV (QPLL0_FBDIV))
i_qpll_0 (
.qpll_ref_clk_in (qpll0_ref_clk_in),
.qpll_rst (qpll0_rst),
.qpll_clk (qpll_clk[0]),
.qpll_ref_clk (qpll_ref_clk[0]),
.qpll_locked (qpll_locked[0]),
.up_clk (up_clk),
.up_drp_sel (up_drp_qpll0_sel_s),
.up_drp_addr (up_drp_qpll0_addr_s),
.up_drp_wr (up_drp_qpll0_wr_s),
.up_drp_wdata (up_drp_qpll0_wdata_s),
.up_drp_rdata (up_drp_qpll0_rdata_s),
.up_drp_ready (up_drp_qpll0_ready_s));
ad_gt_common #(
.GTH_OR_GTX_N (GTH_OR_GTX_N),
.QPLL_ENABLE (QPLL1_ENABLE),
.QPLL_REFCLK_DIV (QPLL1_REFCLK_DIV),
.QPLL_CFG (QPLL1_CFG),
.QPLL_FBDIV_RATIO (QPLL1_FBDIV_RATIO),
.QPLL_FBDIV (QPLL1_FBDIV))
i_qpll_1 (
.qpll_ref_clk_in (qpll1_ref_clk_in),
.qpll_rst (qpll1_rst),
.qpll_clk (qpll_clk[4]),
.qpll_ref_clk (qpll_ref_clk[4]),
.qpll_locked (qpll_locked[4]),
.up_clk (up_clk),
.up_drp_sel (up_drp_qpll1_sel_s),
.up_drp_addr (up_drp_qpll1_addr_s),
.up_drp_wr (up_drp_qpll1_wr_s),
.up_drp_wdata (up_drp_qpll1_wdata_s),
.up_drp_rdata (up_drp_qpll1_rdata_s),
.up_drp_ready (up_drp_qpll1_ready_s));
up_gt #(
.GTH_OR_GTX_N (GTH_OR_GTX_N))
i_up (
.up_drp_qpll0_sel (up_drp_qpll0_sel_s),
.up_drp_qpll0_wr (up_drp_qpll0_wr_s),
.up_drp_qpll0_addr (up_drp_qpll0_addr_s),
.up_drp_qpll0_wdata (up_drp_qpll0_wdata_s),
.up_drp_qpll0_rdata (up_drp_qpll0_rdata_s),
.up_drp_qpll0_ready (up_drp_qpll0_ready_s),
.up_drp_qpll1_sel (up_drp_qpll1_sel_s),
.up_drp_qpll1_wr (up_drp_qpll1_wr_s),
.up_drp_qpll1_addr (up_drp_qpll1_addr_s),
.up_drp_qpll1_wdata (up_drp_qpll1_wdata_s),
.up_drp_qpll1_rdata (up_drp_qpll1_rdata_s),
.up_drp_qpll1_ready (up_drp_qpll1_ready_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

759
library/common/ad_gt_es.v
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@ -1,759 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_gt_es #(
parameter integer GTH_OR_GTX_N = 0) (
input lpm_dfe_n,
// drp interface
input up_rstn,
input up_clk,
output reg up_es_drp_sel,
output reg up_es_drp_wr,
output reg [11:0] up_es_drp_addr,
output reg [15:0] up_es_drp_wdata,
input [15:0] up_es_drp_rdata,
input up_es_drp_ready,
// dma interface
output reg up_es_dma_req,
output reg [31:0] up_es_dma_addr,
output reg [31:0] up_es_dma_data,
input up_es_dma_ack,
// processor interface
input up_es_start,
input up_es_stop,
input up_es_init,
input [15:0] up_es_sdata0,
input [15:0] up_es_sdata1,
input [15:0] up_es_sdata2,
input [15:0] up_es_sdata3,
input [15:0] up_es_sdata4,
input [15:0] up_es_qdata0,
input [15:0] up_es_qdata1,
input [15:0] up_es_qdata2,
input [15:0] up_es_qdata3,
input [15:0] up_es_qdata4,
input [ 4:0] up_es_prescale,
input [11:0] up_es_hoffset_min,
input [11:0] up_es_hoffset_max,
input [11:0] up_es_hoffset_step,
input [ 7:0] up_es_voffset_min,
input [ 7:0] up_es_voffset_max,
input [ 7:0] up_es_voffset_step,
input [ 1:0] up_es_voffset_range,
input [31:0] up_es_start_addr,
output reg up_es_status);
localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
localparam [11:0] ES_DRP_SDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036
localparam [11:0] ES_DRP_SDATA1_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037
localparam [11:0] ES_DRP_SDATA2_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038
localparam [11:0] ES_DRP_SDATA3_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039
localparam [11:0] ES_DRP_SDATA4_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a
localparam [11:0] ES_DRP_QDATA0_ADDR = (GTH_OR_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031
localparam [11:0] ES_DRP_QDATA1_ADDR = (GTH_OR_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032
localparam [11:0] ES_DRP_QDATA2_ADDR = (GTH_OR_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033
localparam [11:0] ES_DRP_QDATA3_ADDR = (GTH_OR_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034
localparam [11:0] ES_DRP_QDATA4_ADDR = (GTH_OR_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035
localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
localparam [ 5:0] ES_FSM_IDLE = 6'h00;
localparam [ 5:0] ES_FSM_STATUS = 6'h01;
localparam [ 5:0] ES_FSM_INIT = 6'h02;
localparam [ 5:0] ES_FSM_CTRLINIT_READ = 6'h03;
localparam [ 5:0] ES_FSM_CTRLINIT_RRDY = 6'h04;
localparam [ 5:0] ES_FSM_CTRLINIT_WRITE = 6'h05;
localparam [ 5:0] ES_FSM_CTRLINIT_WRDY = 6'h06;
localparam [ 5:0] ES_FSM_SDATA0_WRITE = 6'h07;
localparam [ 5:0] ES_FSM_SDATA0_WRDY = 6'h08;
localparam [ 5:0] ES_FSM_SDATA1_WRITE = 6'h09;
localparam [ 5:0] ES_FSM_SDATA1_WRDY = 6'h0a;
localparam [ 5:0] ES_FSM_SDATA2_WRITE = 6'h0b;
localparam [ 5:0] ES_FSM_SDATA2_WRDY = 6'h0c;
localparam [ 5:0] ES_FSM_SDATA3_WRITE = 6'h0d;
localparam [ 5:0] ES_FSM_SDATA3_WRDY = 6'h0e;
localparam [ 5:0] ES_FSM_SDATA4_WRITE = 6'h0f;
localparam [ 5:0] ES_FSM_SDATA4_WRDY = 6'h10;
localparam [ 5:0] ES_FSM_QDATA0_WRITE = 6'h11;
localparam [ 5:0] ES_FSM_QDATA0_WRDY = 6'h12;
localparam [ 5:0] ES_FSM_QDATA1_WRITE = 6'h13;
localparam [ 5:0] ES_FSM_QDATA1_WRDY = 6'h14;
localparam [ 5:0] ES_FSM_QDATA2_WRITE = 6'h15;
localparam [ 5:0] ES_FSM_QDATA2_WRDY = 6'h16;
localparam [ 5:0] ES_FSM_QDATA3_WRITE = 6'h17;
localparam [ 5:0] ES_FSM_QDATA3_WRDY = 6'h18;
localparam [ 5:0] ES_FSM_QDATA4_WRITE = 6'h19;
localparam [ 5:0] ES_FSM_QDATA4_WRDY = 6'h1a;
localparam [ 5:0] ES_FSM_HOFFSET_READ = 6'h1b;
localparam [ 5:0] ES_FSM_HOFFSET_RRDY = 6'h1c;
localparam [ 5:0] ES_FSM_HOFFSET_WRITE = 6'h1d;
localparam [ 5:0] ES_FSM_HOFFSET_WRDY = 6'h1e;
localparam [ 5:0] ES_FSM_VOFFSET_READ = 6'h1f;
localparam [ 5:0] ES_FSM_VOFFSET_RRDY = 6'h20;
localparam [ 5:0] ES_FSM_VOFFSET_WRITE = 6'h21;
localparam [ 5:0] ES_FSM_VOFFSET_WRDY = 6'h22;
localparam [ 5:0] ES_FSM_CTRLSTART_READ = 6'h23;
localparam [ 5:0] ES_FSM_CTRLSTART_RRDY = 6'h24;
localparam [ 5:0] ES_FSM_CTRLSTART_WRITE = 6'h25;
localparam [ 5:0] ES_FSM_CTRLSTART_WRDY = 6'h26;
localparam [ 5:0] ES_FSM_STATUS_READ = 6'h27;
localparam [ 5:0] ES_FSM_STATUS_RRDY = 6'h28;
localparam [ 5:0] ES_FSM_CTRLSTOP_READ = 6'h29;
localparam [ 5:0] ES_FSM_CTRLSTOP_RRDY = 6'h2a;
localparam [ 5:0] ES_FSM_CTRLSTOP_WRITE = 6'h2b;
localparam [ 5:0] ES_FSM_CTRLSTOP_WRDY = 6'h2c;
localparam [ 5:0] ES_FSM_SCNT_READ = 6'h2d;
localparam [ 5:0] ES_FSM_SCNT_RRDY = 6'h2e;
localparam [ 5:0] ES_FSM_ECNT_READ = 6'h2f;
localparam [ 5:0] ES_FSM_ECNT_RRDY = 6'h30;
localparam [ 5:0] ES_FSM_DMA_WRITE = 6'h31;
localparam [ 5:0] ES_FSM_DMA_READY = 6'h32;
localparam [ 5:0] ES_FSM_UPDATE = 6'h33;
// internal registers
reg up_es_ut = 'd0;
reg [31:0] up_es_addr = 'd0;
reg [11:0] up_es_hoffset = 'd0;
reg [ 7:0] up_es_voffset = 'd0;
reg [15:0] up_es_hoffset_rdata = 'd0;
reg [15:0] up_es_voffset_rdata = 'd0;
reg [15:0] up_es_ctrl_rdata = 'd0;
reg [15:0] up_es_scnt_rdata = 'd0;
reg [15:0] up_es_ecnt_rdata = 'd0;
reg [ 5:0] up_es_fsm = 'd0;
// internal signals
wire up_es_heos_s;
wire up_es_eos_s;
wire up_es_ut_s;
wire [ 7:0] up_es_voffset_2_s;
wire [ 7:0] up_es_voffset_n_s;
wire [ 7:0] up_es_voffset_s;
// dma interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_es_dma_req <= 'b0;
up_es_dma_addr <= 'd0;
up_es_dma_data <= 'd0;
end else begin
if ((up_es_dma_req == 1'b1) && (up_es_dma_ack == 1'b1)) begin
up_es_dma_req <= 1'b0;
up_es_dma_addr <= 32'd0;
up_es_dma_data <= 32'd0;
end else if (up_es_fsm == ES_FSM_DMA_WRITE) begin
up_es_dma_req <= 1'b1;
up_es_dma_addr <= up_es_addr;
up_es_dma_data <= {up_es_scnt_rdata, up_es_ecnt_rdata};
end
end
end
// prescale, horizontal and vertical offsets
assign up_es_heos_s = (up_es_hoffset == up_es_hoffset_max) ? up_es_ut : 1'b0;
assign up_es_eos_s = (up_es_voffset == up_es_voffset_max) ? up_es_heos_s : 1'b0;
assign up_es_ut_s = up_es_ut & ~lpm_dfe_n;
assign up_es_voffset_2_s = ~up_es_voffset + 1'b1;
assign up_es_voffset_n_s = {1'b1, up_es_voffset_2_s[6:0]};
assign up_es_voffset_s = (up_es_voffset[7] == 1'b1) ? up_es_voffset_n_s : up_es_voffset;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_status <= 1'b0;
up_es_ut <= 'd0;
up_es_addr <= 'd0;
up_es_hoffset <= 'd0;
up_es_voffset <= 'd0;
end else begin
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_status <= 1'b0;
end else begin
up_es_status <= 1'b1;
end
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_ut <= lpm_dfe_n;
up_es_addr <= up_es_start_addr;
up_es_hoffset <= up_es_hoffset_min;
up_es_voffset <= up_es_voffset_min;
end else if (up_es_fsm == ES_FSM_UPDATE) begin
up_es_ut <= ~up_es_ut | lpm_dfe_n;
up_es_addr <= up_es_addr + 3'd4;
if (up_es_heos_s == 1'b1) begin
up_es_hoffset <= up_es_hoffset_min;
end else if (up_es_ut == 1'b1) begin
up_es_hoffset <= up_es_hoffset + up_es_hoffset_step;
end
if (up_es_heos_s == 1'b1) begin
up_es_voffset <= up_es_voffset + up_es_voffset_step;
end
end
end
end
// read-modify-write parameters (gt's are full of mixed up controls)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_hoffset_rdata <= 'd0;
up_es_voffset_rdata <= 'd0;
up_es_ctrl_rdata <= 'd0;
up_es_scnt_rdata <= 'd0;
up_es_ecnt_rdata <= 'd0;
end else begin
if ((up_es_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_hoffset_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_voffset_rdata <= up_es_drp_rdata;
end
if (((up_es_fsm == ES_FSM_CTRLINIT_RRDY) || (up_es_fsm == ES_FSM_CTRLSTART_RRDY) ||
(up_es_fsm == ES_FSM_CTRLSTOP_RRDY)) && (up_es_drp_ready == 1'b1)) begin
up_es_ctrl_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_SCNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_scnt_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_ECNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_ecnt_rdata <= up_es_drp_rdata;
end
end
end
// eye scan state machine- write vertical and horizontal offsets
// and read back sample and error counters
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
if (up_es_stop == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
case (up_es_fsm)
ES_FSM_IDLE: begin // idle
if (up_es_start == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS;
end else begin
up_es_fsm <= ES_FSM_IDLE;
end
end
ES_FSM_STATUS: begin // set status
up_es_fsm <= ES_FSM_INIT;
end
ES_FSM_INIT: begin // initialize
if (up_es_init == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end
end
ES_FSM_CTRLINIT_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
ES_FSM_CTRLINIT_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
end
ES_FSM_CTRLINIT_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
ES_FSM_CTRLINIT_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
end
ES_FSM_SDATA0_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
ES_FSM_SDATA0_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
end
ES_FSM_SDATA1_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
ES_FSM_SDATA1_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
end
ES_FSM_SDATA2_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
ES_FSM_SDATA2_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
end
ES_FSM_SDATA3_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
ES_FSM_SDATA3_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
end
ES_FSM_SDATA4_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
ES_FSM_SDATA4_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
end
ES_FSM_QDATA0_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
ES_FSM_QDATA0_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
end
ES_FSM_QDATA1_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
ES_FSM_QDATA1_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
end
ES_FSM_QDATA2_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
ES_FSM_QDATA2_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
end
ES_FSM_QDATA3_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
ES_FSM_QDATA3_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
end
ES_FSM_QDATA4_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
ES_FSM_QDATA4_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
end
ES_FSM_HOFFSET_READ: begin // horizontal offset read
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
ES_FSM_HOFFSET_RRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
end
ES_FSM_HOFFSET_WRITE: begin // horizontal offset write
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
ES_FSM_HOFFSET_WRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
end
ES_FSM_VOFFSET_READ: begin // vertical offset read
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
ES_FSM_VOFFSET_RRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
end
ES_FSM_VOFFSET_WRITE: begin // vertical offset write
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
ES_FSM_VOFFSET_WRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
end
ES_FSM_CTRLSTART_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
ES_FSM_CTRLSTART_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
end
ES_FSM_CTRLSTART_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
ES_FSM_CTRLSTART_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
end
ES_FSM_STATUS_READ: begin // status read
up_es_fsm <= ES_FSM_STATUS_RRDY;
end
ES_FSM_STATUS_RRDY: begin // status ready
if (up_es_drp_ready == 1'b0) begin
up_es_fsm <= ES_FSM_STATUS_RRDY;
end else if (up_es_drp_rdata[3:0] == 4'b0101) begin
up_es_fsm <= ES_FSM_CTRLSTOP_READ;
end else begin
up_es_fsm <= ES_FSM_STATUS_READ;
end
end
ES_FSM_CTRLSTOP_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
ES_FSM_CTRLSTOP_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
end
ES_FSM_CTRLSTOP_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
ES_FSM_CTRLSTOP_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SCNT_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
end
ES_FSM_SCNT_READ: begin // read sample count
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
ES_FSM_SCNT_RRDY: begin // sample count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_ECNT_READ;
end else begin
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
end
ES_FSM_ECNT_READ: begin // read error count
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
ES_FSM_ECNT_RRDY: begin // error count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_DMA_WRITE;
end else begin
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
end
ES_FSM_DMA_WRITE: begin // dma write
up_es_fsm <= ES_FSM_DMA_READY;
end
ES_FSM_DMA_READY: begin // dma ack
if (up_es_dma_ack == 1'b1) begin
up_es_fsm <= ES_FSM_UPDATE;
end else begin
up_es_fsm <= ES_FSM_DMA_READY;
end
end
ES_FSM_UPDATE: begin // update
if (up_es_eos_s == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else if (up_es_ut == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end
end
default: begin
up_es_fsm <= ES_FSM_IDLE;
end
endcase
end
end
end
// drp signals controlled by the fsm
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_drp_sel <= 'd0;
up_es_drp_wr <= 'd0;
up_es_drp_addr <= 'd0;
up_es_drp_wdata <= 'd0;
end else begin
case (up_es_fsm)
ES_FSM_CTRLINIT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLINIT_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11,
up_es_ctrl_rdata[7:5], up_es_prescale};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:0]};
end
end
ES_FSM_SDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA0_ADDR;
up_es_drp_wdata <= up_es_sdata0;
end
ES_FSM_SDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA1_ADDR;
up_es_drp_wdata <= up_es_sdata1;
end
ES_FSM_SDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA2_ADDR;
up_es_drp_wdata <= up_es_sdata2;
end
ES_FSM_SDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA3_ADDR;
up_es_drp_wdata <= up_es_sdata3;
end
ES_FSM_SDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA4_ADDR;
up_es_drp_wdata <= up_es_sdata4;
end
ES_FSM_QDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA0_ADDR;
up_es_drp_wdata <= up_es_qdata0;
end
ES_FSM_QDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA1_ADDR;
up_es_drp_wdata <= up_es_qdata1;
end
ES_FSM_QDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA2_ADDR;
up_es_drp_wdata <= up_es_qdata2;
end
ES_FSM_QDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA3_ADDR;
up_es_drp_wdata <= up_es_qdata3;
end
ES_FSM_QDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA4_ADDR;
up_es_drp_wdata <= up_es_qdata4;
end
ES_FSM_HOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_HOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_hoffset, up_es_hoffset_rdata[3:0]};
end else begin
up_es_drp_wdata <= {up_es_hoffset_rdata[15:12], up_es_hoffset};
end
end
ES_FSM_VOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_VOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_voffset_rdata[15:11], up_es_voffset_s[7],
up_es_ut_s, up_es_voffset_s[6:0], up_es_voffset_range};
end else begin
up_es_drp_wdata <= {up_es_prescale, up_es_voffset_rdata[10:9],
up_es_ut_s, up_es_voffset_s};
end
end
ES_FSM_CTRLSTART_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTART_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {6'd1, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_STATUS_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_OR_GTX_N == 1) begin
up_es_drp_wdata <= {6'd0, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_SCNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_ECNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_ECNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
default: begin
up_es_drp_sel <= 1'b0;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= 9'h000;
up_es_drp_wdata <= 16'h0000;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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library/common/ad_gt_es_axi.v
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@ -1,366 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_gt_es_axi (
// es interface
input up_rstn,
input up_clk,
input up_es_dma_req_0,
input [31:0] up_es_dma_addr_0,
input [31:0] up_es_dma_data_0,
output reg up_es_dma_ack_0,
output reg up_es_dma_err_0,
input up_es_dma_req_1,
input [31:0] up_es_dma_addr_1,
input [31:0] up_es_dma_data_1,
output reg up_es_dma_ack_1,
output reg up_es_dma_err_1,
input up_es_dma_req_2,
input [31:0] up_es_dma_addr_2,
input [31:0] up_es_dma_data_2,
output reg up_es_dma_ack_2,
output reg up_es_dma_err_2,
input up_es_dma_req_3,
input [31:0] up_es_dma_addr_3,
input [31:0] up_es_dma_data_3,
output reg up_es_dma_ack_3,
output reg up_es_dma_err_3,
input up_es_dma_req_4,
input [31:0] up_es_dma_addr_4,
input [31:0] up_es_dma_data_4,
output reg up_es_dma_ack_4,
output reg up_es_dma_err_4,
input up_es_dma_req_5,
input [31:0] up_es_dma_addr_5,
input [31:0] up_es_dma_data_5,
output reg up_es_dma_ack_5,
output reg up_es_dma_err_5,
input up_es_dma_req_6,
input [31:0] up_es_dma_addr_6,
input [31:0] up_es_dma_data_6,
output reg up_es_dma_ack_6,
output reg up_es_dma_err_6,
input up_es_dma_req_7,
input [31:0] up_es_dma_addr_7,
input [31:0] up_es_dma_data_7,
output reg up_es_dma_ack_7,
output reg up_es_dma_err_7,
// axi4 interface
output reg axi_awvalid,
output reg [31:0] axi_awaddr,
output [ 2:0] axi_awprot,
input axi_awready,
output reg axi_wvalid,
output reg [31:0] axi_wdata,
output [ 3:0] axi_wstrb,
input axi_wready,
input axi_bvalid,
input [ 1:0] axi_bresp,
output axi_bready,
output axi_arvalid,
output [31:0] axi_araddr,
output [ 2:0] axi_arprot,
input axi_arready,
input axi_rvalid,
input [ 1:0] axi_rresp,
input [31:0] axi_rdata,
output axi_rready);
localparam [ 3:0] AXI_FSM_SCAN_0 = 4'h0;
localparam [ 3:0] AXI_FSM_SCAN_1 = 4'h1;
localparam [ 3:0] AXI_FSM_SCAN_2 = 4'h2;
localparam [ 3:0] AXI_FSM_SCAN_3 = 4'h3;
localparam [ 3:0] AXI_FSM_SCAN_4 = 4'h4;
localparam [ 3:0] AXI_FSM_SCAN_5 = 4'h5;
localparam [ 3:0] AXI_FSM_SCAN_6 = 4'h6;
localparam [ 3:0] AXI_FSM_SCAN_7 = 4'h7;
localparam [ 3:0] AXI_FSM_WRITE = 4'h8;
localparam [ 3:0] AXI_FSM_WAIT = 4'h9;
localparam [ 3:0] AXI_FSM_ACK = 4'ha;
// internal registers
reg axi_error = 'd0;
reg [ 2:0] axi_sel = 'd0;
reg [ 3:0] axi_fsm = 'd0;
// axi write interface
assign axi_awprot = 3'd0;
assign axi_wstrb = 4'hf;
assign axi_bready = 1'd1;
assign axi_arvalid = 1'd0;
assign axi_araddr = 32'd0;
assign axi_arprot = 3'd0;
assign axi_rready = 1'd1;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_es_dma_ack_0 <= 1'b0;
up_es_dma_err_0 <= 1'b0;
up_es_dma_ack_1 <= 1'b0;
up_es_dma_err_1 <= 1'b0;
up_es_dma_ack_2 <= 1'b0;
up_es_dma_err_2 <= 1'b0;
up_es_dma_ack_3 <= 1'b0;
up_es_dma_err_3 <= 1'b0;
up_es_dma_ack_4 <= 1'b0;
up_es_dma_err_4 <= 1'b0;
up_es_dma_ack_5 <= 1'b0;
up_es_dma_err_5 <= 1'b0;
up_es_dma_ack_6 <= 1'b0;
up_es_dma_err_6 <= 1'b0;
up_es_dma_ack_7 <= 1'b0;
up_es_dma_err_7 <= 1'b0;
end else begin
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd0)) begin
up_es_dma_ack_0 <= 1'b1;
up_es_dma_err_0 <= axi_error;
end else begin
up_es_dma_ack_0 <= 1'b0;
up_es_dma_err_0 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd1)) begin
up_es_dma_ack_1 <= 1'b1;
up_es_dma_err_1 <= axi_error;
end else begin
up_es_dma_ack_1 <= 1'b0;
up_es_dma_err_1 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd2)) begin
up_es_dma_ack_2 <= 1'b1;
up_es_dma_err_2 <= axi_error;
end else begin
up_es_dma_ack_2 <= 1'b0;
up_es_dma_err_2 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd3)) begin
up_es_dma_ack_3 <= 1'b1;
up_es_dma_err_3 <= axi_error;
end else begin
up_es_dma_ack_3 <= 1'b0;
up_es_dma_err_3 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd4)) begin
up_es_dma_ack_4 <= 1'b1;
up_es_dma_err_4 <= axi_error;
end else begin
up_es_dma_ack_4 <= 1'b0;
up_es_dma_err_4 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd5)) begin
up_es_dma_ack_5 <= 1'b1;
up_es_dma_err_5 <= axi_error;
end else begin
up_es_dma_ack_5 <= 1'b0;
up_es_dma_err_5 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd6)) begin
up_es_dma_ack_6 <= 1'b1;
up_es_dma_err_6 <= axi_error;
end else begin
up_es_dma_ack_6 <= 1'b0;
up_es_dma_err_6 <= 1'b0;
end
if ((axi_fsm == AXI_FSM_ACK) && (axi_sel == 3'd7)) begin
up_es_dma_ack_7 <= 1'b1;
up_es_dma_err_7 <= axi_error;
end else begin
up_es_dma_ack_7 <= 1'b0;
up_es_dma_err_7 <= 1'b0;
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
axi_awvalid <= 'b0;
axi_awaddr <= 'd0;
axi_wvalid <= 'b0;
axi_wdata <= 'd0;
axi_error <= 'd0;
end else begin
if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awvalid <= 1'b0;
axi_awaddr <= 32'd0;
end else if (axi_fsm == AXI_FSM_WRITE) begin
axi_awvalid <= 1'b1;
case (axi_sel)
3'b000: axi_awaddr <= up_es_dma_addr_0;
3'b001: axi_awaddr <= up_es_dma_addr_1;
3'b010: axi_awaddr <= up_es_dma_addr_2;
3'b011: axi_awaddr <= up_es_dma_addr_3;
3'b100: axi_awaddr <= up_es_dma_addr_4;
3'b101: axi_awaddr <= up_es_dma_addr_5;
3'b110: axi_awaddr <= up_es_dma_addr_6;
default: axi_awaddr <= up_es_dma_addr_7;
endcase
end
if ((axi_wvalid == 1'b1) && (axi_wready == 1'b1)) begin
axi_wvalid <= 1'b0;
axi_wdata <= 32'd0;
end else if (axi_fsm == AXI_FSM_WRITE) begin
axi_wvalid <= 1'b1;
case (axi_sel)
3'b000: axi_wdata <= up_es_dma_data_0;
3'b001: axi_wdata <= up_es_dma_data_1;
3'b010: axi_wdata <= up_es_dma_data_2;
3'b011: axi_wdata <= up_es_dma_data_3;
3'b100: axi_wdata <= up_es_dma_data_4;
3'b101: axi_wdata <= up_es_dma_data_5;
3'b110: axi_wdata <= up_es_dma_data_6;
default: axi_wdata <= up_es_dma_data_7;
endcase
end
if (axi_bvalid == 1'b1) begin
axi_error <= axi_bresp[1] | axi_bresp[0];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
axi_sel <= 3'd0;
axi_fsm <= AXI_FSM_SCAN_0;
end else begin
case (axi_fsm)
AXI_FSM_SCAN_0: begin
axi_sel <= 3'd0;
if (up_es_dma_req_0 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_1;
end
end
AXI_FSM_SCAN_1: begin
axi_sel <= 3'd1;
if (up_es_dma_req_1 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_2;
end
end
AXI_FSM_SCAN_2: begin
axi_sel <= 3'd2;
if (up_es_dma_req_2 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_3;
end
end
AXI_FSM_SCAN_3: begin
axi_sel <= 3'd3;
if (up_es_dma_req_3 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_4;
end
end
AXI_FSM_SCAN_4: begin
axi_sel <= 3'd4;
if (up_es_dma_req_4 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_5;
end
end
AXI_FSM_SCAN_5: begin
axi_sel <= 3'd5;
if (up_es_dma_req_5 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_6;
end
end
AXI_FSM_SCAN_6: begin
axi_sel <= 3'd6;
if (up_es_dma_req_6 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_7;
end
end
AXI_FSM_SCAN_7: begin
axi_sel <= 3'd7;
if (up_es_dma_req_7 == 1'b1) begin
axi_fsm <= AXI_FSM_WRITE;
end else begin
axi_fsm <= AXI_FSM_SCAN_0;
end
end
AXI_FSM_WRITE: begin
axi_sel <= axi_sel;
axi_fsm <= AXI_FSM_WAIT;
end
AXI_FSM_WAIT: begin
axi_sel <= axi_sel;
if (axi_bvalid == 1'b1) begin
axi_fsm <= AXI_FSM_ACK;
end else begin
axi_fsm <= AXI_FSM_WAIT;
end
end
AXI_FSM_ACK: begin
axi_sel <= axi_sel;
case (axi_sel)
3'b000: axi_fsm <= AXI_FSM_SCAN_1;
3'b001: axi_fsm <= AXI_FSM_SCAN_2;
3'b010: axi_fsm <= AXI_FSM_SCAN_3;
3'b011: axi_fsm <= AXI_FSM_SCAN_4;
3'b100: axi_fsm <= AXI_FSM_SCAN_5;
3'b101: axi_fsm <= AXI_FSM_SCAN_6;
3'b110: axi_fsm <= AXI_FSM_SCAN_7;
default: axi_fsm <= AXI_FSM_SCAN_0;
endcase
end
default: begin
axi_fsm <= AXI_FSM_SCAN_0;
end
endcase
end
end
endmodule
// ***************************************************************************
// ***************************************************************************