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axi_dmac: 2d_transfer: Remove resets from data path 

The data path register of the 2d_transfer module are qualified by the
corresponding valid signal. Their content is not used until they have been
explicitly initialized. There is no need to reset them explicitly.

This reduces the fan-out of the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-05-12 14:04:26 +02:00 committed by Lars-Peter Clausen
parent 6b7a46410c
commit 6bc1eae48d
1 changed files with 49 additions and 47 deletions
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96
library/axi_dmac/2d_transfer.v
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@ -63,76 +63,78 @@ module dmac_2d_transfer #(
input out_eot
);
reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address;
reg [DMA_LENGTH_WIDTH-1:0] x_length;
reg [DMA_LENGTH_WIDTH-1:0] y_length;
reg [DMA_LENGTH_WIDTH-1:0] dest_stride;
reg [DMA_LENGTH_WIDTH-1:0] src_stride;
reg [31:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00;
reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0;
reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00;
reg [1:0] req_id;
reg [1:0] eot_id;
reg [3:0] last_req;
reg [1:0] req_id = 'h00;
reg [1:0] eot_id = 'h00;
reg [3:0] last_req = 'h00;
wire out_last;
assign out_req_dest_address = dest_address;
assign out_req_src_address = src_address;
assign out_req_length = x_length;
assign out_last = y_length == 'h00;
always @(posedge req_aclk)
begin
always @(posedge req_aclk) begin
if (req_aresetn == 1'b0) begin
req_id <= 2'b0;
eot_id <= 2'b0;
req_eot <= 1'b0;
end else begin
if (out_req_valid && out_req_ready) begin
if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
req_id <= req_id + 1'b1;
last_req[req_id] <= y_length == 0;
end
req_eot <= 1'b0;
if (out_eot) begin
if (out_eot == 1'b1) begin
eot_id <= eot_id + 1'b1;
req_eot <= last_req[eot_id];
end else begin
req_eot <= 1'b0;
end
end
end
always @(posedge req_aclk)
begin
always @(posedge req_aclk) begin
if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
last_req[req_id] <= out_last;
end
end
always @(posedge req_aclk) begin
if (req_ready == 1'b1 && req_valid == 1'b1) begin
dest_address <= req_dest_address;
src_address <= req_src_address;
x_length <= req_x_length;
y_length <= req_y_length;
dest_stride <= req_dest_stride;
src_stride <= req_src_stride;
out_req_sync_transfer_start <= req_sync_transfer_start;
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
end
end
always @(posedge req_aclk) begin
if (req_aresetn == 1'b0) begin
dest_address <= 'h00;
src_address <= 'h00;
x_length <= 'h00;
y_length <= 'h00;
dest_stride <= 'h00;
src_stride <= 'h00;
req_ready <= 1'b1;
out_req_valid <= 1'b0;
out_req_sync_transfer_start <= 1'b0;
end else begin
if (req_ready) begin
if (req_valid) begin
dest_address <= req_dest_address;
src_address <= req_src_address;
x_length <= req_x_length;
y_length <= req_y_length;
dest_stride <= req_dest_stride;
src_stride <= req_src_stride;
out_req_sync_transfer_start <= req_sync_transfer_start;
req_ready <= 1'b0;
out_req_valid <= 1'b1;
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin
out_req_valid <= 1'b0;
req_ready <= 1'b1;
end
end
if (req_ready == 1'b1 && req_valid == 1'b1) begin
req_ready <= 1'b0;
out_req_valid <= 1'b1;
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 &&
out_last == 1'b1) begin
out_req_valid <= 1'b0;
req_ready <= 1'b1;
end
end
end