From 6bc05fc844573c90c29cf61cc996544e1343db21 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Mon, 16 May 2016 12:17:19 -0400
Subject: [PATCH] ad_*_in: register post-iob

---
 library/common/altera/ad_cmos_in.v | 21 ++++++++++++++++++---
 library/common/altera/ad_lvds_in.v | 21 ++++++++++++++++++---
 2 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v
index b424cc440..4860361ea 100644
--- a/library/common/altera/ad_cmos_in.v
+++ b/library/common/altera/ad_cmos_in.v
@@ -86,6 +86,16 @@ module ad_cmos_in (
   input               delay_rst;
   output              delay_locked;
 
+  // internal registers
+
+  reg                 rx_data_p = 'd0;
+  reg                 rx_data_n = 'd0;
+
+  // internal signals
+
+  wire                rx_data_p_s;
+  wire                rx_data_n_s;
+
   // defaults
 
   assign up_drdata = 5'd0;
@@ -98,7 +108,7 @@ module ad_cmos_in (
   alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in),
-    .dout ({rx_data_p, rx_data_n}));
+    .dout ({rx_data_p_s, rx_data_n_s}));
   end
   endgenerate
 
@@ -107,8 +117,8 @@ module ad_cmos_in (
   altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
     .inclock (rx_clk),
     .datain (rx_data_in),
-    .dataout_h (rx_data_p),
-    .dataout_l (rx_data_n),
+    .dataout_h (rx_data_p_s),
+    .dataout_l (rx_data_n_s),
     .inclocken (1'b1),
     .aclr (1'b0),
     .aset (1'b0),
@@ -117,6 +127,11 @@ module ad_cmos_in (
   end
   endgenerate
 
+  always @(posedge rx_clk) begin
+    rx_data_p <= rx_data_p_s;
+    rx_data_n <= rx_data_n_s;
+  end
+
 endmodule
 
 // ***************************************************************************
diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v
index 08dd863f1..91774bdf1 100644
--- a/library/common/altera/ad_lvds_in.v
+++ b/library/common/altera/ad_lvds_in.v
@@ -88,6 +88,16 @@ module ad_lvds_in (
   input               delay_rst;
   output              delay_locked;
 
+  // internal registers
+
+  reg                 rx_data_p = 'd0;
+  reg                 rx_data_n = 'd0;
+
+  // internal signals
+
+  wire                rx_data_p_s;
+  wire                rx_data_n_s;
+
   // defaults
 
   assign up_drdata = 5'd0;
@@ -100,7 +110,7 @@ module ad_lvds_in (
   alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in_p),
-    .dout ({rx_data_p, rx_data_n}));
+    .dout ({rx_data_p_s, rx_data_n_s}));
   end
   endgenerate
 
@@ -109,8 +119,8 @@ module ad_lvds_in (
   altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
     .inclock (rx_clk),
     .datain (rx_data_in_p),
-    .dataout_h (rx_data_p),
-    .dataout_l (rx_data_n),
+    .dataout_h (rx_data_p_s),
+    .dataout_l (rx_data_n_s),
     .inclocken (1'b1),
     .aclr (1'b0),
     .aset (1'b0),
@@ -119,6 +129,11 @@ module ad_lvds_in (
   end
   endgenerate
 
+  always @(posedge rx_clk) begin
+    rx_data_p <= rx_data_p_s;
+    rx_data_n <= rx_data_n_s;
+  end
+
 endmodule
 
 // ***************************************************************************