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avl_dacfifo: End of burst is not always end of a transaction 

The XFER_END state defines the end of a transaction, when the entire
data set is written or read to/from the DDRx memory.
A transaction can contain multiple Avalon bursts. Make sure that the FSM
goes back into staging phase at the end of each burst; also define a
signals which indicate the end of each burst for control.
main
Istvan Csomortani 2017-12-09 09:56:33 +00:00
parent ba24909a25
commit 6bbf1ae83c
1 changed files with 5 additions and 4 deletions
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9
library/altera/avl_dacfifo/avl_dacfifo_rd.v
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@ -220,7 +220,7 @@ module avl_dacfifo_rd #(
if (avl_burstcounter < avl_burstcount) begin if (avl_burstcounter < avl_burstcount) begin
avl_read_state <= XFER_FULL_BURST; avl_read_state <= XFER_FULL_BURST;
end else begin end else begin
avl_read_state <= XFER_END; avl_read_state <= XFER_STAGING;
end end
end end
// Avalon transaction with the remaining data, burst length is less than // Avalon transaction with the remaining data, burst length is less than
@ -246,6 +246,7 @@ module avl_dacfifo_rd #(
assign avl_read_int_s = ((avl_read_state == XFER_FULL_BURST) || assign avl_read_int_s = ((avl_read_state == XFER_FULL_BURST) ||
(avl_read_state == XFER_PARTIAL_BURST)) ? 1 : 0; (avl_read_state == XFER_PARTIAL_BURST)) ? 1 : 0;
assign avl_end_of_burst_s = (avl_burstcount == avl_burstcounter) ? 1 : 0;
// Avalon address generation and read control signaling // Avalon address generation and read control signaling
@ -253,7 +254,7 @@ module avl_dacfifo_rd #(
if (avl_fifo_reset_s == 1'b1) begin if (avl_fifo_reset_s == 1'b1) begin
avl_address <= AVL_DDR_BASE_ADDRESS; avl_address <= AVL_DDR_BASE_ADDRESS;
end else begin end else begin
if (avl_read_state == XFER_END) begin if (avl_end_of_burst_s == 1'b1) begin
avl_address <= (avl_address < avl_last_address) ? avl_address + (avl_burstcount * AVL_BYTE_DATA_WIDTH) : AVL_DDR_BASE_ADDRESS; avl_address <= (avl_address < avl_last_address) ? avl_address + (avl_burstcount * AVL_BYTE_DATA_WIDTH) : AVL_DDR_BASE_ADDRESS;
end end
end end
@ -274,7 +275,7 @@ module avl_dacfifo_rd #(
end else if ((avl_read == 1'b1) && (avl_waitrequest == 1'b0)) begin end else if ((avl_read == 1'b1) && (avl_waitrequest == 1'b0)) begin
avl_read <= 1'b0; avl_read <= 1'b0;
end end
if (avl_read_state == XFER_END) begin if (avl_end_of_burst_s == 1'b1) begin
avl_inread <= 1'b0; avl_inread <= 1'b0;
end end
end end
@ -288,7 +289,7 @@ module avl_dacfifo_rd #(
end else begin end else begin
if ((avl_read_int == 1'b1) && (avl_readdatavalid == 1'b1)) begin if ((avl_read_int == 1'b1) && (avl_readdatavalid == 1'b1)) begin
avl_burstcounter <= (avl_burstcounter < avl_burstcount) ? avl_burstcounter + 1'b1 : 1'b0; avl_burstcounter <= (avl_burstcounter < avl_burstcount) ? avl_burstcounter + 1'b1 : 1'b0;
end else if (avl_read_state == XFER_END) begin end else if (avl_end_of_burst_s == 1'b1) begin
avl_burstcounter <= 8'b0; avl_burstcounter <= 8'b0;
end end
end end