library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2

main
Adrian Costina 2015-08-20 18:17:38 +03:00
parent 6ae0c8f85e
commit 6b99ce2482
28 changed files with 44 additions and 85 deletions

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@ -13,6 +13,7 @@ adi_ip_files axi_ad6676 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad6676_pnmon.v" \
"axi_ad6676_channel.v" \
"axi_ad6676_if.v" \
@ -20,8 +21,6 @@ adi_ip_files axi_ad6676 [list \
"axi_ad6676.v" ]
adi_ip_properties axi_ad6676
adi_ip_constraints axi_ad6676 [list \
"axi_ad6676_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -19,6 +19,7 @@ adi_ip_files axi_ad9122 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9122_channel.v" \
"axi_ad9122_core.v" \
"axi_ad9122_if.v" \
@ -27,9 +28,6 @@ adi_ip_files axi_ad9122 [list \
adi_ip_properties axi_ad9122
adi_ip_constraints axi_ad9122 [list \
"axi_ad9122_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

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@ -16,17 +16,14 @@ adi_ip_files axi_ad9144 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9144_channel.v" \
"axi_ad9144_core.v" \
"axi_ad9144_if.v" \
"axi_ad9144.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
"axi_ad9144.v" ]
adi_ip_properties axi_ad9144
adi_ip_constraints axi_ad9144 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -16,6 +16,7 @@ adi_ip_files axi_ad9152 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9152_channel.v" \
"axi_ad9152_core.v" \
"axi_ad9152_if.v" \
@ -24,9 +25,6 @@ adi_ip_files axi_ad9152 [list \
adi_ip_properties axi_ad9152
adi_ip_constraints axi_ad9152 [list \
"axi_ad9152_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -13,6 +13,7 @@ adi_ip_files axi_ad9234 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9234_pnmon.v" \
"axi_ad9234_channel.v" \
"axi_ad9234_if.v" \
@ -21,9 +22,6 @@ adi_ip_files axi_ad9234 [list \
adi_ip_properties axi_ad9234
adi_ip_constraints axi_ad9234 [list \
"axi_ad9234_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -14,6 +14,7 @@ adi_ip_files axi_ad9250 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9250_pnmon.v" \
"axi_ad9250_channel.v" \
"axi_ad9250_if.v" \
@ -22,9 +23,6 @@ adi_ip_files axi_ad9250 [list \
adi_ip_properties axi_ad9250
adi_ip_constraints axi_ad9250 [list \
"axi_ad9250_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -18,6 +18,7 @@ adi_ip_files axi_ad9265 [list \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9265_pnmon.v" \
"axi_ad9265_if.v" \
"axi_ad9265_channel.v" \
@ -26,9 +27,6 @@ adi_ip_files axi_ad9265 [list \
adi_ip_properties axi_ad9265
adi_ip_constraints axi_ad9265 [list \
"axi_ad9265_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

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@ -31,6 +31,7 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9361_dev_if.v" \
"axi_ad9361_rx_pnmon.v" \
"axi_ad9361_rx_channel.v" \
@ -43,14 +44,14 @@ adi_ip_files axi_ad9361 [list \
"axi_ad9361.v" ]
adi_ip_properties axi_ad9361
adi_ip_constraints axi_ad9361 "axi_ad9361_constr.xdc" "late"
set_property physical_name {s_axi_aclk} [ipx::get_port_maps CLK \
-of_objects [ipx::get_bus_interfaces s_axi_signal_clock -of_objects [ipx::current_core]]]
#set_property physical_name {s_axi_aclk} [ipx::get_port_maps CLK \
# -of_objects [ipx::get_bus_interfaces s_axi_signal_clock -of_objects [ipx::current_core]]]
ipx::remove_bus_interface {signal_clock} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -18,6 +18,7 @@ adi_ip_files axi_ad9434 [list \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9434_if.v" \
"axi_ad9434_pnmon.v" \
"axi_ad9434_core.v" \
@ -26,9 +27,6 @@ adi_ip_files axi_ad9434 [list \
adi_ip_properties axi_ad9434
adi_ip_constraints axi_ad9434 [list \
"axi_ad9434_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

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@ -17,6 +17,7 @@ adi_ip_files axi_ad9467 [list \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9467_pnmon.v" \
"axi_ad9467_if.v" \
"axi_ad9467_channel.v" \
@ -25,9 +26,6 @@ adi_ip_files axi_ad9467 [list \
adi_ip_properties axi_ad9467
adi_ip_constraints axi_ad9467 [list \
"axi_ad9467_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -15,6 +15,7 @@ adi_ip_files axi_ad9625 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9625_pnmon.v" \
"axi_ad9625_channel.v" \
"axi_ad9625_if.v" \
@ -23,9 +24,6 @@ adi_ip_files axi_ad9625 [list \
adi_ip_properties axi_ad9625
adi_ip_constraints axi_ad9625 [list \
"axi_ad9625_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]

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@ -20,6 +20,7 @@ adi_ip_files axi_ad9643 [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9643_pnmon.v" \
"axi_ad9643_channel.v" \
"axi_ad9643_if.v" \
@ -28,9 +29,6 @@ adi_ip_files axi_ad9643 [list \
adi_ip_properties axi_ad9643
adi_ip_constraints axi_ad9643 [list \
"axi_ad9643_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]]

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@ -19,6 +19,7 @@ adi_ip_files axi_ad9652 [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9652_pnmon.v" \
"axi_ad9652_channel.v" \
"axi_ad9652_if.v" \
@ -27,9 +28,6 @@ adi_ip_files axi_ad9652 [list \
adi_ip_properties axi_ad9652
adi_ip_constraints axi_ad9652 [list \
"axi_ad9652_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]]

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@ -15,6 +15,7 @@ adi_ip_files axi_ad9671 [list \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9671_pnmon.v" \
"axi_ad9671_channel.v" \
"axi_ad9671_if.v" \
@ -23,9 +24,6 @@ adi_ip_files axi_ad9671 [list \
adi_ip_properties axi_ad9671
adi_ip_constraints axi_ad9671 [list \
"axi_ad9671_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]

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@ -14,6 +14,7 @@ adi_ip_files axi_ad9680 [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9680_pnmon.v" \
"axi_ad9680_channel.v" \
"axi_ad9680_if.v" \
@ -22,9 +23,6 @@ adi_ip_files axi_ad9680 [list \
adi_ip_properties axi_ad9680
adi_ip_constraints axi_ad9680 [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -17,6 +17,7 @@ adi_ip_files axi_ad9739a [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9739a_channel.v" \
"axi_ad9739a_core.v" \
"axi_ad9739a_if.v" \
@ -25,9 +26,6 @@ adi_ip_files axi_ad9739a [list \
adi_ip_properties axi_ad9739a
adi_ip_constraints axi_ad9739a [list \
"axi_ad9739a_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]

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@ -9,6 +9,7 @@ adi_ip_files axi_adcfifo [list \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_adcfifo_adc.v" \
"axi_adcfifo_dma.v" \
"axi_adcfifo_wr.v" \
@ -17,8 +18,6 @@ adi_ip_files axi_adcfifo [list \
"axi_adcfifo_constr.xdc" ]
adi_ip_properties_lite axi_adcfifo
adi_ip_constraints axi_adcfifo [list \
"axi_adcfifo_constr.xdc" ]
ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]

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@ -9,18 +9,18 @@ adi_ip_files axi_clkgen [list \
"$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_clkgen.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_clkgen_constr.xdc" \
"axi_clkgen.v" ]
adi_ip_properties axi_clkgen
adi_ip_constraints axi_clkgen [list \
"axi_clkgen_constr.xdc" ]
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
ipx::remove_bus_interface {signal_clock} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
#set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
# [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
ipx::save_core [ipx::current_core]

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@ -13,6 +13,7 @@ adi_ip_files axi_generic_adc [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_generic_adc.v" \
]

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@ -16,6 +16,7 @@ adi_ip_files axi_hdmi_rx [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_hdmi_rx.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_hdmi_rx.v" \
"axi_hdmi_rx_es.v" \
"axi_hdmi_rx_tpm.v" \
@ -23,8 +24,6 @@ adi_ip_files axi_hdmi_rx [list \
"axi_hdmi_rx_core.v" ]
adi_ip_properties axi_hdmi_rx
adi_ip_constraints axi_hdmi_rx [list \
"axi_hdmi_rx_constr.xdc" ]
ipx::save_core [ipx::current_core]

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@ -18,6 +18,7 @@ adi_ip_files axi_hdmi_tx [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_hdmi_tx.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_hdmi_tx_constr.xdc" \
"axi_hdmi_tx_vdma.v" \
"axi_hdmi_tx_es.v" \
@ -26,9 +27,5 @@ adi_ip_files axi_hdmi_tx [list \
adi_ip_properties axi_hdmi_tx
adi_ip_constraints axi_hdmi_tx [list \
"axi_hdmi_tx_constr.xdc" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
ipx::save_core [ipx::current_core]

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@ -10,6 +10,7 @@ adi_ip_files axi_i2s_adi [list \
"$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"i2s_controller.vhd" \
"i2s_rx.vhd" \
"i2s_tx.vhd" \
@ -20,7 +21,6 @@ adi_ip_files axi_i2s_adi [list \
]
adi_ip_properties_lite axi_i2s_adi
adi_ip_constraints axi_spdif_tx axi_i2s_adi_constr.xdc late
adi_add_bus "DMA_ACK_RX" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \

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@ -17,20 +17,18 @@ adi_ip_files axi_jesd_gt [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_gt_channel.v" \
"$ad_hdl_dir/library/common/up_gt.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_jesd_gt.v" ]
adi_ip_properties axi_jesd_gt
adi_ip_constraints axi_jesd_gt [list \
"axi_jesd_gt_constr.xdc" ]
#set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
# -of_objects [ipx::get_bus_interfaces axi_signal_clock \
# -of_objects [ipx::current_core]]]
set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
-of_objects [ipx::get_bus_interfaces axi_signal_clock \
-of_objects [ipx::current_core]]]
set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \
-of_objects [ipx::get_bus_interfaces axi_signal_clock \
-of_objects [ipx::current_core]]]
#set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \
# -of_objects [ipx::get_bus_interfaces axi_signal_clock \
# -of_objects [ipx::current_core]]]
adi_if_infer_bus ADI:user:if_gt_qpll slave gt_qpll_0 [list \
"qpll_rst qpll0_rst "\

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@ -14,6 +14,7 @@ adi_ip_files axi_mc_controller [list \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"motor_driver.v" \
"delay.v" \
"control_registers.v" \
@ -22,9 +23,6 @@ adi_ip_files axi_mc_controller [list \
adi_ip_properties axi_mc_controller
adi_ip_constraints axi_mc_controller [list \
"axi_mc_controller_constr.xdc" ]
ipx::save_core [ipx::current_core]

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@ -13,6 +13,7 @@ adi_ip_files axi_mc_current_monitor [list \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"dec256sinc24b.v" \
"ad7401.v" \
"axi_mc_current_monitor_constr.xdc" \
@ -20,9 +21,6 @@ adi_ip_files axi_mc_current_monitor [list \
adi_ip_properties axi_mc_current_monitor
adi_ip_constraints axi_mc_current_monitor [list \
"axi_mc_current_monitor_constr.xdc" ]
ipx::save_core [ipx::current_core]

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@ -13,6 +13,7 @@ adi_ip_files axi_mc_speed [list \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"debouncer.v" \
"speed_detector.v" \
"delay_30_degrees.v" \
@ -21,9 +22,6 @@ adi_ip_files axi_mc_speed [list \
adi_ip_properties axi_mc_speed
adi_ip_constraints axi_mc_speed [list \
"axi_mc_speed_constr.xdc" ]
ipx::save_core [ipx::current_core]

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@ -9,6 +9,7 @@ adi_ip_files axi_spdif_rx [list \
"$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"rx_phase_det.vhd" \
"rx_package.vhd" \
"rx_decode.vhd" \
@ -17,7 +18,6 @@ adi_ip_files axi_spdif_rx [list \
"axi_spdif_rx_constr.xdc"]
adi_ip_properties_lite axi_spdif_rx
adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc
adi_add_bus "DMA_ACK" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \

View File

@ -9,13 +9,13 @@ adi_ip_files axi_spdif_tx [list \
"$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \
"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"tx_package.vhd" \
"tx_encoder.vhd" \
"axi_spdif_tx.vhd" \
"axi_spdif_tx_constr.xdc" ]
adi_ip_properties_lite axi_spdif_tx
adi_ip_constraints axi_spdif_tx axi_spdif_tx_constr.xdc
adi_add_bus "DMA_ACK" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \