ad463x_data_capture: Initial commit
IP required to support echo and master clock modemain
Istvan Csomortani
sarpadi
parent
5ac64b021f
commit
6a526f4bb6
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@ -13,6 +13,7 @@ all: lib
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clean:
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$(MAKE) -C ad463x_data_capture clean
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$(MAKE) -C axi_ad5766 clean
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$(MAKE) -C axi_ad6676 clean
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$(MAKE) -C axi_ad7616 clean
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@ -135,6 +136,7 @@ clean-all:clean
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lib:
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$(MAKE) -C ad463x_data_capture
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$(MAKE) -C axi_ad5766
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$(MAKE) -C axi_ad6676
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$(MAKE) -C axi_ad7616
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@ -0,0 +1,13 @@
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####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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### SPDX short identifier: BSD-1-Clause
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := ad463x_data_capture
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GENERIC_DEPS += ad463x_data_capture.v
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XILINX_DEPS += ad463x_data_capture_ip.tcl
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include ../scripts/library.mk
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@ -0,0 +1,134 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// The AD4630-24 device requires this module to capture data in master and
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// echo clock mode, because the data is clocked by the BUSY/SCLKOUT line,
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// independent from the SPI interface
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module ad463x_data_capture #(
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parameter DDR_EN = 0,
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parameter NUM_OF_LANES = 2,
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parameter DATA_WIDTH = 32
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) (
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input clk, // core clock of the SPIE
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input csn, // CSN (chip select)
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input echo_sclk, // BUSY/SCLKOUT
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input [NUM_OF_LANES-1:0] data_in, // serial data lines
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output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines
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output m_axis_valid, // data validation
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input m_axis_ready // NOTE: back pressure is ignored
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);
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reg csn_d;
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wire reset;
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always @(posedge clk) begin
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csn_d <= csn;
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end
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// negative edge resets the shift registers
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assign reset = ~csn & csn_d;
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// CSN positive edge validates the output data
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// WARNING: there isn't any buffering for data, if the sink module is not
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// ready, the data will be discarded
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assign m_axis_valid = csn & ~csn_d & m_axis_ready;
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genvar i, j;
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generate
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if (DDR_EN) // Double Data Rate mode
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begin
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for (i=0; i<NUM_OF_LANES; i=i+1) begin
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reg [DATA_WIDTH-1:0] data_shift_p;
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reg [DATA_WIDTH-1:0] data_shift_n;
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// shift register for positive edge
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always @(negedge echo_sclk or posedge reset) begin
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if (reset) begin
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data_shift_n <= 0;
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end else begin
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data_shift_n <= {data_shift_n, data_in[i]};
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end
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end
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// shift register for positive edge
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always @(posedge echo_sclk or posedge reset) begin
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if (reset) begin
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data_shift_p <= 0;
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end else begin
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data_shift_p <= {data_shift_p, data_in[i]};
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end
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end
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// DDR output logic - only the first 16 bits are forwarded
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for (j=0; j<DATA_WIDTH/2; j=j+1) begin
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assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]};
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end
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end /* for loop */
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end else begin // Single Data Rate mode
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for (i=0; i<NUM_OF_LANES; i=i+1) begin
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reg [DATA_WIDTH-1:0] data_shift_n;
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// shift register for positive edge
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always @(negedge echo_sclk or posedge reset) begin
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if (reset) begin
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data_shift_n <= 0;
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end else begin
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data_shift_n <= {data_shift_n, data_in[i]};
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end
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end
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// SDR output logic
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assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
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end /* for loop */
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end
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endgenerate
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endmodule
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@ -0,0 +1,26 @@
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create ad463x_data_capture
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adi_ip_files ad463x_data_capture [list \
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"ad463x_data_capture.v" \
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]
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adi_ip_properties_lite ad463x_data_capture
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# Remove all inferred interfaces
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ipx::remove_all_bus_interface [ipx::current_core]
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# Interface definitions
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adi_add_bus "m_axis" "master" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"m_axis_ready" "TREADY"} \
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{"m_axis_valid" "TVALID"} \
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{"m_axis_data" "TDATA"}]
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adi_add_bus_clock "clk" "m_axis"
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ipx::save_core [ipx::current_core]
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@ -0,0 +1,10 @@
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#!/bin/bash
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SOURCE="../ad463x_data_capture.v"
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SOURCE+=" ad463x_data_capture_tb.sv"
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TOP="ad463x_data_capture_tb"
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cd `dirname $0`
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source "../../common/tb/run_tb.sh"
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@ -0,0 +1,268 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad463x_data_capture_tb ();
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parameter VCD_FILE = {`__FILE__,"cd"};
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// set to one to increase verbosity
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localparam DEBUG = 1;
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localparam PASSED = 1;
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localparam FAILED = 0;
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localparam DDR_EN = 0;
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localparam NUM_OF_LANES = 1;
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localparam TRANSFER_CYCLE = 120;
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localparam TRANSFER_PERIOD = 40;
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reg clk = 1'b0;
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reg [NUM_OF_LANES-1:0] data_in = {NUM_OF_LANES{1'b0}};
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reg m_axis_ready = 1'b1;
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reg csn_clk = 1;
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wire csn;
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wire echo_sclk;
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wire m_axis_valid;
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wire [(NUM_OF_LANES *32)-1:0] m_axis_data;
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//---------------------------------------------------------------------------
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// test bench regs and wires
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//---------------------------------------------------------------------------
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reg echo_sclk_int = 0;
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integer csn_counter = 0;
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//---------------------------------------------------------------------------
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// VCD dump
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//---------------------------------------------------------------------------
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initial begin
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$dumpfile (VCD_FILE);
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$dumpvars;
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end
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//---------------------------------------------------------------------------
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// clock generation
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//---------------------------------------------------------------------------
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always #5 clk = ~clk;
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always #10 echo_sclk_int = ~echo_sclk_int;
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//---------------------------------------------------------------------------
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// chis select generation
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//---------------------------------------------------------------------------
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always @(negedge clk) begin
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if (csn_counter == TRANSFER_CYCLE-1)
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csn_counter = 0;
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else
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csn_counter++;
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end
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assign csn = (csn_counter < TRANSFER_CYCLE - TRANSFER_PERIOD) ? 1'b1 : 1'b0;
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assign echo_sclk = ~csn & echo_sclk_int;
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// CSN for DUT must be synchronous to clk
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always @(posedge clk) begin
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csn_clk <= csn;
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end
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//---------------------------------------------------------------------------
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// device BFM - MISO (SDO) generation
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//---------------------------------------------------------------------------
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reg csn_d = 0;
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always @(posedge clk) begin
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csn_d <= csn;
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end
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reg [19:0] data_serial[NUM_OF_LANES-1:0];
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// SDR
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initial begin
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while (1) begin
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@(posedge echo_sclk or negedge csn);
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if (csn_d) begin
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for (int i=0; i<NUM_OF_LANES; i=i+1)
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data_serial[i] <= $urandom();
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end else begin
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for (int i=0; i<NUM_OF_LANES; i=i+1) begin
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data_in[i] <= data_serial[i][19];
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data_serial[i] <= data_serial[i] << 1;
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end
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end
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end
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end
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//---------------------------------------------------------------------------
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// Monitors
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//---------------------------------------------------------------------------
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bit [31:0] mon_data_src[$];
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bit [31:0] mon_data_snk[$];
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// source - expected data
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initial begin
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while (1) begin
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@(negedge csn_clk);
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for (int i=0; i<NUM_OF_LANES; i++) begin
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mon_data_src.push_front(data_serial[i]);
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end
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end
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end
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// sink - received data
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initial begin
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while (1) begin
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@(posedge clk) #1;
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if (m_axis_valid) begin
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for (int i=0; i<NUM_OF_LANES; i++) begin
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mon_data_snk.push_front(m_axis_data[32*i+:32]);
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end
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end
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end
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end
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//---------------------------------------------------------------------------
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// Scoreboard
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//---------------------------------------------------------------------------
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event end_of_sim;
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bit tb_status = PASSED; // not guilty until proven
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initial begin
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@end_of_sim;
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$display("Scoreboard results...");
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check_xfer_queue("SCOREBOARD", mon_data_src, mon_data_snk);
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end
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//---------------------------------------------------------------------------
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// test bench
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//---------------------------------------------------------------------------
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initial begin
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csn_counter = 0;
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// time of the simulation
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#10000;
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@(posedge m_axis_valid) #20; // WARNING this can block the sim
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->end_of_sim;
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#0
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print_status(tb_status);
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$finish;
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end
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//--------------------------------------------------------------------------
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// Helper functions
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//--------------------------------------------------------------------------
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function print_queue(string queue_name, bit [31:0] queue[$]);
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begin
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$display("======================================");
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$display("Printing %s...", queue_name);
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for(int i=0; i<queue.size(); i++)
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$display("INFO %s[%d] = 0x%h", queue_name, i, queue[i]);
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$display("======================================");
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end
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endfunction
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function check_xfer_queue(string xfer_name, bit [31:0] exp[$], bit [31:0] rec[$]);
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begin
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if (exp.size() != rec.size()) begin
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$display("ERROR %s Source and sink number of transfers mismatch! SRC=%d - SNK=%d", xfer_name, exp.size(), rec.size());
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if (DEBUG) begin
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print_queue({"expected_", xfer_name}, exp);
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print_queue({"received_", xfer_name}, rec);
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end
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tb_status = FAILED;
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end else begin
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while(exp.size()) begin
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if(exp[$] != rec[$]) begin
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$display("ERROR %s transfer mismatch: rec 0x%h - exp 0x%h", xfer_name, rec[$], exp[$]);
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tb_status = FAILED;
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end
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exp.pop_back();
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rec.pop_back();
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end
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end
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end
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endfunction
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function print_status(bit tb_status);
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begin
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if (tb_status == PASSED) begin
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$display(" ##### ##### ###### ###### ");
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$display(" # # # # # # ");
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$display(" # # # # # # ");
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$display(" ##### ####### ##### ##### ");
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$display(" # # # # # ");
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$display(" # # # # # ");
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$display(" # # # ###### ###### ");
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end else begin
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$display(" ##### ##### ### # ");
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$display(" # # # # # ");
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$display(" # # # # # ");
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$display(" ##### ####### # # ");
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$display(" # # # # # ");
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$display(" # # # # # ");
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$display(" # # # ### ####### ");
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end
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end
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endfunction
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//---------------------------------------------------------------------------
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// DUT instance
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//---------------------------------------------------------------------------
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ad463x_data_capture #(
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.DDR_EN (DDR_EN),
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.NUM_OF_LANES (NUM_OF_LANES))
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i_dut (
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.clk (clk),
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.csn (csn_clk),
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.echo_sclk (echo_sclk),
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.data_in (data_in),
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.m_axis_data (m_axis_data),
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.m_axis_valid (m_axis_valid),
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.m_axis_ready (m_axis_ready)
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);
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endmodule
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