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ad463x_data_capture: Initial commit 

IP required to support echo and master clock mode
main
Istvan Csomortani 2021-01-18 15:11:57 +00:00 committed by sarpadi
parent 5ac64b021f
commit 6a526f4bb6
6 changed files with 453 additions and 0 deletions
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2
library/Makefile
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@ -13,6 +13,7 @@ all: lib
clean: clean:
$(MAKE) -C ad463x_data_capture clean
$(MAKE) -C axi_ad5766 clean $(MAKE) -C axi_ad5766 clean
$(MAKE) -C axi_ad6676 clean $(MAKE) -C axi_ad6676 clean
$(MAKE) -C axi_ad7616 clean $(MAKE) -C axi_ad7616 clean
@ -135,6 +136,7 @@ clean-all:clean
lib: lib:
$(MAKE) -C ad463x_data_capture
$(MAKE) -C axi_ad5766 $(MAKE) -C axi_ad5766
$(MAKE) -C axi_ad6676 $(MAKE) -C axi_ad6676
$(MAKE) -C axi_ad7616 $(MAKE) -C axi_ad7616

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library/ad463x_data_capture/Makefile Normal file
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@ -0,0 +1,13 @@
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := ad463x_data_capture
GENERIC_DEPS += ad463x_data_capture.v
XILINX_DEPS += ad463x_data_capture_ip.tcl
include ../scripts/library.mk

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library/ad463x_data_capture/ad463x_data_capture.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
// The AD4630-24 device requires this module to capture data in master and
// echo clock mode, because the data is clocked by the BUSY/SCLKOUT line,
// independent from the SPI interface
module ad463x_data_capture #(
parameter DDR_EN = 0,
parameter NUM_OF_LANES = 2,
parameter DATA_WIDTH = 32
) (
input clk, // core clock of the SPIE
input csn, // CSN (chip select)
input echo_sclk, // BUSY/SCLKOUT
input [NUM_OF_LANES-1:0] data_in, // serial data lines
output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines
output m_axis_valid, // data validation
input m_axis_ready // NOTE: back pressure is ignored
);
reg csn_d;
wire reset;
always @(posedge clk) begin
csn_d <= csn;
end
// negative edge resets the shift registers
assign reset = ~csn & csn_d;
// CSN positive edge validates the output data
// WARNING: there isn't any buffering for data, if the sink module is not
// ready, the data will be discarded
assign m_axis_valid = csn & ~csn_d & m_axis_ready;
genvar i, j;
generate
if (DDR_EN) // Double Data Rate mode
begin
for (i=0; i<NUM_OF_LANES; i=i+1) begin
reg [DATA_WIDTH-1:0] data_shift_p;
reg [DATA_WIDTH-1:0] data_shift_n;
// shift register for positive edge
always @(negedge echo_sclk or posedge reset) begin
if (reset) begin
data_shift_n <= 0;
end else begin
data_shift_n <= {data_shift_n, data_in[i]};
end
end
// shift register for positive edge
always @(posedge echo_sclk or posedge reset) begin
if (reset) begin
data_shift_p <= 0;
end else begin
data_shift_p <= {data_shift_p, data_in[i]};
end
end
// DDR output logic - only the first 16 bits are forwarded
for (j=0; j<DATA_WIDTH/2; j=j+1) begin
assign m_axis_data[DATA_WIDTH*i+(j*2)+:2] = {data_shift_p[j], data_shift_n[j]};
end
end /* for loop */
end else begin // Single Data Rate mode
for (i=0; i<NUM_OF_LANES; i=i+1) begin
reg [DATA_WIDTH-1:0] data_shift_n;
// shift register for positive edge
always @(negedge echo_sclk or posedge reset) begin
if (reset) begin
data_shift_n <= 0;
end else begin
data_shift_n <= {data_shift_n, data_in[i]};
end
end
// SDR output logic
assign m_axis_data[DATA_WIDTH*i+:DATA_WIDTH] = data_shift_n;
end /* for loop */
end
endgenerate
endmodule

26
library/ad463x_data_capture/ad463x_data_capture_ip.tcl Normal file
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source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create ad463x_data_capture
adi_ip_files ad463x_data_capture [list \
"ad463x_data_capture.v" \
]
adi_ip_properties_lite ad463x_data_capture
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]
# Interface definitions
adi_add_bus "m_axis" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list {"m_axis_ready" "TREADY"} \
{"m_axis_valid" "TVALID"} \
{"m_axis_data" "TDATA"}]
adi_add_bus_clock "clk" "m_axis"
ipx::save_core [ipx::current_core]

10
library/ad463x_data_capture/tb/ad463x_data_capture_tb Executable file
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#!/bin/bash
SOURCE="../ad463x_data_capture.v"
SOURCE+=" ad463x_data_capture_tb.sv"
TOP="ad463x_data_capture_tb"
cd `dirname $0`
source "../../common/tb/run_tb.sh"

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library/ad463x_data_capture/tb/ad463x_data_capture_tb.sv Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad463x_data_capture_tb ();
parameter VCD_FILE = {`__FILE__,"cd"};
// set to one to increase verbosity
localparam DEBUG = 1;
localparam PASSED = 1;
localparam FAILED = 0;
localparam DDR_EN = 0;
localparam NUM_OF_LANES = 1;
localparam TRANSFER_CYCLE = 120;
localparam TRANSFER_PERIOD = 40;
reg clk = 1'b0;
reg [NUM_OF_LANES-1:0] data_in = {NUM_OF_LANES{1'b0}};
reg m_axis_ready = 1'b1;
reg csn_clk = 1;
wire csn;
wire echo_sclk;
wire m_axis_valid;
wire [(NUM_OF_LANES *32)-1:0] m_axis_data;
//---------------------------------------------------------------------------
// test bench regs and wires
//---------------------------------------------------------------------------
reg echo_sclk_int = 0;
integer csn_counter = 0;
//---------------------------------------------------------------------------
// VCD dump
//---------------------------------------------------------------------------
initial begin
$dumpfile (VCD_FILE);
$dumpvars;
end
//---------------------------------------------------------------------------
// clock generation
//---------------------------------------------------------------------------
always #5 clk = ~clk;
always #10 echo_sclk_int = ~echo_sclk_int;
//---------------------------------------------------------------------------
// chis select generation
//---------------------------------------------------------------------------
always @(negedge clk) begin
if (csn_counter == TRANSFER_CYCLE-1)
csn_counter = 0;
else
csn_counter++;
end
assign csn = (csn_counter < TRANSFER_CYCLE - TRANSFER_PERIOD) ? 1'b1 : 1'b0;
assign echo_sclk = ~csn & echo_sclk_int;
// CSN for DUT must be synchronous to clk
always @(posedge clk) begin
csn_clk <= csn;
end
//---------------------------------------------------------------------------
// device BFM - MISO (SDO) generation
//---------------------------------------------------------------------------
reg csn_d = 0;
always @(posedge clk) begin
csn_d <= csn;
end
reg [19:0] data_serial[NUM_OF_LANES-1:0];
// SDR
initial begin
while (1) begin
@(posedge echo_sclk or negedge csn);
if (csn_d) begin
for (int i=0; i<NUM_OF_LANES; i=i+1)
data_serial[i] <= $urandom();
end else begin
for (int i=0; i<NUM_OF_LANES; i=i+1) begin
data_in[i] <= data_serial[i][19];
data_serial[i] <= data_serial[i] << 1;
end
end
end
end
//---------------------------------------------------------------------------
// Monitors
//---------------------------------------------------------------------------
bit [31:0] mon_data_src[$];
bit [31:0] mon_data_snk[$];
// source - expected data
initial begin
while (1) begin
@(negedge csn_clk);
for (int i=0; i<NUM_OF_LANES; i++) begin
mon_data_src.push_front(data_serial[i]);
end
end
end
// sink - received data
initial begin
while (1) begin
@(posedge clk) #1;
if (m_axis_valid) begin
for (int i=0; i<NUM_OF_LANES; i++) begin
mon_data_snk.push_front(m_axis_data[32*i+:32]);
end
end
end
end
//---------------------------------------------------------------------------
// Scoreboard
//---------------------------------------------------------------------------
event end_of_sim;
bit tb_status = PASSED; // not guilty until proven
initial begin
@end_of_sim;
$display("Scoreboard results...");
check_xfer_queue("SCOREBOARD", mon_data_src, mon_data_snk);
end
//---------------------------------------------------------------------------
// test bench
//---------------------------------------------------------------------------
initial begin
csn_counter = 0;
// time of the simulation
#10000;
@(posedge m_axis_valid) #20; // WARNING this can block the sim
->end_of_sim;
#0
print_status(tb_status);
$finish;
end
//--------------------------------------------------------------------------
// Helper functions
//--------------------------------------------------------------------------
function print_queue(string queue_name, bit [31:0] queue[$]);
begin
$display("======================================");
$display("Printing %s...", queue_name);
for(int i=0; i<queue.size(); i++)
$display("INFO %s[%d] = 0x%h", queue_name, i, queue[i]);
$display("======================================");
end
endfunction
function check_xfer_queue(string xfer_name, bit [31:0] exp[$], bit [31:0] rec[$]);
begin
if (exp.size() != rec.size()) begin
$display("ERROR %s Source and sink number of transfers mismatch! SRC=%d - SNK=%d", xfer_name, exp.size(), rec.size());
if (DEBUG) begin
print_queue({"expected_", xfer_name}, exp);
print_queue({"received_", xfer_name}, rec);
end
tb_status = FAILED;
end else begin
while(exp.size()) begin
if(exp[$] != rec[$]) begin
$display("ERROR %s transfer mismatch: rec 0x%h - exp 0x%h", xfer_name, rec[$], exp[$]);
tb_status = FAILED;
end
exp.pop_back();
rec.pop_back();
end
end
end
endfunction
function print_status(bit tb_status);
begin
if (tb_status == PASSED) begin
$display(" ##### ##### ###### ###### ");
$display(" # # # # # # ");
$display(" # # # # # # ");
$display(" ##### ####### ##### ##### ");
$display(" # # # # # ");
$display(" # # # # # ");
$display(" # # # ###### ###### ");
end else begin
$display(" ##### ##### ### # ");
$display(" # # # # # ");
$display(" # # # # # ");
$display(" ##### ####### # # ");
$display(" # # # # # ");
$display(" # # # # # ");
$display(" # # # ### ####### ");
end
end
endfunction
//---------------------------------------------------------------------------
// DUT instance
//---------------------------------------------------------------------------
ad463x_data_capture #(
.DDR_EN (DDR_EN),
.NUM_OF_LANES (NUM_OF_LANES))
i_dut (
.clk (clk),
.csn (csn_clk),
.echo_sclk (echo_sclk),
.data_in (data_in),
.m_axis_data (m_axis_data),
.m_axis_valid (m_axis_valid),
.m_axis_ready (m_axis_ready)
);
endmodule