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axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 

If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
main
Laszlo Nagy 2021-11-24 14:25:31 +02:00 committed by Laszlo Nagy
parent 77f3e5155b
commit 6a4b46ebb4
3 changed files with 154 additions and 121 deletions
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8
library/axi_adrv9001/axi_adrv9001.v
View File

@ -42,6 +42,8 @@ module axi_adrv9001 #(
parameter DDS_DISABLE = 0,
parameter INDEPENDENT_1R1T_SUPPORT = 1,
parameter COMMON_2R2T_SUPPORT = 1,
parameter DISABLE_RX2_SSI = 0,
parameter DISABLE_TX2_SSI = 0,
parameter RX_USE_BUFG = 0,
parameter TX_USE_BUFG = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
@ -274,7 +276,9 @@ module axi_adrv9001 #(
.RX_USE_BUFG (RX_USE_BUFG),
.TX_USE_BUFG (TX_USE_BUFG),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
.DISABLE_RX2_SSI (DISABLE_RX2_SSI),
.DISABLE_TX2_SSI (DISABLE_TX2_SSI),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_if(
//
@ -407,6 +411,8 @@ module axi_adrv9001 #(
.DDS_DISABLE (DDS_DISABLE),
.INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT),
.COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT),
.DISABLE_RX2_SSI (DISABLE_RX2_SSI),
.DISABLE_TX2_SSI (DISABLE_TX2_SSI),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),

10
library/axi_adrv9001/axi_adrv9001_core.v
View File

@ -45,6 +45,8 @@ module axi_ad9001_core #(
parameter DDS_DISABLE = 0,
parameter INDEPENDENT_1R1T_SUPPORT = 1,
parameter COMMON_2R2T_SUPPORT = 1,
parameter DISABLE_RX2_SSI = 0,
parameter DISABLE_TX2_SSI = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
@ -308,7 +310,7 @@ module axi_ad9001_core #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR(6'h00),
.CHANNEL_BASE_ADDR(6'h01),
.MODE_R1 (COMMON_2R2T_SUPPORT==0),
.MODE_R1 (COMMON_2R2T_SUPPORT == 0 || DISABLE_RX2_SSI == 1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -368,7 +370,7 @@ module axi_ad9001_core #(
axi_adrv9001_rx #(
.ID (ID),
.ENABLED (INDEPENDENT_1R1T_SUPPORT),
.ENABLED (INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI != 1),
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR(6'h04),
.CHANNEL_BASE_ADDR(6'h05),
@ -431,7 +433,7 @@ module axi_ad9001_core #(
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
.COMMON_BASE_ADDR ('h08),
.CHANNEL_BASE_ADDR ('h09),
.MODE_R1 (COMMON_2R2T_SUPPORT==0),
.MODE_R1 (COMMON_2R2T_SUPPORT == 0 || DISABLE_RX2_SSI == 1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -482,7 +484,7 @@ module axi_ad9001_core #(
axi_adrv9001_tx #(
.ID (ID),
.ENABLED (INDEPENDENT_1R1T_SUPPORT),
.ENABLED (INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI != 1),
.CMOS_LVDS_N (CMOS_LVDS_N),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
.COMMON_BASE_ADDR ('h10),

257
library/axi_adrv9001/axi_adrv9001_if.v
View File

@ -42,6 +42,8 @@ module axi_adrv9001_if #(
parameter DRP_WIDTH = 5,
parameter RX_USE_BUFG = 0,
parameter TX_USE_BUFG = 0,
parameter DISABLE_RX2_SSI = 0,
parameter DISABLE_TX2_SSI = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter USE_RX_CLK_FOR_TX = 0
) (
@ -267,69 +269,79 @@ module axi_adrv9001_if #(
.rx_symb_8_16b (rx1_symb_8_16b)
);
adrv9001_rx
#(.CMOS_LVDS_N (CMOS_LVDS_N),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.NUM_LANES (NUM_LANES),
.DRP_WIDTH (DRP_WIDTH),
.IODELAY_CTRL (0),
.USE_BUFG (RX_USE_BUFG),
.IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"})
) i_rx_2_phy (
.rx_dclk_in_n_NC (rx2_dclk_in_n_NC),
.rx_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in),
.rx_idata_in_n_idata0 (rx2_idata_in_n_idata0),
.rx_idata_in_p_idata1 (rx2_idata_in_p_idata1),
.rx_qdata_in_n_qdata2 (rx2_qdata_in_n_qdata2),
.rx_qdata_in_p_qdata3 (rx2_qdata_in_p_qdata3),
.rx_strobe_in_n_NC (rx2_strobe_in_n_NC),
.rx_strobe_in_p_strobe_in (rx2_strobe_in_p_strobe_in),
generate if (DISABLE_RX2_SSI == 0) begin
adrv9001_rx
#(.CMOS_LVDS_N (CMOS_LVDS_N),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.NUM_LANES (NUM_LANES),
.DRP_WIDTH (DRP_WIDTH),
.IODELAY_CTRL (0),
.USE_BUFG (RX_USE_BUFG),
.IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"})
) i_rx_2_phy (
.rx_dclk_in_n_NC (rx2_dclk_in_n_NC),
.rx_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in),
.rx_idata_in_n_idata0 (rx2_idata_in_n_idata0),
.rx_idata_in_p_idata1 (rx2_idata_in_p_idata1),
.rx_qdata_in_n_qdata2 (rx2_qdata_in_n_qdata2),
.rx_qdata_in_p_qdata3 (rx2_qdata_in_p_qdata3),
.rx_strobe_in_n_NC (rx2_strobe_in_n_NC),
.rx_strobe_in_p_strobe_in (rx2_strobe_in_p_strobe_in),
.adc_rst (rx2_rst),
.adc_clk (adc_2_clk),
.adc_clk_div (adc_2_clk_div),
.adc_data_0 (adc_2_data_0),
.adc_data_1 (adc_2_data_1),
.adc_data_2 (adc_2_data_2),
.adc_data_3 (adc_2_data_3),
.adc_data_strobe (adc_2_data_strobe),
.adc_valid (adc_2_valid),
.adc_rst (rx2_rst),
.adc_clk (adc_2_clk),
.adc_clk_div (adc_2_clk_div),
.adc_data_0 (adc_2_data_0),
.adc_data_1 (adc_2_data_1),
.adc_data_2 (adc_2_data_2),
.adc_data_3 (adc_2_data_3),
.adc_data_strobe (adc_2_data_strobe),
.adc_valid (adc_2_valid),
.up_clk (up_clk),
.up_adc_dld (up_rx2_dld),
.up_adc_dwdata (up_rx2_dwdata),
.up_adc_drdata (up_rx2_drdata),
.delay_clk (delay_clk),
.delay_rst (delay_rx2_rst),
.delay_locked (delay_rx2_locked),
.up_clk (up_clk),
.up_adc_dld (up_rx2_dld),
.up_adc_dwdata (up_rx2_dwdata),
.up_adc_drdata (up_rx2_drdata),
.delay_clk (delay_clk),
.delay_rst (delay_rx2_rst),
.delay_locked (delay_rx2_locked),
.mssi_sync (1'b0),
.ssi_sync_out (),
.ssi_sync_in (rx_ssi_sync_out),
.ssi_rst (adc_2_ssi_rst)
);
.mssi_sync (1'b0),
.ssi_sync_out (),
.ssi_sync_in (rx_ssi_sync_out),
.ssi_rst (adc_2_ssi_rst)
);
adrv9001_rx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N)
) i_rx_2_link (
.adc_rst (rx2_rst),
.adc_clk_div (adc_2_clk_div),
.adc_data_0 (adc_2_data_0),
.adc_data_1 (adc_2_data_1),
.adc_data_2 (adc_2_data_2),
.adc_data_3 (adc_2_data_3),
.adc_data_strobe (adc_2_data_strobe),
.adc_valid (adc_2_valid),
// ADC interface
.rx_clk (rx2_clk),
.rx_data_valid (rx2_data_valid),
.rx_data_i (rx2_data_i),
.rx_data_q (rx2_data_q),
.rx_single_lane (rx2_single_lane),
.rx_sdr_ddr_n (rx2_sdr_ddr_n),
.rx_symb_op (rx2_symb_op),
.rx_symb_8_16b (rx2_symb_8_16b)
);
adrv9001_rx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N)
) i_rx_2_link (
.adc_rst (rx2_rst),
.adc_clk_div (adc_2_clk_div),
.adc_data_0 (adc_2_data_0),
.adc_data_1 (adc_2_data_1),
.adc_data_2 (adc_2_data_2),
.adc_data_3 (adc_2_data_3),
.adc_data_strobe (adc_2_data_strobe),
.adc_valid (adc_2_valid),
// ADC interface
.rx_clk (rx2_clk),
.rx_data_valid (rx2_data_valid),
.rx_data_i (rx2_data_i),
.rx_data_q (rx2_data_q),
.rx_single_lane (rx2_single_lane),
.rx_sdr_ddr_n (rx2_sdr_ddr_n),
.rx_symb_op (rx2_symb_op),
.rx_symb_8_16b (rx2_symb_8_16b)
);
end else begin
assign delay_rx2_locked = 1'b1;
assign up_rx2_drdata = 'h0;
assign rx2_clk = 1'b0;
assign rx2_data_valid = 1'b0;
assign rx2_data_i = 16'b0;
assign rx2_data_q = 16'b0;
end
endgenerate
adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
@ -399,71 +411,84 @@ module axi_adrv9001_if #(
.tx_symb_8_16b (tx1_symb_8_16b)
);
adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.NUM_LANES (TX_NUM_LANES),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.USE_BUFG (TX_USE_BUFG),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_tx_2_phy (
generate if (DISABLE_TX2_SSI == 0) begin
adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.NUM_LANES (TX_NUM_LANES),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.USE_BUFG (TX_USE_BUFG),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_tx_2_phy (
.ref_clk (ref_clk),
.up_clk (up_clk),
.ref_clk (ref_clk),
.up_clk (up_clk),
.tx_output_enable(tx_output_enable),
.tx_output_enable(tx_output_enable),
.tx_dclk_out_n_NC (tx2_dclk_out_n_NC),
.tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
.tx_dclk_in_n_NC (tx2_dclk_in_n_NC),
.tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
.tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
.tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
.tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
.tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
.tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
.tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
.tx_dclk_out_n_NC (tx2_dclk_out_n_NC),
.tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out),
.tx_dclk_in_n_NC (tx2_dclk_in_n_NC),
.tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in),
.tx_idata_out_n_idata0 (tx2_idata_out_n_idata0),
.tx_idata_out_p_idata1 (tx2_idata_out_p_idata1),
.tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2),
.tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3),
.tx_strobe_out_n_NC (tx2_strobe_out_n_NC),
.tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out),
.rx_clk_div (adc_2_clk_div),
.rx_clk (adc_2_clk),
.rx_ssi_rst (adc_2_ssi_rst),
.rx_clk_div (adc_2_clk_div),
.rx_clk (adc_2_clk),
.rx_ssi_rst (adc_2_ssi_rst),
.dac_rst (tx2_rst),
.dac_clk_div (dac_2_clk_div),
.dac_rst (tx2_rst),
.dac_clk_div (dac_2_clk_div),
.dac_data_0 (dac_2_data_0),
.dac_data_1 (dac_2_data_1),
.dac_data_2 (dac_2_data_2),
.dac_data_3 (dac_2_data_3),
.dac_data_strb (dac_2_data_strobe),
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
.dac_data_0 (dac_2_data_0),
.dac_data_1 (dac_2_data_1),
.dac_data_2 (dac_2_data_2),
.dac_data_3 (dac_2_data_3),
.dac_data_strb (dac_2_data_strobe),
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
.mssi_sync (mssi_sync)
);
.mssi_sync (mssi_sync)
);
adrv9001_tx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.CLK_DIV_IS_FAST_CLK (FPGA_TECHNOLOGY >= 100)
) i_tx_2_link (
.dac_clk_div (dac_2_clk_div),
.dac_data_0 (dac_2_data_0),
.dac_data_1 (dac_2_data_1),
.dac_data_2 (dac_2_data_2),
.dac_data_3 (dac_2_data_3),
.dac_data_strobe (dac_2_data_strobe),
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
// DAC interface
.tx_clk (tx2_clk),
.tx_rst (tx2_rst),
.tx_data_valid (tx2_data_valid),
.tx_data_i (tx2_data_i),
.tx_data_q (tx2_data_q),
.tx_sdr_ddr_n (tx2_sdr_ddr_n),
.tx_single_lane (tx2_single_lane),
.tx_symb_op (tx2_symb_op),
.tx_symb_8_16b (tx2_symb_8_16b)
);
adrv9001_tx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.CLK_DIV_IS_FAST_CLK (FPGA_TECHNOLOGY >= 100)
) i_tx_2_link (
.dac_clk_div (dac_2_clk_div),
.dac_data_0 (dac_2_data_0),
.dac_data_1 (dac_2_data_1),
.dac_data_2 (dac_2_data_2),
.dac_data_3 (dac_2_data_3),
.dac_data_strobe (dac_2_data_strobe),
.dac_data_clk (dac_2_data_clk),
.dac_data_valid (dac_2_data_valid),
// DAC interface
.tx_clk (tx2_clk),
.tx_rst (tx2_rst),
.tx_data_valid (tx2_data_valid),
.tx_data_i (tx2_data_i),
.tx_data_q (tx2_data_q),
.tx_sdr_ddr_n (tx2_sdr_ddr_n),
.tx_single_lane (tx2_single_lane),
.tx_symb_op (tx2_symb_op),
.tx_symb_8_16b (tx2_symb_8_16b)
);
end else begin
assign tx2_clk = 1'b0;
assign tx2_dclk_out_n_NC = 1'b0;
assign tx2_dclk_out_p_dclk_out = 1'b0;
assign tx2_idata_out_n_idata0 = 1'b0;
assign tx2_idata_out_p_idata1 = 1'b0;
assign tx2_qdata_out_n_qdata2 = 1'b0;
assign tx2_qdata_out_p_qdata3 = 1'b0;
assign tx2_strobe_out_n_NC = 1'b0;
assign tx2_strobe_out_p_strobe_out = 1'b0;
end
endgenerate
endmodule