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axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 

If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
main
Laszlo Nagy 2021-11-24 14:25:31 +02:00 committed by Laszlo Nagy
parent 77f3e5155b
commit 6a4b46ebb4
3 changed files with 154 additions and 121 deletions
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6
library/axi_adrv9001/axi_adrv9001.v
View File

@ -42,6 +42,8 @@ module axi_adrv9001 #(
parameter DDS_DISABLE = 0,
parameter INDEPENDENT_1R1T_SUPPORT = 1,
parameter COMMON_2R2T_SUPPORT = 1,
parameter DISABLE_RX2_SSI = 0,
parameter DISABLE_TX2_SSI = 0,
parameter RX_USE_BUFG = 0,
parameter TX_USE_BUFG = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
@ -274,6 +276,8 @@ module axi_adrv9001 #(
.RX_USE_BUFG (RX_USE_BUFG),
.TX_USE_BUFG (TX_USE_BUFG),
.IO_DELAY_GROUP (IO_DELAY_GROUP),
.DISABLE_RX2_SSI (DISABLE_RX2_SSI),
.DISABLE_TX2_SSI (DISABLE_TX2_SSI),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX)
) i_if(
@ -407,6 +411,8 @@ module axi_adrv9001 #(
.DDS_DISABLE (DDS_DISABLE),
.INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT),
.COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT),
.DISABLE_RX2_SSI (DISABLE_RX2_SSI),
.DISABLE_TX2_SSI (DISABLE_TX2_SSI),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),

10
library/axi_adrv9001/axi_adrv9001_core.v
View File

@ -45,6 +45,8 @@ module axi_ad9001_core #(
parameter DDS_DISABLE = 0,
parameter INDEPENDENT_1R1T_SUPPORT = 1,
parameter COMMON_2R2T_SUPPORT = 1,
parameter DISABLE_RX2_SSI = 0,
parameter DISABLE_TX2_SSI = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
@ -308,7 +310,7 @@ module axi_ad9001_core #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR(6'h00),
.CHANNEL_BASE_ADDR(6'h01),
.MODE_R1 (COMMON_2R2T_SUPPORT==0),
.MODE_R1 (COMMON_2R2T_SUPPORT == 0 || DISABLE_RX2_SSI == 1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -368,7 +370,7 @@ module axi_ad9001_core #(
axi_adrv9001_rx #(
.ID (ID),
.ENABLED (INDEPENDENT_1R1T_SUPPORT),
.ENABLED (INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI != 1),
.CMOS_LVDS_N (CMOS_LVDS_N),
.COMMON_BASE_ADDR(6'h04),
.CHANNEL_BASE_ADDR(6'h05),
@ -431,7 +433,7 @@ module axi_ad9001_core #(
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
.COMMON_BASE_ADDR ('h08),
.CHANNEL_BASE_ADDR ('h09),
.MODE_R1 (COMMON_2R2T_SUPPORT==0),
.MODE_R1 (COMMON_2R2T_SUPPORT == 0 || DISABLE_RX2_SSI == 1),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -482,7 +484,7 @@ module axi_ad9001_core #(
axi_adrv9001_tx #(
.ID (ID),
.ENABLED (INDEPENDENT_1R1T_SUPPORT),
.ENABLED (INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI != 1),
.CMOS_LVDS_N (CMOS_LVDS_N),
.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
.COMMON_BASE_ADDR ('h10),

25
library/axi_adrv9001/axi_adrv9001_if.v
View File

@ -42,6 +42,8 @@ module axi_adrv9001_if #(
parameter DRP_WIDTH = 5,
parameter RX_USE_BUFG = 0,
parameter TX_USE_BUFG = 0,
parameter DISABLE_RX2_SSI = 0,
parameter DISABLE_TX2_SSI = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter USE_RX_CLK_FOR_TX = 0
) (
@ -267,6 +269,7 @@ module axi_adrv9001_if #(
.rx_symb_8_16b (rx1_symb_8_16b)
);
generate if (DISABLE_RX2_SSI == 0) begin
adrv9001_rx
#(.CMOS_LVDS_N (CMOS_LVDS_N),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
@ -330,6 +333,15 @@ module axi_adrv9001_if #(
.rx_symb_op (rx2_symb_op),
.rx_symb_8_16b (rx2_symb_8_16b)
);
end else begin
assign delay_rx2_locked = 1'b1;
assign up_rx2_drdata = 'h0;
assign rx2_clk = 1'b0;
assign rx2_data_valid = 1'b0;
assign rx2_data_i = 16'b0;
assign rx2_data_q = 16'b0;
end
endgenerate
adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
@ -399,6 +411,7 @@ module axi_adrv9001_if #(
.tx_symb_8_16b (tx1_symb_8_16b)
);
generate if (DISABLE_TX2_SSI == 0) begin
adrv9001_tx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.NUM_LANES (TX_NUM_LANES),
@ -464,6 +477,18 @@ module axi_adrv9001_if #(
.tx_symb_op (tx2_symb_op),
.tx_symb_8_16b (tx2_symb_8_16b)
);
end else begin
assign tx2_clk = 1'b0;
assign tx2_dclk_out_n_NC = 1'b0;
assign tx2_dclk_out_p_dclk_out = 1'b0;
assign tx2_idata_out_n_idata0 = 1'b0;
assign tx2_idata_out_p_idata1 = 1'b0;
assign tx2_qdata_out_n_qdata2 = 1'b0;
assign tx2_qdata_out_p_qdata3 = 1'b0;
assign tx2_strobe_out_n_NC = 1'b0;
assign tx2_strobe_out_p_strobe_out = 1'b0;
end
endgenerate
endmodule