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util_mii_to_rmii: Fix 100 Mbps configuration functionality

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alin724 2022-03-18 13:51:48 +02:00 committed by Alin-Tudor Sferle
parent 4499ddaae7
commit 6a252ec067
2 changed files with 6 additions and 12 deletions
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11
library/util_mii_to_rmii/mac_phy_link.v
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@ -62,7 +62,6 @@ module mac_phy_link #(
reg rising_tx_clk_r0 = 1'b0;
reg rising_tx_clk_r1 = 1'b0;
reg [4:0] reg_count = 5'b0;
reg tx_dibit_d = 1'b0;
localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1;
@ -129,15 +128,7 @@ module mac_phy_link #(
end
end
always @(posedge ref_clk) begin
if (!reset_n) begin
tx_dibit_d <= 1'b0;
end else begin
tx_dibit_d <= tx_dibit;
end
end
assign dibit_sample = RATE_10_100 ? (reg_count_w == 5'b01001 ? 1'b1 : 1'b0) : rising_tx_clk_r1;
assign dibit_sample = RATE_10_100 ? ((reg_count_w == 5'b01001) ? 1'b1 : 1'b0) : rising_tx_clk_r1;
assign num_w = num_r + 1;
assign mii_tx_clk = mii_tx_clk_10_100_r;
assign reg_count_w = reg_count;

7
library/util_mii_to_rmii/phy_mac_link.v
View File

@ -54,7 +54,6 @@ module phy_mac_link #(
wire data_valid_w;
wire dibit_sample;
wire eopack_w;
wire [9:0] mii_rx_dv_10mbps_w;
wire [3:0] num_w;
wire [3:0] reg_count_w;
wire sopack_w;
@ -243,7 +242,11 @@ module phy_mac_link #(
clk_phase_r <= mii_rx_clk;
nibble_valid <= 1'b0;
end else begin
if (dibit_sample) begin
if (RATE_10_100) begin
if (dibit_sample) begin
nibble_valid <= ~nibble_valid;
end
end else begin
nibble_valid <= ~nibble_valid;
end
end