From 6a252ec067a5a6b94fa3291499f4001ffde6fa6a Mon Sep 17 00:00:00 2001 From: alin724 Date: Fri, 18 Mar 2022 13:51:48 +0200 Subject: [PATCH] util_mii_to_rmii: Fix 100 Mbps configuration functionality --- library/util_mii_to_rmii/mac_phy_link.v | 11 +---------- library/util_mii_to_rmii/phy_mac_link.v | 7 +++++-- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/library/util_mii_to_rmii/mac_phy_link.v b/library/util_mii_to_rmii/mac_phy_link.v index 7d7c680f3..ca18c379e 100644 --- a/library/util_mii_to_rmii/mac_phy_link.v +++ b/library/util_mii_to_rmii/mac_phy_link.v @@ -62,7 +62,6 @@ module mac_phy_link #( reg rising_tx_clk_r0 = 1'b0; reg rising_tx_clk_r1 = 1'b0; reg [4:0] reg_count = 5'b0; - reg tx_dibit_d = 1'b0; localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1; @@ -129,15 +128,7 @@ module mac_phy_link #( end end - always @(posedge ref_clk) begin - if (!reset_n) begin - tx_dibit_d <= 1'b0; - end else begin - tx_dibit_d <= tx_dibit; - end - end - - assign dibit_sample = RATE_10_100 ? (reg_count_w == 5'b01001 ? 1'b1 : 1'b0) : rising_tx_clk_r1; + assign dibit_sample = RATE_10_100 ? ((reg_count_w == 5'b01001) ? 1'b1 : 1'b0) : rising_tx_clk_r1; assign num_w = num_r + 1; assign mii_tx_clk = mii_tx_clk_10_100_r; assign reg_count_w = reg_count; diff --git a/library/util_mii_to_rmii/phy_mac_link.v b/library/util_mii_to_rmii/phy_mac_link.v index 0f424c053..5359beda8 100644 --- a/library/util_mii_to_rmii/phy_mac_link.v +++ b/library/util_mii_to_rmii/phy_mac_link.v @@ -54,7 +54,6 @@ module phy_mac_link #( wire data_valid_w; wire dibit_sample; wire eopack_w; - wire [9:0] mii_rx_dv_10mbps_w; wire [3:0] num_w; wire [3:0] reg_count_w; wire sopack_w; @@ -243,7 +242,11 @@ module phy_mac_link #( clk_phase_r <= mii_rx_clk; nibble_valid <= 1'b0; end else begin - if (dibit_sample) begin + if (RATE_10_100) begin + if (dibit_sample) begin + nibble_valid <= ~nibble_valid; + end + end else begin nibble_valid <= ~nibble_valid; end end