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fmcomms2/zc706pr- bypass pr as default

main
Rejeesh Kutty 2016-11-21 09:45:10 -05:00
parent 4739d05269
commit 69ee410d3d
4 changed files with 188 additions and 241 deletions
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315
projects/fmcomms2/common/prcfg_bd.tcl
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@ -3,238 +3,119 @@
create_bd_port -dir O clk create_bd_port -dir O clk
create_bd_port -dir I dma_dac_i0_enable
create_bd_port -dir O dma_dac_i0_data
create_bd_port -dir I dma_dac_i0_valid
create_bd_port -dir I dma_dac_q0_enable
create_bd_port -dir O dma_dac_q0_data
create_bd_port -dir I dma_dac_q0_valid
create_bd_port -dir I dma_dac_i1_enable
create_bd_port -dir O dma_dac_i1_data
create_bd_port -dir I dma_dac_i1_valid
create_bd_port -dir I dma_dac_q1_enable
create_bd_port -dir O dma_dac_q1_data
create_bd_port -dir I dma_dac_q1_valid
create_bd_port -dir O core_dac_i0_enable create_bd_port -dir O core_dac_i0_enable
create_bd_port -dir I core_dac_i0_data
create_bd_port -dir O core_dac_i0_valid
create_bd_port -dir O core_dac_q0_enable create_bd_port -dir O core_dac_q0_enable
create_bd_port -dir I core_dac_q0_data
create_bd_port -dir O core_dac_q0_valid
create_bd_port -dir O core_dac_i1_enable create_bd_port -dir O core_dac_i1_enable
create_bd_port -dir I core_dac_i1_data
create_bd_port -dir O core_dac_i1_valid
create_bd_port -dir O core_dac_q1_enable create_bd_port -dir O core_dac_q1_enable
create_bd_port -dir I core_dac_q1_data create_bd_port -dir O core_dac_i0_valid
create_bd_port -dir O core_dac_q0_valid
create_bd_port -dir O core_dac_i1_valid
create_bd_port -dir O core_dac_q1_valid create_bd_port -dir O core_dac_q1_valid
create_bd_port -dir I dma_adc_i0_enable create_bd_port -dir I -from 15 -to 0 core_dac_i0_data
create_bd_port -dir I dma_adc_i0_data create_bd_port -dir I -from 15 -to 0 core_dac_q0_data
create_bd_port -dir I dma_adc_i0_valid create_bd_port -dir I -from 15 -to 0 core_dac_i1_data
create_bd_port -dir I dma_adc_q0_enable create_bd_port -dir I -from 15 -to 0 core_dac_q1_data
create_bd_port -dir I dma_adc_q0_data
create_bd_port -dir I dma_adc_q0_valid create_bd_port -dir I dma_dac_i0_enable
create_bd_port -dir I dma_adc_i1_enable create_bd_port -dir I dma_dac_q0_enable
create_bd_port -dir I dma_adc_i1_data create_bd_port -dir I dma_dac_i1_enable
create_bd_port -dir I dma_adc_i1_valid create_bd_port -dir I dma_dac_q1_enable
create_bd_port -dir I dma_adc_q1_enable create_bd_port -dir I dma_dac_i0_valid
create_bd_port -dir I dma_adc_q1_data create_bd_port -dir I dma_dac_q0_valid
create_bd_port -dir I dma_adc_q1_valid create_bd_port -dir I dma_dac_i1_valid
create_bd_port -dir I dma_dac_q1_valid
create_bd_port -dir O -from 15 -to 0 dma_dac_i0_data
create_bd_port -dir O -from 15 -to 0 dma_dac_q0_data
create_bd_port -dir O -from 15 -to 0 dma_dac_i1_data
create_bd_port -dir O -from 15 -to 0 dma_dac_q1_data
create_bd_port -dir O core_adc_i0_enable create_bd_port -dir O core_adc_i0_enable
create_bd_port -dir O core_adc_i0_data
create_bd_port -dir O core_adc_i0_valid
create_bd_port -dir O core_adc_q0_enable create_bd_port -dir O core_adc_q0_enable
create_bd_port -dir O core_adc_q0_data
create_bd_port -dir O core_adc_q0_valid
create_bd_port -dir O core_adc_i1_enable create_bd_port -dir O core_adc_i1_enable
create_bd_port -dir O core_adc_i1_data
create_bd_port -dir O core_adc_i1_valid
create_bd_port -dir O core_adc_q1_enable create_bd_port -dir O core_adc_q1_enable
create_bd_port -dir O core_adc_q1_data create_bd_port -dir O core_adc_i0_valid
create_bd_port -dir O core_adc_q0_valid
create_bd_port -dir O core_adc_i1_valid
create_bd_port -dir O core_adc_q1_valid create_bd_port -dir O core_adc_q1_valid
create_bd_port -dir O -from 15 -to 0 core_adc_i0_data
create_bd_port -dir O -from 15 -to 0 core_adc_q0_data
create_bd_port -dir O -from 15 -to 0 core_adc_i1_data
create_bd_port -dir O -from 15 -to 0 core_adc_q1_data
create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in create_bd_port -dir I dma_adc_i0_enable
create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in create_bd_port -dir I dma_adc_q0_enable
create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out create_bd_port -dir I dma_adc_i1_enable
create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out create_bd_port -dir I dma_adc_q1_enable
create_bd_port -dir I dma_adc_i0_valid
create_bd_port -dir I dma_adc_q0_valid
create_bd_port -dir I dma_adc_i1_valid
create_bd_port -dir I dma_adc_q1_valid
create_bd_port -dir I -from 15 -to 0 dma_adc_i0_data
create_bd_port -dir I -from 15 -to 0 dma_adc_q0_data
create_bd_port -dir I -from 15 -to 0 dma_adc_i1_data
create_bd_port -dir I -from 15 -to 0 dma_adc_q1_data
# re-wiring create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in
create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in
create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out
create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_0]] [get_bd_pins util_ad9361_dac_upack/dac_enable_0] # re-wiring, split between ad9361 core & upack/cpack modules
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_0]] [get_bd_pins util_ad9361_dac_upack/dac_valid_0]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_0]] [get_bd_pins util_ad9361_dac_upack/dac_data_0]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_1]] [get_bd_pins util_ad9361_dac_upack/dac_enable_1]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_1]] [get_bd_pins util_ad9361_dac_upack/dac_valid_1]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_1]] [get_bd_pins util_ad9361_dac_upack/dac_data_1]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_2]] [get_bd_pins util_ad9361_dac_upack/dac_enable_2]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_2]] [get_bd_pins util_ad9361_dac_upack/dac_valid_2]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_2]] [get_bd_pins util_ad9361_dac_upack/dac_data_2]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_3]] [get_bd_pins util_ad9361_dac_upack/dac_enable_3]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_3]] [get_bd_pins util_ad9361_dac_upack/dac_valid_3]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_3]] [get_bd_pins util_ad9361_dac_upack/dac_data_3]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_0]] [get_bd_pins util_ad9361_adc_pack/adc_enable_0] ad_connect axi_ad9361_clk clk
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_0]] [get_bd_pins util_ad9361_adc_pack/adc_valid_0]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_0]] [get_bd_pins util_ad9361_adc_pack/adc_data_0]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_1]] [get_bd_pins util_ad9361_adc_pack/adc_enable_1]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_1]] [get_bd_pins util_ad9361_adc_pack/adc_valid_1]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_1]] [get_bd_pins util_ad9361_adc_pack/adc_data_1]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_2]] [get_bd_pins util_ad9361_adc_pack/adc_enable_2]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_2]] [get_bd_pins util_ad9361_adc_pack/adc_valid_2]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_2]] [get_bd_pins util_ad9361_adc_pack/adc_data_2]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_3]] [get_bd_pins util_ad9361_adc_pack/adc_enable_3]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_3]] [get_bd_pins util_ad9361_adc_pack/adc_valid_3]
disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_3]] [get_bd_pins util_ad9361_adc_pack/adc_data_3]
ad_connect clk axi_ad9361/clk ad_reconct util_ad9361_dac_upack/dac_enable_0 dma_dac_i0_enable
ad_reconct util_ad9361_dac_upack/dac_enable_1 dma_dac_q0_enable
ad_reconct util_ad9361_dac_upack/dac_enable_2 dma_dac_i1_enable
ad_reconct util_ad9361_dac_upack/dac_enable_3 dma_dac_q1_enable
ad_reconct util_ad9361_dac_upack/dac_valid_0 dma_dac_i0_valid
ad_reconct util_ad9361_dac_upack/dac_valid_1 dma_dac_q0_valid
ad_reconct util_ad9361_dac_upack/dac_valid_2 dma_dac_i1_valid
ad_reconct util_ad9361_dac_upack/dac_valid_3 dma_dac_q1_valid
ad_reconct util_ad9361_dac_upack/dac_data_0 dma_dac_i0_data
ad_reconct util_ad9361_dac_upack/dac_data_1 dma_dac_q0_data
ad_reconct util_ad9361_dac_upack/dac_data_2 dma_dac_i1_data
ad_reconct util_ad9361_dac_upack/dac_data_3 dma_dac_q1_data
ad_reconct axi_ad9361/dac_enable_i0 core_dac_i0_enable
ad_reconct axi_ad9361/dac_enable_q0 core_dac_q0_enable
ad_reconct axi_ad9361/dac_enable_i1 core_dac_i1_enable
ad_reconct axi_ad9361/dac_enable_q1 core_dac_q1_enable
ad_reconct axi_ad9361/dac_valid_i0 core_dac_i0_valid
ad_reconct axi_ad9361/dac_valid_q0 core_dac_q0_valid
ad_reconct axi_ad9361/dac_valid_i1 core_dac_i1_valid
ad_reconct axi_ad9361/dac_valid_q1 core_dac_q1_valid
ad_reconct axi_ad9361/dac_data_i0 core_dac_i0_data
ad_reconct axi_ad9361/dac_data_q0 core_dac_q0_data
ad_reconct axi_ad9361/dac_data_i1 core_dac_i1_data
ad_reconct axi_ad9361/dac_data_q1 core_dac_q1_data
# tx data path ad_reconct util_ad9361_adc_fifo/din_enable_0 dma_adc_i0_enable
ad_connect dma_dac_i0_enable util_ad9361_dac_upack/dac_enable_0 ad_reconct util_ad9361_adc_fifo/din_enable_1 dma_adc_q0_enable
ad_connect dma_dac_i0_data util_ad9361_dac_upack/dac_data_0 ad_reconct util_ad9361_adc_fifo/din_enable_2 dma_adc_i1_enable
ad_connect dma_dac_i0_valid util_ad9361_dac_upack/dac_valid_0 ad_reconct util_ad9361_adc_fifo/din_enable_3 dma_adc_q1_enable
ad_connect dma_dac_q0_enable util_ad9361_dac_upack/dac_enable_1 ad_reconct util_ad9361_adc_fifo/din_valid_0 dma_adc_i0_valid
ad_connect dma_dac_q0_data util_ad9361_dac_upack/dac_data_1 ad_reconct util_ad9361_adc_fifo/din_valid_1 dma_adc_q0_valid
ad_connect dma_dac_q0_valid util_ad9361_dac_upack/dac_valid_1 ad_reconct util_ad9361_adc_fifo/din_valid_2 dma_adc_i1_valid
ad_connect dma_dac_i1_enable util_ad9361_dac_upack/dac_enable_2 ad_reconct util_ad9361_adc_fifo/din_valid_3 dma_adc_q1_valid
ad_connect dma_dac_i1_data util_ad9361_dac_upack/dac_data_2 ad_reconct util_ad9361_adc_fifo/din_data_0 dma_adc_i0_data
ad_connect dma_dac_i1_valid util_ad9361_dac_upack/dac_valid_2 ad_reconct util_ad9361_adc_fifo/din_data_1 dma_adc_q0_data
ad_connect dma_dac_q1_enable util_ad9361_dac_upack/dac_enable_3 ad_reconct util_ad9361_adc_fifo/din_data_2 dma_adc_i1_data
ad_connect dma_dac_q1_data util_ad9361_dac_upack/dac_data_3 ad_reconct util_ad9361_adc_fifo/din_data_3 dma_adc_q1_data
ad_connect dma_dac_q1_valid util_ad9361_dac_upack/dac_valid_3 ad_reconct axi_ad9361/adc_enable_i0 core_adc_i0_enable
ad_reconct axi_ad9361/adc_enable_q0 core_adc_q0_enable
ad_reconct axi_ad9361/adc_enable_i1 core_adc_i1_enable
ad_reconct axi_ad9361/adc_enable_q1 core_adc_q1_enable
ad_reconct axi_ad9361/adc_valid_i0 core_adc_i0_valid
ad_reconct axi_ad9361/adc_valid_q0 core_adc_q0_valid
ad_reconct axi_ad9361/adc_valid_i1 core_adc_i1_valid
ad_reconct axi_ad9361/adc_valid_q1 core_adc_q1_valid
ad_reconct axi_ad9361/adc_data_i0 core_adc_i0_data
ad_reconct axi_ad9361/adc_data_q0 core_adc_q0_data
ad_reconct axi_ad9361/adc_data_i1 core_adc_i1_data
ad_reconct axi_ad9361/adc_data_q1 core_adc_q1_data
ad_connect core_dac_i0_enable axi_ad9361/dac_enable_i0 ad_reconct axi_ad9361/up_dac_gpio_in up_dac_gpio_in
ad_connect core_dac_i0_data axi_ad9361/dac_data_i0 ad_reconct axi_ad9361/up_adc_gpio_in up_adc_gpio_in
ad_connect core_dac_i0_valid axi_ad9361/dac_valid_i0 ad_reconct axi_ad9361/up_dac_gpio_out up_dac_gpio_out
ad_connect core_dac_q0_enable axi_ad9361/dac_enable_q0 ad_reconct axi_ad9361/up_adc_gpio_out up_adc_gpio_out
ad_connect core_dac_q0_data axi_ad9361/dac_data_q0
ad_connect core_dac_q0_valid axi_ad9361/dac_valid_q0
ad_connect core_dac_i1_enable axi_ad9361/dac_enable_i1
ad_connect core_dac_i1_data axi_ad9361/dac_data_i1
ad_connect core_dac_i1_valid axi_ad9361/dac_valid_i1
ad_connect core_dac_q1_enable axi_ad9361/dac_enable_q1
ad_connect core_dac_q1_data axi_ad9361/dac_data_q1
ad_connect core_dac_q1_valid axi_ad9361/dac_valid_q1
# rx data path
ad_connect dma_adc_i0_enable util_ad9361_adc_pack/adc_enable_0
ad_connect dma_adc_i0_data util_ad9361_adc_pack/adc_data_0
ad_connect dma_adc_i0_valid util_ad9361_adc_pack/adc_valid_0
ad_connect dma_adc_q0_enable util_ad9361_adc_pack/adc_enable_1
ad_connect dma_adc_q0_data util_ad9361_adc_pack/adc_data_1
ad_connect dma_adc_q0_valid util_ad9361_adc_pack/adc_valid_1
ad_connect dma_adc_i1_enable util_ad9361_adc_pack/adc_enable_2
ad_connect dma_adc_i1_data util_ad9361_adc_pack/adc_data_2
ad_connect dma_adc_i1_valid util_ad9361_adc_pack/adc_valid_2
ad_connect dma_adc_q1_enable util_ad9361_adc_pack/adc_enable_3
ad_connect dma_adc_q1_data util_ad9361_adc_pack/adc_data_3
ad_connect dma_adc_q1_valid util_ad9361_adc_pack/adc_valid_3
ad_connect core_adc_i0_enable util_ad9361_adc_fifo/dout_enable_0
ad_connect core_adc_i0_data util_ad9361_adc_fifo/dout_data_0
ad_connect core_adc_i0_valid util_ad9361_adc_fifo/dout_valid_0
ad_connect core_adc_q0_enable util_ad9361_adc_fifo/dout_enable_1
ad_connect core_adc_q0_data util_ad9361_adc_fifo/dout_data_1
ad_connect core_adc_q0_valid util_ad9361_adc_fifo/dout_valid_1
ad_connect core_adc_i1_enable util_ad9361_adc_fifo/dout_enable_2
ad_connect core_adc_i1_data util_ad9361_adc_fifo/dout_data_2
ad_connect core_adc_i1_valid util_ad9361_adc_fifo/dout_valid_2
ad_connect core_adc_q1_enable util_ad9361_adc_fifo/dout_enable_3
ad_connect core_adc_q1_data util_ad9361_adc_fifo/dout_data_3
ad_connect core_adc_q1_valid util_ad9361_adc_fifo/dout_valid_3
ad_connect up_dac_gpio_in axi_ad9361/up_dac_gpio_in
ad_connect up_adc_gpio_in axi_ad9361/up_adc_gpio_in
ad_connect up_dac_gpio_out axi_ad9361/up_dac_gpio_out
ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out
# rx side monitoring
set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_0
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_0
ad_connect sys_cpu_clk ila_rx_0/clk
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1
set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_1
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_1
ad_connect sys_cpu_clk ila_rx_1/clk
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_1/probe0
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_1/probe1
set ila_rx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_2]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_2
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_2
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_2
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_2
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_2
ad_connect sys_cpu_clk ila_rx_2/clk
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_2/probe0
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_2/probe1
set ila_rx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_3]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_3
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_3
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_3
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_3
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_3
ad_connect sys_cpu_clk ila_rx_3/clk
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_3/probe0
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_3/probe1
# rx side monitoring
set ila_tx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_0]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_0
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_0
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_0
ad_connect axi_ad9361/l_clk ila_tx_0/clk
ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0
ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1
set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_1
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_1
ad_connect axi_ad9361/l_clk ila_tx_1/clk
ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0
ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1
set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_2
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_2
ad_connect axi_ad9361/l_clk ila_tx_2/clk
ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0
ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1
set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_3
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_3
ad_connect axi_ad9361/l_clk ila_tx_3/clk
ad_connect util_ad9361_adc_fifo/dout_valid_3 ila_tx_3/probe0
ad_connect util_ad9361_adc_fifo/dout_data_3 ila_tx_3/probe1

33
projects/fmcomms2/zc706pr/Makefile
View File

@ -5,22 +5,30 @@
#################################################################################### ####################################################################################
#################################################################################### ####################################################################################
M_DEPS := system_project.tcl M_DEPS += system_top.v
M_DEPS += ../../scripts/adi_env.tcl M_DEPS += system_project.tcl
M_DEPS += ../../scripts/adi_project.tcl M_DEPS += system_constr.xdc
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += system_bd.tcl M_DEPS += system_bd.tcl
M_DEPS += ../zc706/system_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../common/fmcomms2_bd.tcl M_DEPS += ../common/fmcomms2_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_DEPS += ../zc706/system_bd.tcl
M_DEPS += ../zc706/system_constr.xdc
M_DEPS += ../common/prcfg_bd.tcl
M_DEPS += ../common/prcfg_bb.v
M_VIVADO := vivado -mode batch -source M_VIVADO := vivado -mode batch -source
@ -33,12 +41,15 @@ M_FLIST += xgui
M_FLIST += *.runs M_FLIST += *.runs
M_FLIST += *.srcs M_FLIST += *.srcs
M_FLIST += *.sdk M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all .PHONY: all lib clean clean-all
all: lib fmcomms2_zc706pr.sdk/system_top.hdf all: lib fmcomms2_zc706.sdk/system_top.hdf
clean: clean:
@ -52,13 +63,14 @@ clean-all:clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
fmcomms2_zc706pr.sdk/system_top.hdf: $(M_DEPS) fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS)
rm -rf $(M_FLIST) -rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms2_zc706pr_vivado.log 2>&1 $(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1
lib: lib:
@ -68,6 +80,7 @@ lib:
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

26
projects/fmcomms2/zc706pr/system_project.tcl
View File

@ -1,10 +1,32 @@
## requires partial reconfiguration license
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
set mode 0
if {$::argc > 0} {
set mode [lindex $argv 0]
}
if {$mode == 0} {
adi_project_create fmcomms2_zc706
adi_project_files fmcomms2_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
"$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \
"$ad_hdl_dir/library/prcfg/default/prcfg_adc.v" \
"../common/prcfg.v" \
"../zc706/system_constr.xdc" \
"system_top.v" ]
adi_project_run fmcomms2_zc706
return
}
adi_project_create fmcomms2_zc706 1 adi_project_create fmcomms2_zc706 1
adi_project_synth fmcomms2_zc706 "" \ adi_project_synth fmcomms2_zc706 "" \
[list "system_top.v" \ [list "system_top.v" \

55
projects/fmcomms2/zc706pr/system_top.v
View File

@ -88,8 +88,13 @@ module system_top (
tx_data_out_p, tx_data_out_p,
tx_data_out_n, tx_data_out_n,
gpio_txnrx, enable,
gpio_enable, txnrx,
tdd_sync,
gpio_muxout_tx,
gpio_muxout_rx,
gpio_resetb, gpio_resetb,
gpio_sync, gpio_sync,
gpio_en_agc, gpio_en_agc,
@ -99,7 +104,12 @@ module system_top (
spi_csn, spi_csn,
spi_clk, spi_clk,
spi_mosi, spi_mosi,
spi_miso); spi_miso,
spi_udc_csn_tx,
spi_udc_csn_rx,
spi_udc_sclk,
spi_udc_data);
inout [14:0] ddr_addr; inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba; inout [ 2:0] ddr_ba;
@ -150,8 +160,13 @@ module system_top (
output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n; output [ 5:0] tx_data_out_n;
inout gpio_txnrx; output enable;
inout gpio_enable; output txnrx;
inout tdd_sync;
inout gpio_muxout_tx;
inout gpio_muxout_rx;
inout gpio_resetb; inout gpio_resetb;
inout gpio_sync; inout gpio_sync;
inout gpio_en_agc; inout gpio_en_agc;
@ -163,12 +178,16 @@ module system_top (
output spi_mosi; output spi_mosi;
input spi_miso; input spi_miso;
output spi_udc_csn_tx;
output spi_udc_csn_rx;
output spi_udc_sclk;
output spi_udc_data;
// internal signals // internal signals
wire [63:0] gpio_i; wire [63:0] gpio_i;
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
wire clk; wire clk;
wire dma_dac_i0_enable; wire dma_dac_i0_enable;
wire [15:0] dma_dac_i0_data; wire [15:0] dma_dac_i0_data;
@ -218,7 +237,6 @@ module system_top (
wire core_adc_q1_enable; wire core_adc_q1_enable;
wire [15:0] core_adc_q1_data; wire [15:0] core_adc_q1_data;
wire core_adc_q1_valid; wire core_adc_q1_valid;
wire [31:0] adc_gpio_input; wire [31:0] adc_gpio_input;
wire [31:0] adc_gpio_output; wire [31:0] adc_gpio_output;
wire [31:0] dac_gpio_input; wire [31:0] dac_gpio_input;
@ -254,6 +272,7 @@ module system_top (
.dio_p (tdd_sync)); .dio_p (tdd_sync));
// prcfg instance // prcfg instance
prcfg i_prcfg ( prcfg i_prcfg (
.clk (clk), .clk (clk),
.adc_gpio_input (adc_gpio_input), .adc_gpio_input (adc_gpio_input),
@ -307,8 +326,7 @@ module system_top (
.core_adc_i1_valid (core_adc_i1_valid), .core_adc_i1_valid (core_adc_i1_valid),
.core_adc_q1_enable (core_adc_q1_enable), .core_adc_q1_enable (core_adc_q1_enable),
.core_adc_q1_data (core_adc_q1_data), .core_adc_q1_data (core_adc_q1_data),
.core_adc_q1_valid (core_adc_q1_valid) .core_adc_q1_valid (core_adc_q1_valid));
);
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr), .ddr_addr (ddr_addr),
@ -371,13 +389,27 @@ module system_top (
.spi0_sdi_i (spi_miso), .spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0), .spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi), .spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (spi_udc_sclk),
.spi1_csn_0_o (spi_udc_csn_tx),
.spi1_csn_1_o (spi_udc_csn_rx),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (spi_udc_data),
.spi1_sdo_o (spi_udc_data),
.tdd_sync_i (tdd_sync_i),
.tdd_sync_o (tdd_sync_o),
.tdd_sync_t (tdd_sync_t),
.tx_clk_out_n (tx_clk_out_n), .tx_clk_out_n (tx_clk_out_n),
.tx_clk_out_p (tx_clk_out_p), .tx_clk_out_p (tx_clk_out_p),
.tx_data_out_n (tx_data_out_n), .tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p), .tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n), .tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p), .tx_frame_out_p (tx_frame_out_p),
// pr related ports .txnrx (txnrx),
.up_enable (gpio_o[47]),
.up_txnrx (gpio_o[48]),
.clk (clk), .clk (clk),
.up_adc_gpio_in (adc_gpio_input), .up_adc_gpio_in (adc_gpio_input),
.up_adc_gpio_out (adc_gpio_output), .up_adc_gpio_out (adc_gpio_output),
@ -430,8 +462,7 @@ module system_top (
.core_adc_i1_valid (core_adc_i1_valid), .core_adc_i1_valid (core_adc_i1_valid),
.core_adc_q1_enable (core_adc_q1_enable), .core_adc_q1_enable (core_adc_q1_enable),
.core_adc_q1_data (core_adc_q1_data), .core_adc_q1_data (core_adc_q1_data),
.core_adc_q1_valid (core_adc_q1_valid) .core_adc_q1_valid (core_adc_q1_valid));
);
endmodule endmodule