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adcfifo_axi: added

main
Rejeesh Kutty 2015-04-07 16:00:47 -04:00
parent 056d6bbf40
commit 69cadd46ed
8 changed files with 1539 additions and 0 deletions
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
## Fri Apr 3 11:55:07 2015
####################################################################################
####################################################################################
M_DEPS := util_adcfifo_axi_ip.tcl
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../common/ad_mem.v
M_DEPS += ../common/ad_mem_asym.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../common/ad_axis_inf_rx.v
M_DEPS += util_adcfifo_axi_adc.v
M_DEPS += util_adcfifo_axi_dma.v
M_DEPS += util_adcfifo_axi_wr.v
M_DEPS += util_adcfifo_axi_rd.v
M_DEPS += util_adcfifo_axi.v
M_DEPS += util_adcfifo_axi_constr.xdc
C_VIVADO := vivado -mode batch -source
F_LIST := `find . -not -name '.' -not -name '*.tcl' -not -name '*.v' -not -name '*.xdc' -not -name '*.vhd' -not -name '*.prj' -not -name 'Makefile' -not -name '*.h' `
.PHONY: all
all: util_adcfifo_axi.xpr
.PHONY: clean
clean:clean-all
.PHONY: clean-all
clean-all:
rm -rf $(F_LIST)
util_adcfifo_axi.xpr: $(M_DEPS)
rm -rf $(F_LIST)
$(C_VIVADO) util_adcfifo_axi_ip.tcl >> util_adcfifo_axi_ip.log 2>&1
####################################################################################
####################################################################################

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library/util_adcfifo_axi/util_adcfifo_axi.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_adcfifo_axi (
// fifo interface
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
adc_wovf,
// dma interface
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status,
// axi interface
axi_clk,
axi_resetn,
axi_awvalid,
axi_awid,
axi_awburst,
axi_awlock,
axi_awcache,
axi_awprot,
axi_awqos,
axi_awuser,
axi_awlen,
axi_awsize,
axi_awaddr,
axi_awready,
axi_wvalid,
axi_wdata,
axi_wstrb,
axi_wlast,
axi_wuser,
axi_wready,
axi_bvalid,
axi_bid,
axi_bresp,
axi_buser,
axi_bready,
axi_arvalid,
axi_arid,
axi_arburst,
axi_arlock,
axi_arcache,
axi_arprot,
axi_arqos,
axi_aruser,
axi_arlen,
axi_arsize,
axi_araddr,
axi_arready,
axi_rvalid,
axi_rid,
axi_ruser,
axi_rresp,
axi_rlast,
axi_rdata,
axi_rready);
// parameters
parameter ADC_DATA_WIDTH = 128;
parameter DMA_DATA_WIDTH = 64;
parameter AXI_DATA_WIDTH = 512;
parameter DMA_READY_ENABLE = 1;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'hffffffff;
parameter AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
// adc interface
input adc_rst;
input adc_clk;
input adc_wr;
input [ADC_DATA_WIDTH-1:0] adc_wdata;
output adc_wovf;
// dma interface
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// axi interface
input axi_clk;
input axi_resetn;
output axi_awvalid;
output [ 3:0] axi_awid;
output [ 1:0] axi_awburst;
output axi_awlock;
output [ 3:0] axi_awcache;
output [ 2:0] axi_awprot;
output [ 3:0] axi_awqos;
output [ 3:0] axi_awuser;
output [ 7:0] axi_awlen;
output [ 2:0] axi_awsize;
output [ 31:0] axi_awaddr;
input axi_awready;
output axi_wvalid;
output [AXI_DATA_WIDTH-1:0] axi_wdata;
output [AXI_BYTE_WIDTH-1:0] axi_wstrb;
output axi_wlast;
output [ 3:0] axi_wuser;
input axi_wready;
input axi_bvalid;
input [ 3:0] axi_bid;
input [ 1:0] axi_bresp;
input [ 3:0] axi_buser;
output axi_bready;
output axi_arvalid;
output [ 3:0] axi_arid;
output [ 1:0] axi_arburst;
output axi_arlock;
output [ 3:0] axi_arcache;
output [ 2:0] axi_arprot;
output [ 3:0] axi_arqos;
output [ 3:0] axi_aruser;
output [ 7:0] axi_arlen;
output [ 2:0] axi_arsize;
output [ 31:0] axi_araddr;
input axi_arready;
input axi_rvalid;
input [ 3:0] axi_rid;
input [ 3:0] axi_ruser;
input [ 1:0] axi_rresp;
input axi_rlast;
input [AXI_DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// internal signals
wire adc_dwr_s;
wire [AXI_DATA_WIDTH-1:0] adc_ddata_s;
wire axi_rd_req_s;
wire [ 31:0] axi_rd_addr_s;
wire [ 3:0] axi_xfer_status_s;
wire axi_drst_s;
wire axi_dvalid_s;
wire [AXI_DATA_WIDTH-1:0] axi_ddata_s;
wire axi_dready_s;
// instantiations
util_adcfifo_axi_adc #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.ADC_DATA_WIDTH (ADC_DATA_WIDTH))
i_adc_if (
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_wr (adc_wr),
.adc_wdata (adc_wdata),
.adc_wovf (adc_wovf),
.adc_dwr (adc_dwr_s),
.adc_ddata (adc_ddata_s),
.axi_drst (axi_drst_s),
.axi_clk (axi_clk),
.axi_xfer_status (axi_xfer_status_s));
util_adcfifo_axi_wr #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
i_wr (
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_wr (adc_dwr_s),
.adc_wdata (adc_ddata_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_awvalid (axi_awvalid),
.axi_awid (axi_awid),
.axi_awburst (axi_awburst),
.axi_awlock (axi_awlock),
.axi_awcache (axi_awcache),
.axi_awprot (axi_awprot),
.axi_awqos (axi_awqos),
.axi_awuser (axi_awuser),
.axi_awlen (axi_awlen),
.axi_awsize (axi_awsize),
.axi_awaddr (axi_awaddr),
.axi_awready (axi_awready),
.axi_wvalid (axi_wvalid),
.axi_wdata (axi_wdata),
.axi_wstrb (axi_wstrb),
.axi_wlast (axi_wlast),
.axi_wuser (axi_wuser),
.axi_wready (axi_wready),
.axi_bvalid (axi_bvalid),
.axi_bid (axi_bid),
.axi_bresp (axi_bresp),
.axi_buser (axi_buser),
.axi_bready (axi_bready),
.axi_dwovf (axi_xfer_status_s[0]),
.axi_dwunf (axi_xfer_status_s[1]),
.axi_werror (axi_xfer_status_s[2]));
util_adcfifo_axi_rd #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
i_rd (
.dma_xfer_req (dma_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_arvalid (axi_arvalid),
.axi_arid (axi_arid),
.axi_arburst (axi_arburst),
.axi_arlock (axi_arlock),
.axi_arcache (axi_arcache),
.axi_arprot (axi_arprot),
.axi_arqos (axi_arqos),
.axi_aruser (axi_aruser),
.axi_arlen (axi_arlen),
.axi_arsize (axi_arsize),
.axi_araddr (axi_araddr),
.axi_arready (axi_arready),
.axi_rvalid (axi_rvalid),
.axi_rid (axi_rid),
.axi_ruser (axi_ruser),
.axi_rresp (axi_rresp),
.axi_rlast (axi_rlast),
.axi_rdata (axi_rdata),
.axi_rready (axi_rready),
.axi_rerror (axi_xfer_status_s[3]),
.axi_drst (axi_drst_s),
.axi_dvalid (axi_dvalid_s),
.axi_ddata (axi_ddata_s),
.axi_dready (axi_dready_s));
util_adcfifo_axi_dma #(
.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DMA_READY_ENABLE (DMA_READY_ENABLE))
i_dma_if (
.axi_clk (axi_clk),
.axi_drst (axi_drst_s),
.axi_dvalid (axi_dvalid_s),
.axi_ddata (axi_ddata_s),
.axi_dready (axi_dready_s),
.axi_xfer_status (axi_xfer_status_s),
.dma_clk (dma_clk),
.dma_wr (dma_wr),
.dma_wdata (dma_wdata),
.dma_wready (dma_wready),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_status (dma_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/util_adcfifo_axi/util_adcfifo_axi_adc.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_adcfifo_axi_adc (
// fifo interface
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
adc_wovf,
adc_dwr,
adc_ddata,
// axi interface
axi_drst,
axi_clk,
axi_xfer_status);
// parameters
parameter ADC_DATA_WIDTH = 128;
parameter AXI_DATA_WIDTH = 512;
localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH;
// adc interface
input adc_rst;
input adc_clk;
input adc_wr;
input [ADC_DATA_WIDTH-1:0] adc_wdata;
output adc_wovf;
output adc_dwr;
output [AXI_DATA_WIDTH-1:0] adc_ddata;
// axi interface
input axi_clk;
input axi_drst;
input [ 3:0] axi_xfer_status;
// internal registers
reg adc_wovf = 'd0;
reg [ 2:0] adc_wcnt_int = 'd0;
reg adc_dwr = 'd0;
reg [AXI_DATA_WIDTH-1:0] adc_ddata = 'd0;
// internal signals
wire [ 3:0] adc_xfer_status_s;
// write interface: supports only 64, 128, 256 and 512 against 512
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_wovf <= 'd0;
adc_wcnt_int <= 'd0;
adc_dwr <= 'd0;
adc_ddata <= 'd0;
end else begin
adc_wovf <= | adc_xfer_status_s;
adc_dwr <= (ADC_MEM_RATIO == 8) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2] :
(ADC_MEM_RATIO == 4) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] :
(ADC_MEM_RATIO == 2) ? adc_wr & adc_wcnt_int[0] :
(ADC_MEM_RATIO == 1) ? adc_wr : 'd0;
if (adc_wr == 1'b1) begin
adc_wcnt_int <= adc_wcnt_int + 1'b1;
case (ADC_MEM_RATIO)
8: begin
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)];
end
4: begin
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)];
end
2: begin
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata;
adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <=
adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)];
end
1: begin
adc_ddata <= adc_wdata;
end
default: begin
adc_ddata <= 'd0;
end
endcase
end
end
end
// instantiations
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~adc_rst),
.up_clk (adc_clk),
.up_data_status (adc_xfer_status_s),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************

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set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *up_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *up_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_adcfifo_axi_dma (
axi_clk,
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready,
axi_xfer_status,
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter DMA_DATA_WIDTH = 64;
parameter DMA_READY_ENABLE = 1;
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDR_WIDTH = 8;
localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
// adc write
input axi_clk;
input axi_drst;
input axi_dvalid;
input [AXI_DATA_WIDTH-1:0] axi_ddata;
output axi_dready;
input [ 3:0] axi_xfer_status;
// dma read
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// internal registers
reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0;
reg axi_dready = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_waddr <= 'd0;
axi_waddr_rel_count <= 'd0;
axi_waddr_rel_t <= 'd0;
axi_waddr_rel <= 'd0;
end else begin
if (axi_dvalid == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
if (axi_waddr_rel_count == 3'd7) begin
axi_waddr_rel_t <= ~axi_waddr_rel_t;
axi_waddr_rel <= axi_waddr;
end
end
end
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_raddr_rel_t_m <= 'd0;
axi_raddr_rel <= 'd0;
axi_addr_diff <= 'd0;
axi_dready <= 'd0;
end else begin
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
axi_dready <= 1'b1;
end
end
end
// read interface
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= axi_waddr_rel;
end
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
dma_raddr_rel_count <= 'd0;
dma_raddr_rel_t <= 'd0;
dma_raddr_rel <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
if (dma_raddr_rel_count == 3'd7) begin
dma_raddr_rel_t <= ~dma_raddr_rel_t;
dma_raddr_rel <= dma_raddr;
end
end
end
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (AXI_ADDR_WIDTH),
.DATA_WIDTH_A (AXI_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),
.addra (axi_waddr),
.dina (axi_ddata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~dma_rst),
.up_clk (dma_clk),
.up_data_status (dma_xfer_status),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/util_adcfifo_axi/util_adcfifo_axi_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_adcfifo_axi
adi_ip_files util_adcfifo_axi [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"util_adcfifo_axi_adc.v" \
"util_adcfifo_axi_dma.v" \
"util_adcfifo_axi_wr.v" \
"util_adcfifo_axi_rd.v" \
"util_adcfifo_axi.v" \
"util_adcfifo_axi_constr.xdc" ]
adi_ip_properties_lite util_adcfifo_axi
adi_ip_constraints util_adcfifo_axi [list \
"util_adcfifo_axi_constr.xdc" ]
ipx::infer_bus_interfaces {{xilinx.com:interface:aximm:1.0}} [ipx::current_core]
ipx::save_core [ipx::current_core]

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library/util_adcfifo_axi/util_adcfifo_axi_rd.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_adcfifo_axi_rd (
// request and synchronization
dma_xfer_req,
// read interface
axi_rd_req,
axi_rd_addr,
// axi interface
axi_clk,
axi_resetn,
axi_arvalid,
axi_arid,
axi_arburst,
axi_arlock,
axi_arcache,
axi_arprot,
axi_arqos,
axi_aruser,
axi_arlen,
axi_arsize,
axi_araddr,
axi_arready,
axi_rvalid,
axi_rid,
axi_ruser,
axi_rresp,
axi_rlast,
axi_rdata,
axi_rready,
// axi status
axi_rerror,
// fifo interface
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
// request and synchronization
input dma_xfer_req;
// read interface
input axi_rd_req;
input [ 31:0] axi_rd_addr;
// axi interface
input axi_clk;
input axi_resetn;
output axi_arvalid;
output [ 3:0] axi_arid;
output [ 1:0] axi_arburst;
output axi_arlock;
output [ 3:0] axi_arcache;
output [ 2:0] axi_arprot;
output [ 3:0] axi_arqos;
output [ 3:0] axi_aruser;
output [ 7:0] axi_arlen;
output [ 2:0] axi_arsize;
output [ 31:0] axi_araddr;
input axi_arready;
input axi_rvalid;
input [ 3:0] axi_rid;
input [ 3:0] axi_ruser;
input [ 1:0] axi_rresp;
input axi_rlast;
input [AXI_DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// axi status
output axi_rerror;
// fifo interface
output axi_drst;
output axi_dvalid;
output [AXI_DATA_WIDTH-1:0] axi_ddata;
input axi_dready;
// internal registers
reg [ 31:0] axi_rd_addr_h = 'd0;
reg axi_rd = 'd0;
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_xfer_enable = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_drst = 'd0;
reg axi_dvalid = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_ddata = 'd0;
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
// internal signals
wire axi_ready_s;
// read is way too slow- buffer mode
assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_addr_h <= 'd0;
axi_rd <= 'd0;
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
axi_xfer_enable <= 'd0;
end else begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr_h <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr_h <= axi_rd_addr;
end
if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0;
if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin
axi_rd_active <= 1'b0;
end
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin
axi_rd <= axi_xfer_enable;
axi_rd_active <= axi_xfer_enable;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
axi_xfer_enable <= axi_xfer_req_m[2];
end
end
// address channel
assign axi_arid = 4'b0000;
assign axi_arburst = 2'b01;
assign axi_arlock = 1'b0;
assign axi_arcache = 4'b0010;
assign axi_arprot = 3'b000;
assign axi_arqos = 4'b0000;
assign axi_aruser = 4'b0001;
assign axi_arlen = AXI_LENGTH - 1;
assign axi_arsize = AXI_SIZE;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_arvalid <= 'd0;
axi_araddr <= 'd0;
end else begin
if (axi_arvalid == 1'b1) begin
if (axi_arready == 1'b1) begin
axi_arvalid <= 1'b0;
end
end else begin
if (axi_rd == 1'b1) begin
axi_arvalid <= 1'b1;
end
end
if (axi_xfer_init == 1'b1) begin
axi_araddr <= AXI_ADDRESS;
end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
axi_araddr <= axi_araddr + AXI_AWINCR;
end
end
end
// read data channel
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_drst <= 'd1;
axi_dvalid <= 'd0;
axi_ddata <= 'd0;
axi_rready <= 'd0;
end else begin
axi_drst <= ~axi_xfer_req_m[1];
axi_dvalid <= axi_rvalid;
axi_ddata <= axi_rdata;
axi_rready <= 1'b1;
end
end
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rerror <= 'd0;
end else begin
axi_rerror <= axi_rvalid & axi_rresp[1];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_adcfifo_axi_wr (
// request and synchronization
dma_xfer_req,
// read interface
axi_rd_req,
axi_rd_addr,
// fifo interface
adc_rst,
adc_clk,
adc_wr,
adc_wdata,
// axi interface
axi_clk,
axi_resetn,
axi_awvalid,
axi_awid,
axi_awburst,
axi_awlock,
axi_awcache,
axi_awprot,
axi_awqos,
axi_awuser,
axi_awlen,
axi_awsize,
axi_awaddr,
axi_awready,
axi_wvalid,
axi_wdata,
axi_wstrb,
axi_wlast,
axi_wuser,
axi_wready,
axi_bvalid,
axi_bid,
axi_bresp,
axi_buser,
axi_bready,
// axi status
axi_dwovf,
axi_dwunf,
axi_werror);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
localparam BUF_THRESHOLD_LO = 8'd6;
localparam BUF_THRESHOLD_HI = 8'd250;
// request and synchronization
input dma_xfer_req;
// read interface
output axi_rd_req;
output [ 31:0] axi_rd_addr;
// fifo interface
input adc_rst;
input adc_clk;
input adc_wr;
input [AXI_DATA_WIDTH-1:0] adc_wdata;
// axi interface
input axi_clk;
input axi_resetn;
output axi_awvalid;
output [ 3:0] axi_awid;
output [ 1:0] axi_awburst;
output axi_awlock;
output [ 3:0] axi_awcache;
output [ 2:0] axi_awprot;
output [ 3:0] axi_awqos;
output [ 3:0] axi_awuser;
output [ 7:0] axi_awlen;
output [ 2:0] axi_awsize;
output [ 31:0] axi_awaddr;
input axi_awready;
output axi_wvalid;
output [AXI_DATA_WIDTH-1:0] axi_wdata;
output [AXI_BYTE_WIDTH-1:0] axi_wstrb;
output axi_wlast;
output [ 3:0] axi_wuser;
input axi_wready;
input axi_bvalid;
input [ 3:0] axi_bid;
input [ 1:0] axi_bresp;
input [ 3:0] axi_buser;
output axi_bready;
// axi status
output axi_dwovf;
output axi_dwunf;
output axi_werror;
// internal registers
reg [ 2:0] adc_xfer_req_m = 'd0;
reg adc_xfer_init = 'd0;
reg adc_xfer_limit = 'd0;
reg adc_xfer_enable = 'd0;
reg [ 31:0] adc_xfer_addr = 'd0;
reg [ 7:0] adc_waddr = 'd0;
reg [ 7:0] adc_waddr_g = 'd0;
reg adc_rel_enable = 'd0;
reg adc_rel_toggle = 'd0;
reg [ 7:0] adc_rel_waddr = 'd0;
reg [ 2:0] axi_rel_toggle_m = 'd0;
reg [ 7:0] axi_rel_waddr = 'd0;
reg [ 7:0] axi_waddr_m1 = 'd0;
reg [ 7:0] axi_waddr_m2 = 'd0;
reg [ 7:0] axi_waddr = 'd0;
reg [ 7:0] axi_addr_diff = 'd0;
reg axi_almost_full = 'd0;
reg axi_dwunf = 'd0;
reg axi_almost_empty = 'd0;
reg axi_dwovf = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg [ 7:0] axi_raddr = 'd0;
reg axi_rd = 'd0;
reg axi_rlast = 'd0;
reg axi_rd_d = 'd0;
reg axi_rlast_d = 'd0;
reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0;
reg axi_rd_req = 'd0;
reg [ 31:0] axi_rd_addr = 'd0;
reg axi_awvalid = 'd0;
reg [ 31:0] axi_awaddr = 'd0;
reg axi_werror = 'd0;
reg axi_reset = 'd0;
// internal signals
wire axi_rel_toggle_s;
wire [ 8:0] axi_addr_diff_s;
wire axi_wready_s;
wire axi_rd_s;
wire axi_req_s;
wire axi_rlast_s;
wire [AXI_DATA_WIDTH-1:0] axi_rdata_s;
// binary to grey conversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// fifo interface
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 'd0;
adc_waddr_g <= 'd0;
adc_xfer_req_m <= 'd0;
adc_xfer_init <= 'd0;
adc_xfer_limit <= 'd0;
adc_xfer_enable <= 'd0;
adc_xfer_addr <= 'd0;
adc_rel_enable <= 'd0;
adc_rel_toggle <= 'd0;
adc_rel_waddr <= 'd0;
end else begin
if ((adc_wr == 1'b1) && (adc_xfer_enable == 1'b1)) begin
adc_waddr <= adc_waddr + 1'b1;
end
adc_waddr_g <= b2g(adc_waddr);
adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
if (adc_xfer_init == 1'b1) begin
adc_xfer_limit <= 1'd1;
end else if ((adc_xfer_addr >= AXI_ADDRLIMIT) || (adc_xfer_enable == 1'b0)) begin
adc_xfer_limit <= 1'd0;
end
if (adc_xfer_init == 1'b1) begin
adc_xfer_enable <= 1'b1;
adc_xfer_addr <= AXI_ADDRESS;
end else if ((adc_waddr[1:0] == 2'h3) && (adc_wr == 1'b1)) begin
adc_xfer_enable <= adc_xfer_req_m[2] & adc_xfer_limit;
adc_xfer_addr <= adc_xfer_addr + AXI_AWINCR;
end
if (adc_waddr[1:0] == 2'h3) begin
adc_rel_enable <= adc_wr;
end else begin
adc_rel_enable <= 1'd0;
end
if (adc_rel_enable == 1'b1) begin
adc_rel_toggle <= ~adc_rel_toggle;
adc_rel_waddr <= adc_waddr;
end
end
end
// fifo signals on axi side
assign axi_rel_toggle_s = axi_rel_toggle_m[2] ^ axi_rel_toggle_m[1];
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rel_toggle_m <= 'd0;
axi_rel_waddr <= 'd0;
axi_waddr_m1 <= 'd0;
axi_waddr_m2 <= 'd0;
axi_waddr <= 'd0;
end else begin
axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], adc_rel_toggle};
if (axi_rel_toggle_s == 1'b1) begin
axi_rel_waddr <= adc_rel_waddr;
end
axi_waddr_m1 <= adc_waddr_g;
axi_waddr_m2 <= axi_waddr_m1;
axi_waddr <= g2b(axi_waddr_m2);
end
end
// overflow (no underflow possible)
assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_addr_diff <= 'd0;
axi_almost_full <= 'd0;
axi_dwunf <= 'd0;
axi_almost_empty <= 'd0;
axi_dwovf <= 'd0;
end else begin
axi_addr_diff <= axi_addr_diff_s[7:0];
if (axi_addr_diff > BUF_THRESHOLD_HI) begin
axi_almost_full <= 1'b1;
axi_dwunf <= axi_almost_empty;
end else begin
axi_almost_full <= 1'b0;
axi_dwunf <= 1'b0;
end
if (axi_addr_diff < BUF_THRESHOLD_LO) begin
axi_almost_empty <= 1'b1;
axi_dwovf <= axi_almost_full;
end else begin
axi_almost_empty <= 1'b0;
axi_dwovf <= 1'b0;
end
end
end
// transfer request is required to keep things in sync
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
end else begin
axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
end
end
// read is initiated if xfer enabled
assign axi_wready_s = ~axi_wvalid | axi_wready;
assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : axi_wready_s;
assign axi_req_s = (axi_raddr[1:0] == 2'h0) ? axi_rd_s : 1'b0;
assign axi_rlast_s = (axi_raddr[1:0] == 2'h3) ? axi_rd_s : 1'b0;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_raddr <= 'd0;
axi_rd <= 'd0;
axi_rlast <= 'd0;
axi_rd_d <= 'd0;
axi_rlast_d <= 'd0;
axi_rdata_d <= 'd0;
end else begin
if (axi_rd_s == 1'b1) begin
axi_raddr <= axi_raddr + 1'b1;
end
axi_rd <= axi_rd_s;
axi_rlast <= axi_rlast_s;
axi_rd_d <= axi_rd;
axi_rlast_d <= axi_rlast;
axi_rdata_d <= axi_rdata_s;
end
end
// send read request for every burst about to be completed
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_req <= 'd0;
axi_rd_addr <= 'd0;
end else begin
axi_rd_req <= axi_rlast_s;
if (axi_xfer_init == 1'b1) begin
axi_rd_addr <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr <= axi_rd_addr + AXI_AWINCR;
end
end
end
// address channel
assign axi_awid = 4'b0000;
assign axi_awburst = 2'b01;
assign axi_awlock = 1'b0;
assign axi_awcache = 4'b0010;
assign axi_awprot = 3'b000;
assign axi_awqos = 4'b0000;
assign axi_awuser = 4'b0001;
assign axi_awlen = AXI_LENGTH - 1;
assign axi_awsize = AXI_SIZE;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_awvalid <= 'd0;
axi_awaddr <= 'd0;
end else begin
if (axi_awvalid == 1'b1) begin
if (axi_awready == 1'b1) begin
axi_awvalid <= 1'b0;
end
end else begin
if (axi_req_s == 1'b1) begin
axi_awvalid <= 1'b1;
end
end
if (axi_xfer_init == 1'b1) begin
axi_awaddr <= AXI_ADDRESS;
end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awaddr <= axi_awaddr + AXI_AWINCR;
end
end
end
// write channel
assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
assign axi_wuser = 4'b0000;
// response channel
assign axi_bready = 1'b1;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_werror <= 'd0;
end else begin
axi_werror <= axi_bvalid & axi_bready & axi_bresp[1];
end
end
// fifo needs a reset
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_reset <= 1'b1;
end else begin
axi_reset <= 1'b0;
end
end
// interface handler
ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
.clk (axi_clk),
.rst (axi_reset),
.valid (axi_rd_d),
.last (axi_rlast_d),
.data (axi_rdata_d),
.inf_valid (axi_wvalid),
.inf_last (axi_wlast),
.inf_data (axi_wdata),
.inf_ready (axi_wready));
// buffer
ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDR_WIDTH(8)) i_mem (
.clka (adc_clk),
.wea (adc_wr),
.addra (adc_waddr),
.dina (adc_wdata),
.clkb (axi_clk),
.addrb (axi_raddr),
.doutb (axi_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************