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axi_ad6676: Added CDC and reset constraints

main
Adrian Costina 2015-04-23 10:16:29 +03:00
parent e25cfb9d9f
commit 691c54e0dd
2 changed files with 43 additions and 2 deletions
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41
library/axi_ad6676/axi_ad6676_constr.xdc
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@ -1,4 +1,45 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set ad6676_clk [get_clocks -of_objects [get_ports rx_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $ad6676_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

4
library/axi_ad6676/axi_ad6676_ip.tcl Executable file → Normal file
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@ -18,8 +18,8 @@ adi_ip_files axi_ad6676 [list \
"axi_ad6676_pnmon.v" \ "axi_ad6676_pnmon.v" \
"axi_ad6676_channel.v" \ "axi_ad6676_channel.v" \
"axi_ad6676_if.v" \ "axi_ad6676_if.v" \
"axi_ad6676.v" \ "axi_ad6676_constr.xdc" \
"axi_ad6676_constr.xdc" ] "axi_ad6676.v" ]
adi_ip_properties axi_ad6676 adi_ip_properties axi_ad6676
adi_ip_constraints axi_ad6676 [list \ adi_ip_constraints axi_ad6676 [list \