From 691c54e0dd0226e26cb921aca25d7d0adab31f4b Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Thu, 23 Apr 2015 10:16:29 +0300
Subject: [PATCH] axi_ad6676: Added CDC and reset constraints

---
 library/axi_ad6676/axi_ad6676_constr.xdc | 41 ++++++++++++++++++++++++
 library/axi_ad6676/axi_ad6676_ip.tcl     |  4 +--
 2 files changed, 43 insertions(+), 2 deletions(-)
 mode change 100755 => 100644 library/axi_ad6676/axi_ad6676_ip.tcl

diff --git a/library/axi_ad6676/axi_ad6676_constr.xdc b/library/axi_ad6676/axi_ad6676_constr.xdc
index fd40910d9..84840755e 100644
--- a/library/axi_ad6676/axi_ad6676_constr.xdc
+++ b/library/axi_ad6676/axi_ad6676_constr.xdc
@@ -1,4 +1,45 @@
+set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
+set ad6676_clk [get_clocks -of_objects [get_ports rx_clk]]
 
+set_property ASYNC_REG TRUE \
+  [get_cells -hier *toggle_m1_reg*] \
+  [get_cells -hier *toggle_m2_reg*] \
+  [get_cells -hier *state_m1_reg*] \
+  [get_cells -hier *state_m2_reg*]
 
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $ad6676_clk]
 
+set_false_path \
+  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_false_path \
+  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
+set_max_delay -datapath_only \
+  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
+  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
+  [get_property PERIOD $up_clk]
+
+set_false_path \
+  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
 
diff --git a/library/axi_ad6676/axi_ad6676_ip.tcl b/library/axi_ad6676/axi_ad6676_ip.tcl
old mode 100755
new mode 100644
index 9908fb394..b2eea1af2
--- a/library/axi_ad6676/axi_ad6676_ip.tcl
+++ b/library/axi_ad6676/axi_ad6676_ip.tcl
@@ -18,8 +18,8 @@ adi_ip_files axi_ad6676 [list \
   "axi_ad6676_pnmon.v" \
   "axi_ad6676_channel.v" \
   "axi_ad6676_if.v" \
-  "axi_ad6676.v" \
-  "axi_ad6676_constr.xdc" ]
+  "axi_ad6676_constr.xdc" \
+  "axi_ad6676.v" ]
 
 adi_ip_properties axi_ad6676
 adi_ip_constraints axi_ad6676 [list \