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util_axis_fifo: Switch to Verilog-2001 style parameter declaration 

Verilog-2001 style module parameter declaration is the preferred coding
style for this repository.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-31 13:11:23 +02:00
parent 95d530e7c9
commit 68c48d9bd4
4 changed files with 15 additions and 13 deletions
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6
library/util_axis_fifo/address_gray.v
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@ -33,7 +33,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
module fifo_address_gray ( module fifo_address_gray #(
parameter ADDRESS_WIDTH = 4
) (
input m_axis_aclk, input m_axis_aclk,
input m_axis_aresetn, input m_axis_aresetn,
input m_axis_ready, input m_axis_ready,
@ -49,8 +51,6 @@ module fifo_address_gray (
output reg [ADDRESS_WIDTH:0] s_axis_room output reg [ADDRESS_WIDTH:0] s_axis_room
); );
parameter ADDRESS_WIDTH = 4;
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;

6
library/util_axis_fifo/address_gray_pipelined.v
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@ -33,7 +33,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
module fifo_address_gray_pipelined ( module fifo_address_gray_pipelined #(
parameter ADDRESS_WIDTH = 4
) (
input m_axis_aclk, input m_axis_aclk,
input m_axis_aresetn, input m_axis_aresetn,
input m_axis_ready, input m_axis_ready,
@ -50,8 +52,6 @@ module fifo_address_gray_pipelined (
output reg [ADDRESS_WIDTH:0] s_axis_room output reg [ADDRESS_WIDTH:0] s_axis_room
); );
parameter ADDRESS_WIDTH = 4;
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [ADDRESS_WIDTH:0] _s_axis_raddr; wire [ADDRESS_WIDTH:0] _s_axis_raddr;

4
library/util_axis_fifo/address_sync.v
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@ -33,7 +33,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
module fifo_address_sync ( module fifo_address_sync #(
parameter ADDRESS_WIDTH = 4
) (
input clk, input clk,
input resetn, input resetn,

12
library/util_axis_fifo/util_axis_fifo.v
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@ -33,7 +33,12 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
module util_axis_fifo ( module util_axis_fifo #(
parameter DATA_WIDTH = 64,
parameter ASYNC_CLK = 1,
parameter ADDRESS_WIDTH = 4,
parameter S_AXIS_REGISTERED = 1
) (
input m_axis_aclk, input m_axis_aclk,
input m_axis_aresetn, input m_axis_aresetn,
input m_axis_ready, input m_axis_ready,
@ -50,11 +55,6 @@ module util_axis_fifo (
output [ADDRESS_WIDTH:0] s_axis_room output [ADDRESS_WIDTH:0] s_axis_room
); );
parameter DATA_WIDTH = 64;
parameter ASYNC_CLK = 1;
parameter ADDRESS_WIDTH = 4;
parameter S_AXIS_REGISTERED = 1;
generate if (ADDRESS_WIDTH == 0) begin generate if (ADDRESS_WIDTH == 0) begin
reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;