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avl_dacfifo: Fix reset of write address register 

Fix the reset of the dma_mem_waddr (write address register of the CDC
FIFO on DMA's clock domain). This solves the occasional invalid read backs after
multiple re-initialization of the PL_DDR_FIFO.
main
Istvan Csomortani 2017-11-01 12:03:07 +00:00
parent f692d7bc40
commit 6895915076
1 changed files with 11 additions and 5 deletions
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12
library/altera/avl_dacfifo/avl_dacfifo_wr.v
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@ -192,19 +192,25 @@ module avl_dacfifo_wr #(
assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req_lp; assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req_lp;
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
if (dma_fifo_reset_s == 1'b1) begin if ((dma_fifo_reset_s == 1'b1) || (dma_avl_xfer_req_out == 1'b1)) begin
dma_mem_waddr <= 0; dma_mem_waddr <= 0;
dma_mem_waddr_g <= 0; dma_mem_waddr_g <= 0;
dma_last_beats <= 0;
end else begin end else begin
if (dma_mem_wea_s == 1'b1) begin if (dma_mem_wea_s == 1'b1) begin
dma_mem_waddr <= dma_mem_waddr + 1'b1; dma_mem_waddr <= dma_mem_waddr + 1'b1;
end end
end end
dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
end
always @(posedge dma_clk) begin
if (dma_fifo_reset_s == 1'b1) begin
dma_last_beats <= 0;
end else begin
if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s == 1'b1)) begin if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s == 1'b1)) begin
dma_last_beats <= dma_mem_waddr[MEM_WIDTH_DIFF-1:0]; dma_last_beats <= dma_mem_waddr[MEM_WIDTH_DIFF-1:0];
end end
dma_mem_waddr_g <= dma_mem_waddr_b2g_s; end
end end
ad_b2g # ( ad_b2g # (