From 68959150769dce848dd36babfe00a07bc15aac36 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 1 Nov 2017 12:03:07 +0000 Subject: [PATCH] avl_dacfifo: Fix reset of write address register Fix the reset of the dma_mem_waddr (write address register of the CDC FIFO on DMA's clock domain). This solves the occasional invalid read backs after multiple re-initialization of the PL_DDR_FIFO. --- library/altera/avl_dacfifo/avl_dacfifo_wr.v | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/library/altera/avl_dacfifo/avl_dacfifo_wr.v b/library/altera/avl_dacfifo/avl_dacfifo_wr.v index 57e950445..286266ffc 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_wr.v +++ b/library/altera/avl_dacfifo/avl_dacfifo_wr.v @@ -192,21 +192,27 @@ module avl_dacfifo_wr #( assign dma_mem_wea_s = dma_ready & dma_valid & dma_xfer_req_lp; always @(posedge dma_clk) begin - if (dma_fifo_reset_s == 1'b1) begin + if ((dma_fifo_reset_s == 1'b1) || (dma_avl_xfer_req_out == 1'b1)) begin dma_mem_waddr <= 0; dma_mem_waddr_g <= 0; - dma_last_beats <= 0; end else begin if (dma_mem_wea_s == 1'b1) begin dma_mem_waddr <= dma_mem_waddr + 1'b1; end end - if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s == 1'b1)) begin - dma_last_beats <= dma_mem_waddr[MEM_WIDTH_DIFF-1:0]; - end dma_mem_waddr_g <= dma_mem_waddr_b2g_s; end + always @(posedge dma_clk) begin + if (dma_fifo_reset_s == 1'b1) begin + dma_last_beats <= 0; + end else begin + if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s == 1'b1)) begin + dma_last_beats <= dma_mem_waddr[MEM_WIDTH_DIFF-1:0]; + end + end + end + ad_b2g # ( .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH) ) i_dma_mem_waddr_b2g (