From 68570c1815ee9d0332e69da52ecfdb5c219de609 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 8 May 2015 10:51:27 +0300
Subject: [PATCH] vc707: Common system mig, updated datawidth to 256 from 128

---
 projects/common/vc707/vc707_system_mig.prj | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/projects/common/vc707/vc707_system_mig.prj b/projects/common/vc707/vc707_system_mig.prj
index bcff50b10..d9e74f984 100644
--- a/projects/common/vc707/vc707_system_mig.prj
+++ b/projects/common/vc707/vc707_system_mig.prj
@@ -194,7 +194,7 @@
         <AXIParameters>
             <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
             <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
-            <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
+            <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
             <C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
             <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
         </AXIParameters>