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vc707: Common system mig, updated datawidth to 256 from 128

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Adrian Costina 2015-05-08 10:51:27 +03:00
parent 12ed393d39
commit 68570c1815
1 changed files with 1 additions and 1 deletions
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projects/common/vc707/vc707_system_mig.prj
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@ -194,7 +194,7 @@
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>3</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>