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ad9081_fmca_ebz: Add LANE_RATE param to all projects 

The block design expects a lane rate to be set in the system project.
main
Laszlo Nagy 2021-04-30 16:00:26 +01:00 committed by Laszlo Nagy
parent bd6ec360e2
commit 680d28476c
4 changed files with 22 additions and 18 deletions
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6
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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@ -4,6 +4,8 @@
# 64B66B - 64b66b link layer defined in JESD 204C
# 8B10B - 8b10b link layer defined in JESD 204B
#
# RX_LANE_RATE : Lane rate of the Rx link ( MxFE to FPGA )
# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample
@ -12,6 +14,8 @@
# Common parameter for TX and RX
set JESD_MODE $ad_project_params(JESD_MODE)
set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
set TX_LANE_RATE $ad_project_params(TX_LANE_RATE)
if {$JESD_MODE == "8B10B"} {
set DATAPATH_WIDTH 4
@ -111,6 +115,8 @@ ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
ad_ip_instance axi_adxcvr axi_mxfe_rx_xcvr
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.ID 0

14
projects/ad9081_fmca_ebz/vcu118/system_project.tcl
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@ -9,10 +9,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# Use over-writable parameters from the environment.
#
# e.g.
# make JESD_MODE=64B66B RX_JESD_L=4 TX_JESD_L=4
# make JESD_MODE=64B66B RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
# make JESD_MODE=64B66B RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16
# make JESD_MODE=64B66B RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 RX_JESD_L=4 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_NP=16
# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
# make JESD_MODE=64B66B RX_RATE=16.50 TX_RATE=16.50 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
# make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
#
@ -20,6 +21,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# JESD_MODE : Used link layer encoder mode
# 64B66B - 64b66b link layer defined in JESD 204C
# 8B10B - 8b10b link layer defined in JESD 204B
#
# RX_RATE : Lane rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Lane rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample
@ -28,6 +32,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9081_fmca_ebz_vcu118 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \

8
projects/ad9081_fmca_ebz/zc706/system_project.tcl
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@ -20,12 +20,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
# Encoding is:
# 0 - CPLL
# 1 - QPLL0
# 2 - QPLL1
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample
@ -37,6 +31,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9081_fmca_ebz_zc706 0 [list \
JESD_MODE 8B10B \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \

12
projects/ad9081_fmca_ebz/zcu102/system_project.tcl
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@ -18,14 +18,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer
# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode
# Encoding is:
# 0 - CPLL
# 1 - QPLL0
# 2 - QPLL1
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
@ -37,6 +31,8 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad9081_fmca_ebz_zcu102 0 [list \
JESD_MODE 8B10B \
RX_LANE_RATE [get_env_param RX_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \