From 67ffeb18e8d4ab6bdfdb63b23f985b2d48100ee8 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Fri, 11 Sep 2015 14:04:33 +0300
Subject: [PATCH] axi_ad9739a: Updated core with latest constraints

---
 library/axi_ad9739a/axi_ad9739a_constr.xdc | 43 ----------------------
 library/axi_ad9739a/axi_ad9739a_ip.tcl     |  2 +
 2 files changed, 2 insertions(+), 43 deletions(-)

diff --git a/library/axi_ad9739a/axi_ad9739a_constr.xdc b/library/axi_ad9739a/axi_ad9739a_constr.xdc
index 0a8c39b09..8b1378917 100644
--- a/library/axi_ad9739a/axi_ad9739a_constr.xdc
+++ b/library/axi_ad9739a/axi_ad9739a_constr.xdc
@@ -1,44 +1 @@
-set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
-set ad9739a_clk [get_clocks -of_objects [get_ports dac_div_clk]]
 
-set_property ASYNC_REG TRUE \
-  [get_cells -hier *toggle_m1_reg*] \
-  [get_cells -hier *toggle_m2_reg*] \
-  [get_cells -hier *state_m1_reg*] \
-  [get_cells -hier *state_m2_reg*]
-
-set_false_path \
-  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay \
-  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $ad9739a_clk]
-
-set_false_path \
-  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay \
-  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $up_clk]
-
-set_false_path \
-  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay \
-  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $up_clk]
-
-set_false_path \
-  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_ad9739a/axi_ad9739a_ip.tcl b/library/axi_ad9739a/axi_ad9739a_ip.tcl
index 0a3ddc4d2..49134339c 100644
--- a/library/axi_ad9739a/axi_ad9739a_ip.tcl
+++ b/library/axi_ad9739a/axi_ad9739a_ip.tcl
@@ -17,6 +17,7 @@ adi_ip_files axi_ad9739a [list \
   "$ad_hdl_dir/library/common/up_clock_mon.v" \
   "$ad_hdl_dir/library/common/up_dac_common.v" \
   "$ad_hdl_dir/library/common/up_dac_channel.v" \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9739a_channel.v" \
   "axi_ad9739a_core.v" \
   "axi_ad9739a_if.v" \
@@ -26,6 +27,7 @@ adi_ip_files axi_ad9739a [list \
 adi_ip_properties axi_ad9739a
 
 adi_ip_constraints axi_ad9739a [list \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9739a_constr.xdc" ]
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]