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fmcomms2/a10soc-- bad board design

main
Rejeesh Kutty 2016-06-14 12:29:36 -04:00
parent 7485d27d37
commit 67c948e821
5 changed files with 0 additions and 1045 deletions
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144
projects/fmcomms2/a10soc/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += system_bd.qsys
M_DEPS += ../common/fmcomms2_bd.qsys
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/a10soc/a10soc_system_bd.qsys
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_cmos_if.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_lvds_if.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_addsub.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dcfilter.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_iqcor.v
M_DEPS += ../../../library/common/ad_mul.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_tdd_control.v
M_DEPS += ../../../library/common/altera/DSP48E1.v
M_DEPS += ../../../library/common/altera/MULT_MACRO.v
M_DEPS += ../../../library/common/altera/ad_cmos_clk.v
M_DEPS += ../../../library/common/altera/ad_cmos_in.v
M_DEPS += ../../../library/common/altera/ad_cmos_out.v
M_DEPS += ../../../library/common/altera/ad_lvds_clk.v
M_DEPS += ../../../library/common/altera/ad_lvds_in.v
M_DEPS += ../../../library/common/altera/ad_lvds_out.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_delay_cntrl.v
M_DEPS += ../../../library/common/up_tdd_cntrl.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf
.PHONY: all clean clean-all
all: fmcomms2_a10soc.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
fmcomms2_a10soc.sof: $(M_DEPS)
rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> fmcomms2_a10soc_quartus.log 2>&1
####################################################################################
####################################################################################

500
projects/fmcomms2/a10soc/system_bd.qsys
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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element a10soc
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element a10soc.hps_s1_axi
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element fmcomms2
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element fmcomms2.axi_ad9361_s_axi
{
datum baseAddress
{
value = "0";
type = "String";
}
}
element fmcomms2.axi_dmac_adc_s_axi
{
datum baseAddress
{
value = "81920";
type = "String";
}
}
element fmcomms2.axi_dmac_dac_s_axi
{
datum baseAddress
{
value = "65536";
type = "String";
}
}
element sys_clk
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
element system_bd
{
datum _originalDeviceFamily
{
value = "Arria 10";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="FIFO" />
<parameter name="device" value="10AS066N3F40E2SGE2" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="2" />
<parameter name="projectName" value="fmcomms2_a10soc.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="ad9361_if"
internal="fmcomms2.axi_ad9361_device_if"
type="conduit"
dir="end" />
<interface
name="delay_clk"
internal="fmcomms2.axi_ad9361_delay_clk"
type="clock"
dir="end" />
<interface name="hps_ddr" internal="a10soc.hps_ddr" type="conduit" dir="end" />
<interface
name="hps_ddr_oct"
internal="a10soc.hps_ddr_oct"
type="conduit"
dir="end" />
<interface
name="hps_ddr_ref_clk"
internal="a10soc.hps_ddr_ref_clk"
type="clock"
dir="end" />
<interface name="hps_gpio" internal="a10soc.hps_gpio" type="conduit" dir="end" />
<interface name="hps_io" internal="a10soc.hps_io" type="conduit" dir="end" />
<interface name="hps_spi0" internal="a10soc.hps_spi0" type="conduit" dir="end" />
<interface
name="hps_spi0_sclk"
internal="a10soc.hps_spi0_sclk"
type="clock"
dir="start" />
<interface name="hps_spi1" internal="a10soc.hps_spi1" type="conduit" dir="end" />
<interface
name="hps_spi1_sclk"
internal="a10soc.hps_spi1_sclk"
type="clock"
dir="start" />
<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
<interface
name="sys_reset"
internal="sys_clk.clk_in_reset"
type="reset"
dir="end" />
<interface
name="up_enable"
internal="fmcomms2.axi_ad9361_up_enable"
type="conduit"
dir="end" />
<interface
name="up_txnrx"
internal="fmcomms2.axi_ad9361_up_txnrx"
type="conduit"
dir="end" />
<module name="a10soc" kind="a10soc_system_bd" version="1.0" enabled="1">
<parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_DOMAIN" value="2" />
<parameter name="AUTO_HPS_DDR_REF_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_HPS_DDR_REF_CLK_RESET_DOMAIN" value="2" />
<parameter name="AUTO_HPS_IRQ0_INTERRUPTS_USED" value="3" />
<parameter name="AUTO_HPS_IRQ1_INTERRUPTS_USED" value="3" />
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_MAP"><![CDATA[<address-map><slave name='fmcomms2_axi_ad9361.s_axi' start='0x0' end='0x10000' /><slave name='fmcomms2_axi_dmac_dac.s_axi' start='0x10000' end='0x14000' /><slave name='fmcomms2_axi_dmac_adc.s_axi' start='0x14000' end='0x18000' /></address-map>]]></parameter>
<parameter name="AUTO_SYS_CPU_M_AVL_ADDRESS_WIDTH" value="AddressWidth = 17" />
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_a10soc" />
</module>
<module name="fmcomms2" kind="fmcomms2_bd" version="1.0" enabled="1">
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
<parameter
name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
value="AddressWidth = 32" />
<parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='a10soc_arria10_hps_0_bridges.f2sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
<parameter
name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
value="AddressWidth = 32" />
<parameter name="AUTO_DEVICE" value="10AS066N3F40E2SGE2" />
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="5" />
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="100000000" />
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="5" />
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_fmcomms2</parameter>
</module>
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
<parameter name="clockFrequency" value="100000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<connection
kind="avalon"
version="15.1"
start="fmcomms2.axi_dmac_adc_m_dest_axi"
end="a10soc.hps_s1_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="fmcomms2.axi_dmac_dac_m_src_axi"
end="a10soc.hps_s1_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="a10soc.sys_cpu_m_avl"
end="fmcomms2.axi_ad9361_s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="a10soc.sys_cpu_m_avl"
end="fmcomms2.axi_dmac_adc_s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00014000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.1"
start="a10soc.sys_cpu_m_avl"
end="fmcomms2.axi_dmac_dac_s_axi">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="clock" version="15.1" start="sys_clk.clk" end="a10soc.sys_clk" />
<connection
kind="clock"
version="15.1"
start="sys_clk.clk"
end="fmcomms2.sys_clk" />
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq0"
end="fmcomms2.axi_dmac_adc_intr">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq0"
end="fmcomms2.axi_dmac_dac_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq1"
end="fmcomms2.axi_dmac_adc_intr">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="15.1"
start="a10soc.hps_irq1"
end="fmcomms2.axi_dmac_dac_intr">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="reset"
version="15.1"
start="sys_clk.clk_reset"
end="a10soc.sys_rst_in" />
<connection
kind="reset"
version="15.1"
start="a10soc.sys_rst"
end="fmcomms2.sys_rst" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
</system>

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projects/fmcomms2/a10soc/system_constr.sdc
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk_in}]
derive_pll_clocks
derive_clock_uncertainty

130
projects/fmcomms2/a10soc/system_project.tcl
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load_package flow
source ../../scripts/adi_env.tcl
project_new fmcomms2_a10soc -overwrite
source "../../common/a10soc/a10soc_system_assign.tcl"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# data-path
set_location_assignment PIN_G14 -to rx_clk_in ; ## G6 FMC_LPC_LA00_CC_P
set_location_assignment PIN_H14 -to "rx_clk_in(n)" ; ## G7 FMC_LPC_LA00_CC_N
set_location_assignment PIN_E12 -to rx_frame_in ; ## D8 FMC_LPC_LA01_CC_P
set_location_assignment PIN_E13 -to "rx_frame_in(n)" ; ## D9 FMC_LPC_LA01_CC_N
set_location_assignment PIN_C13 -to rx_data_in[0] ; ## H7 FMC_LPC_LA02_P
set_location_assignment PIN_D13 -to "rx_data_in[0](n)" ; ## H8 FMC_LPC_LA02_N
set_location_assignment PIN_C14 -to rx_data_in[1] ; ## G9 FMC_LPC_LA03_P
set_location_assignment PIN_D14 -to "rx_data_in[1](n)" ; ## G10 FMC_LPC_LA03_N
set_location_assignment PIN_H12 -to rx_data_in[2] ; ## H10 FMC_LPC_LA04_P
set_location_assignment PIN_H13 -to "rx_data_in[2](n)" ; ## H11 FMC_LPC_LA04_N
set_location_assignment PIN_F13 -to rx_data_in[3] ; ## D11 FMC_LPC_LA05_P
set_location_assignment PIN_F14 -to "rx_data_in[3](n)" ; ## D12 FMC_LPC_LA05_N
set_location_assignment PIN_A10 -to rx_data_in[4] ; ## C10 FMC_LPC_LA06_P
set_location_assignment PIN_B10 -to "rx_data_in[4](n)" ; ## C11 FMC_LPC_LA06_N
set_location_assignment PIN_A9 -to rx_data_in[5] ; ## H13 FMC_LPC_LA07_P
set_location_assignment PIN_B9 -to "rx_data_in[5](n)" ; ## H14 FMC_LPC_LA07_N
set_location_assignment PIN_B11 -to tx_clk_out ; ## G12 FMC_LPC_LA08_P
set_location_assignment PIN_B12 -to "tx_clk_out(n)" ; ## G13 FMC_LPC_LA08_N
set_location_assignment PIN_A12 -to tx_frame_out ; ## D14 FMC_LPC_LA09_P
set_location_assignment PIN_A13 -to "tx_frame_out(n)" ; ## D15 FMC_LPC_LA09_N
set_location_assignment PIN_C9 -to tx_data_out[0] ; ## H16 FMC_LPC_LA11_P
set_location_assignment PIN_D9 -to "tx_data_out[0](n)" ; ## H17 FMC_LPC_LA11_N
set_location_assignment PIN_M12 -to tx_data_out[1] ; ## G15 FMC_LPC_LA12_P
set_location_assignment PIN_N13 -to "tx_data_out[1](n)" ; ## G16 FMC_LPC_LA12_N
set_location_assignment PIN_J11 -to tx_data_out[2] ; ## D17 FMC_LPC_LA13_P
set_location_assignment PIN_K11 -to "tx_data_out[2](n)" ; ## D18 FMC_LPC_LA13_N
set_location_assignment PIN_A7 -to tx_data_out[3] ; ## C14 FMC_LPC_LA10_P
set_location_assignment PIN_A8 -to "tx_data_out[3](n)" ; ## C15 FMC_LPC_LA10_N
set_location_assignment PIN_J9 -to tx_data_out[4] ; ## C18 FMC_LPC_LA14_P
set_location_assignment PIN_J10 -to "tx_data_out[4](n)" ; ## C19 FMC_LPC_LA14_N
set_location_assignment PIN_D4 -to tx_data_out[5] ; ## H19 FMC_LPC_LA15_P
set_location_assignment PIN_D5 -to "tx_data_out[5](n)" ; ## H20 FMC_LPC_LA15_N
set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1]
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2]
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3]
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4]
set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5]
set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out
set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out
set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0]
set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1]
set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_clk_in
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_frame_in
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[0]
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[1]
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[2]
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[3]
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[4]
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_data_in[5]
# ensm/tdd control
set_location_assignment PIN_D6 -to enable ; ## G18 FMC_LPC_LA16_P
set_location_assignment PIN_E6 -to txnrx ; ## G19 FMC_LPC_LA16_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx
# control & status
set_location_assignment PIN_C3 -to gpio_status[0] ; ## G21 FMC_LPC_LA20_P
set_location_assignment PIN_C4 -to gpio_status[1] ; ## G22 FMC_LPC_LA20_N
set_location_assignment PIN_C2 -to gpio_status[2] ; ## H25 FMC_LPC_LA21_P
set_location_assignment PIN_D3 -to gpio_status[3] ; ## H26 FMC_LPC_LA21_N
set_location_assignment PIN_F4 -to gpio_status[4] ; ## G24 FMC_LPC_LA22_P
set_location_assignment PIN_G4 -to gpio_status[5] ; ## G25 FMC_LPC_LA22_N
set_location_assignment PIN_C1 -to gpio_status[6] ; ## D23 FMC_LPC_LA23_P
set_location_assignment PIN_D1 -to gpio_status[7] ; ## D24 FMC_LPC_LA23_N
set_location_assignment PIN_E1 -to gpio_ctl[0] ; ## H28 FMC_LPC_LA24_P
set_location_assignment PIN_E2 -to gpio_ctl[1] ; ## H29 FMC_LPC_LA24_N
set_location_assignment PIN_E3 -to gpio_ctl[2] ; ## G27 FMC_LPC_LA25_P
set_location_assignment PIN_F3 -to gpio_ctl[3] ; ## G28 FMC_LPC_LA25_N
set_location_assignment PIN_G5 -to gpio_en_agc ; ## H22 FMC_LPC_LA19_P
set_location_assignment PIN_G6 -to gpio_sync ; ## H23 FMC_LPC_LA19_N
set_location_assignment PIN_L5 -to gpio_resetb ; ## H31 FMC_LPC_LA28_P
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync
set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb
# spi
set_location_assignment PIN_F2 -to spi_csn ; ## D26 FMC_LPC_LA26_P
set_location_assignment PIN_G2 -to spi_clk ; ## D27 FMC_LPC_LA26_N
set_location_assignment PIN_G1 -to spi_mosi ; ## C26 FMC_LPC_LA27_P
set_location_assignment PIN_H2 -to spi_miso ; ## C27 FMC_LPC_LA27_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
execute_flow -compile

264
projects/fmcomms2/a10soc/system_top.v
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@ -1,264 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
input sys_resetn,
// hps-ddr4 (32)
input hps_ddr_ref_clk,
output [ 0:0] hps_ddr_clk_p,
output [ 0:0] hps_ddr_clk_n,
output [ 16:0] hsp_ddr_a,
output [ 1:0] hps_ddr_ba,
output [ 0:0] hps_ddr_bg,
output [ 0:0] hps_ddr_cke,
output [ 0:0] hps_ddr_cs_n,
output [ 0:0] hps_ddr_odt,
output [ 0:0] hps_ddr_reset_n,
output [ 0:0] hps_ddr_act_n,
output [ 0:0] hps_ddr_par,
input [ 0:0] hps_ddr_alert_n,
inout [ 3:0] hps_ddr_dqs_p,
inout [ 3:0] hps_ddr_dqs_n,
inout [ 31:0] hps_ddr_dq,
inout [ 3:0] hps_ddr_dbi_n,
input hps_ddr_rzq,
// hps-ethernet
input [ 0:0] hps_eth_rxclk,
input [ 0:0] hps_eth_rxctl,
input [ 3:0] hps_eth_rxd,
output [ 0:0] hps_eth_txclk,
output [ 0:0] hps_eth_txctl,
output [ 3:0] hps_eth_txd,
output [ 0:0] hps_eth_mdc,
inout [ 0:0] hps_eth_mdio,
// hps-sdio
output [ 0:0] hps_sdio_clk,
inout [ 0:0] hps_sdio_cmd,
inout [ 7:0] hps_sdio_d,
// hps-usb
input [ 0:0] hps_usb_clk,
input [ 0:0] hps_usb_dir,
input [ 0:0] hps_usb_nxt,
output [ 0:0] hps_usb_stp,
inout [ 7:0] hps_usb_d,
// hps-uart
input [ 0:0] hps_uart_rx,
output [ 0:0] hps_uart_tx,
// hps-i2c (shared w fmc-a, fmc-b)
inout [ 0:0] hps_i2c_sda,
inout [ 0:0] hps_i2c_scl,
// hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio,
// gpio (max-v-u21)
input [ 7:0] gpio_bd_i,
output [ 3:0] gpio_bd_o,
// ad9361-interface
input rx_clk_in,
input rx_frame_in,
input [ 5:0] rx_data_in,
output tx_clk_out,
output tx_frame_out,
output [ 5:0] tx_data_out,
output enable,
output txnrx,
output gpio_resetb,
output gpio_sync,
output gpio_en_agc,
output [ 3:0] gpio_ctl,
input [ 7:0] gpio_status,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire [ 31:0] gpio_i;
wire [ 31:0] gpio_o;
// gpio (ad9361)
assign gpio_i[31:24] = gpio_o[31:24];
assign gpio_i[23:16] = gpio_status;
assign gpio_resetb = gpio_o[22];
assign gpio_sync = gpio_o[21];
assign gpio_en_agc = gpio_o[20];
assign gpio_ctl = gpio_o[19:16];
// gpio (max-v-u21)
assign gpio_i[15:8] = gpio_o[15:8];
assign gpio_i[ 7:0] = gpio_bd_i;
assign gpio_bd_o = gpio_o[3:0];
// instantiations
system_bd i_system_bd (
.ad9361_if_rx_clk_in_p (rx_clk_in),
.ad9361_if_rx_clk_in_n (1'b0),
.ad9361_if_rx_frame_in_p (rx_frame_in),
.ad9361_if_rx_frame_in_n (1'b0),
.ad9361_if_rx_data_in_p (rx_data_in),
.ad9361_if_rx_data_in_n (6'd0),
.ad9361_if_tx_clk_out_p (tx_clk_out),
.ad9361_if_tx_clk_out_n (),
.ad9361_if_tx_frame_out_p (tx_frame_out),
.ad9361_if_tx_frame_out_n (),
.ad9361_if_tx_data_out_p (tx_data_out),
.ad9361_if_tx_data_out_n (),
.ad9361_if_enable (enable),
.ad9361_if_txnrx (txnrx),
.delay_clk_clk (1'b0),
.hps_ddr_mem_ck (hps_ddr_clk_p),
.hps_ddr_mem_ck_n (hps_ddr_clk_n),
.hps_ddr_mem_a (hsp_ddr_a),
.hps_ddr_mem_act_n (hps_ddr_act_n),
.hps_ddr_mem_ba (hps_ddr_ba),
.hps_ddr_mem_bg (hps_ddr_bg),
.hps_ddr_mem_cke (hps_ddr_cke),
.hps_ddr_mem_cs_n (hps_ddr_cs_n),
.hps_ddr_mem_odt (hps_ddr_odt),
.hps_ddr_mem_reset_n (hps_ddr_reset_n),
.hps_ddr_mem_par (hps_ddr_par),
.hps_ddr_mem_alert_n (hps_ddr_alert_n),
.hps_ddr_mem_dqs (hps_ddr_dqs_p),
.hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
.hps_ddr_mem_dq (hps_ddr_dq),
.hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
.hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
.hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
.hps_gpio_gp_in (gpio_i),
.hps_gpio_gp_out (gpio_o),
.hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
.hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
.hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
.hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
.hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
.hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
.hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
.hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
.hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
.hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
.hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
.hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
.hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
.hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
.hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
.hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
.hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
.hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
.hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
.hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
.hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
.hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
.hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
.hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
.hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
.hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
.hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
.hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
.hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
.hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
.hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
.hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
.hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
.hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
.hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
.hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
.hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
.hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
.hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
.hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
.hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
.hps_spi0_mosi_o (spi_mosi),
.hps_spi0_miso_i (spi_miso),
.hps_spi0_ss_in_n (1'b1),
.hps_spi0_mosi_oe (),
.hps_spi0_ss0_n_o (spi_csn),
.hps_spi0_ss1_n_o (),
.hps_spi0_ss2_n_o (),
.hps_spi0_ss3_n_o (),
.hps_spi0_sclk_clk (spi_clk),
.hps_spi1_mosi_o (),
.hps_spi1_miso_i (1'b0),
.hps_spi1_ss_in_n (1'b1),
.hps_spi1_mosi_oe (),
.hps_spi1_ss0_n_o (),
.hps_spi1_ss1_n_o (),
.hps_spi1_ss2_n_o (),
.hps_spi1_ss3_n_o (),
.hps_spi1_sclk_clk (),
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.up_enable_up_enable (gpio_o[23]),
.up_txnrx_up_txnrx (gpio_o[24]));
endmodule
// ***************************************************************************
// ***************************************************************************