adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
Set the same inter clock skew characteristics as used in LVDS mode. The physical lanes/routes are common on both modes.main
parent
03de08609b
commit
677c154134
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@ -47,8 +47,10 @@ create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_in_p]
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create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_in_p]
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create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_in_p]
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set_clock_latency -source -early 2 [get_clocks rx1_dclk_out]
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set_clock_latency -source -early 2 [get_clocks rx2_dclk_out]
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set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out]
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set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out]
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set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out]
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set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out]
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set_clock_latency -source -late 5 [get_clocks rx1_dclk_out]
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set_clock_latency -source -late 5 [get_clocks rx2_dclk_out]
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