adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings

Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
main
Laszlo Nagy 2021-02-16 12:50:09 +00:00 committed by Laszlo Nagy
parent 03de08609b
commit 677c154134
1 changed files with 6 additions and 4 deletions

View File

@ -47,8 +47,10 @@ create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_in_p]
create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_in_p]
create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_in_p]
set_clock_latency -source -early 2 [get_clocks rx1_dclk_out]
set_clock_latency -source -early 2 [get_clocks rx2_dclk_out]
set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out]
set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out]
set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out]
set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out]
set_clock_latency -source -late 5 [get_clocks rx1_dclk_out]
set_clock_latency -source -late 5 [get_clocks rx2_dclk_out]