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ad9680_eval: removed

main
Rejeesh Kutty 2014-11-24 11:04:34 -05:00
parent 76fb5d3da9
commit 67065a3130
6 changed files with 0 additions and 596 deletions
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188
projects/ad9680_eval/common/ad9680_eval_bd.tcl
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# ad9680
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_csn_o [create_bd_port -dir O spi_csn_o]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
set rx_sync [create_bd_port -dir O rx_sync]
set rx_sysref [create_bd_port -dir O rx_sysref]
set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n]
# adc peripherals
set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core]
set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma
set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect
# dac/adc common gt/gpio
set axi_ad9680_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9680_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_ad9680_gt
set axi_ad9680_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_gt_interconnect
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
# connections (spi and gpio)
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
# connections (gt)
connect_bd_net -net axi_ad9680_gt_ref_clk_q [get_bd_pins axi_ad9680_gt/ref_clk_q] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_ad9680_gt_rx_data_p [get_bd_pins axi_ad9680_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_ad9680_gt_rx_data_n [get_bd_pins axi_ad9680_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_ad9680_gt_rx_sync [get_bd_pins axi_ad9680_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_ad9680_gt_rx_sysref [get_bd_pins axi_ad9680_gt/rx_sysref] [get_bd_ports rx_sysref]
# connections (adc)
connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins axi_ad9680_gt/rx_clk]
connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk]
connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk]
connect_bd_net -net axi_ad9680_gt_rx_rst [get_bd_pins axi_ad9680_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset]
connect_bd_net -net axi_ad9680_gt_rx_sysref [get_bd_pins axi_ad9680_jesd/rx_sysref]
connect_bd_net -net axi_ad9680_gt_rx_gt_charisk [get_bd_pins axi_ad9680_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9680_gt_rx_gt_disperr [get_bd_pins axi_ad9680_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9680_gt_rx_gt_notintable [get_bd_pins axi_ad9680_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9680_gt_rx_gt_data [get_bd_pins axi_ad9680_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9680_gt_rx_rst_done [get_bd_pins axi_ad9680_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done]
connect_bd_net -net axi_ad9680_gt_rx_ip_comma_align [get_bd_pins axi_ad9680_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9680_gt_rx_ip_sync [get_bd_pins axi_ad9680_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync]
connect_bd_net -net axi_ad9680_gt_rx_ip_sof [get_bd_pins axi_ad9680_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9680_gt_rx_ip_data [get_bd_pins axi_ad9680_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata]
connect_bd_net -net axi_ad9680_gt_rx_data [get_bd_pins axi_ad9680_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data]
connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9680_adc_dwr [get_bd_pins axi_ad9680_core/adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en]
connect_bd_net -net axi_ad9680_adc_dsync [get_bd_pins axi_ad9680_core/adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins axi_ad9680_core/adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din]
connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_gt/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn]
# gt uses hp3, and 100MHz clock for both DRP and AXI4
connect_bd_intf_net -intf_net axi_ad9680_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_intf_net -intf_net axi_ad9680_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_gt/m_axi_aresetn]
# memory interconnects share the same clock (fclk2)
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
# interconnect (mem/dac)
connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn]
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon
connect_bd_net -net axi_ad9680_gt_rx_mon_data [get_bd_pins axi_ad9680_gt/rx_mon_data]
connect_bd_net -net axi_ad9680_gt_rx_mon_trigger [get_bd_pins axi_ad9680_gt/rx_mon_trigger]
connect_bd_net -net axi_ad9680_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_ad9680_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_ad9680_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_ad9680_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_gt/s_axi/axi_lite] SEG_data_ad9680_gt
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm

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projects/ad9680_eval/common/ad9680_eval_spi.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9680_eval_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************

4
projects/ad9680_eval/zc706/system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad9680_eval_bd.tcl

39
projects/ad9680_eval/zc706/system_constr.xdc
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# ad9680
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A6 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A7 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C6 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C7 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A2 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A3 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D8 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H7 FMC_HPC_LA02_P
# clocks
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_ad9680_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9680_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

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projects/ad9680_eval/zc706/system_project.tcl
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@ -1,16 +0,0 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create ad9680_eval_zc706
adi_project_files ad9680_eval_zc706 [list \
"system_top.v" \
"../common/ad9680_eval_spi.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run ad9680_eval_zc706

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projects/ad9680_eval/zc706/system_top.v
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@ -1,240 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
spi_csn,
spi_clk,
spi_sdio);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 3:0] rx_data_p;
input [ 3:0] rx_data_n;
output spi_csn;
output spi_clk;
inout spi_sdio;
// internal signals
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire spi_mosi;
wire spi_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (1'b0),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
genvar n;
generate
for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
ad9680_eval_spi i_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************