From 66c6b2b18237d02d64c6e62f365f61d5339bd3b4 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 11 Mar 2014 20:04:26 -0400 Subject: [PATCH] fmcomms2: added --- projects/fmcomms2/common/fmcomms2_bd.tcl | 172 ++++++++++++ projects/fmcomms2/zc706/system_bd.tcl | 4 + projects/fmcomms2/zc706/system_constr.xdc | 69 +++++ projects/fmcomms2/zc706/system_project.tcl | 15 ++ projects/fmcomms2/zc706/system_top.v | 287 +++++++++++++++++++++ 5 files changed, 547 insertions(+) create mode 100755 projects/fmcomms2/common/fmcomms2_bd.tcl create mode 100755 projects/fmcomms2/zc706/system_bd.tcl create mode 100755 projects/fmcomms2/zc706/system_constr.xdc create mode 100755 projects/fmcomms2/zc706/system_project.tcl create mode 100755 projects/fmcomms2/zc706/system_top.v diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl new file mode 100755 index 000000000..b374bd013 --- /dev/null +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -0,0 +1,172 @@ + +# fmcomms2 + +set spi_csn_i [create_bd_port -dir I spi_csn_i] +set spi_csn_o [create_bd_port -dir O spi_csn_o] +set spi_sclk_i [create_bd_port -dir I spi_sclk_i] +set spi_sclk_o [create_bd_port -dir O spi_sclk_o] +set spi_mosi_i [create_bd_port -dir I spi_mosi_i] +set spi_mosi_o [create_bd_port -dir O spi_mosi_o] +set spi_miso_i [create_bd_port -dir I spi_miso_i] + +set rx_clk_in_p [create_bd_port -dir I rx_clk_in_p] +set rx_clk_in_n [create_bd_port -dir I rx_clk_in_n] +set rx_frame_in_p [create_bd_port -dir I rx_frame_in_p] +set rx_frame_in_n [create_bd_port -dir I rx_frame_in_n] +set rx_data_in_p [create_bd_port -dir I -from 5 -to 0 rx_data_in_p] +set rx_data_in_n [create_bd_port -dir I -from 5 -to 0 rx_data_in_n] + +set tx_clk_out_p [create_bd_port -dir O tx_clk_out_p] +set tx_clk_out_n [create_bd_port -dir O tx_clk_out_n] +set tx_frame_out_p [create_bd_port -dir O tx_frame_out_p] +set tx_frame_out_n [create_bd_port -dir O tx_frame_out_n] +set tx_data_out_p [create_bd_port -dir O -from 5 -to 0 tx_data_out_p] +set tx_data_out_n [create_bd_port -dir O -from 5 -to 0 tx_data_out_n] + +# ad9361 core + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma + +set axi_ad9361_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_dac_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_dac_dma_interconnect + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma + +set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_adc_dma_interconnect + +# additions to default configuration + +set_property -dict [list CONFIG.NUM_MI {10}] $axi_cpu_interconnect +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {49}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + +set_property LEFT 48 [get_bd_ports GPIO_I] +set_property LEFT 48 [get_bd_ports GPIO_O] +set_property LEFT 48 [get_bd_ports GPIO_T] + +# connections (spi) + +connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/spi_csn_i] +connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/spi_csn_o] +connect_bd_net -net spi_sclk_i [get_bd_ports spi_sclk_i] [get_bd_pins sys_ps7/spi_sclk_i] +connect_bd_net -net spi_sclk_o [get_bd_ports spi_sclk_o] [get_bd_pins sys_ps7/spi_sclk_o] +connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/spi_mosi_i] +connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/spi_mosi_o] +connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/spi_miso_i] + +# connections (ad9361) + +connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361/delay_clk] +connect_bd_net -net axi_ad9361_clk [get_bd_pins axi_ad9361/clk] +connect_bd_net -net axi_ad9361_clk [get_bd_pins axi_ad9361_adc_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9361_clk [get_bd_pins axi_ad9361_dac_dma/fifo_rd_clk] + +connect_bd_net -net axi_ad9361_rx_clk_in_p [get_bd_ports rx_clk_in_p] [get_bd_pins axi_ad9361/rx_clk_in_p] +connect_bd_net -net axi_ad9361_rx_clk_in_n [get_bd_ports rx_clk_in_n] [get_bd_pins axi_ad9361/rx_clk_in_n] +connect_bd_net -net axi_ad9361_rx_frame_in_p [get_bd_ports rx_frame_in_p] [get_bd_pins axi_ad9361/rx_frame_in_p] +connect_bd_net -net axi_ad9361_rx_frame_in_n [get_bd_ports rx_frame_in_n] [get_bd_pins axi_ad9361/rx_frame_in_n] +connect_bd_net -net axi_ad9361_rx_data_in_p [get_bd_ports rx_data_in_p] [get_bd_pins axi_ad9361/rx_data_in_p] +connect_bd_net -net axi_ad9361_rx_data_in_n [get_bd_ports rx_data_in_n] [get_bd_pins axi_ad9361/rx_data_in_n] +connect_bd_net -net axi_ad9361_tx_clk_out_p [get_bd_ports tx_clk_out_p] [get_bd_pins axi_ad9361/tx_clk_out_p] +connect_bd_net -net axi_ad9361_tx_clk_out_n [get_bd_ports tx_clk_out_n] [get_bd_pins axi_ad9361/tx_clk_out_n] +connect_bd_net -net axi_ad9361_tx_frame_out_p [get_bd_ports tx_frame_out_p] [get_bd_pins axi_ad9361/tx_frame_out_p] +connect_bd_net -net axi_ad9361_tx_frame_out_n [get_bd_ports tx_frame_out_n] [get_bd_pins axi_ad9361/tx_frame_out_n] +connect_bd_net -net axi_ad9361_tx_data_out_p [get_bd_ports tx_data_out_p] [get_bd_pins axi_ad9361/tx_data_out_p] +connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n] +connect_bd_net -net axi_ad9361_adc_dwr [get_bd_pins axi_ad9361/adc_dwr] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en] +connect_bd_net -net axi_ad9361_adc_dsync [get_bd_pins axi_ad9361/adc_dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins axi_ad9361/adc_ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din] +connect_bd_net -net axi_ad9361_adc_dovf [get_bd_pins axi_ad9361/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins axi_ad9361/dac_drd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] +connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins axi_ad9361/dac_ddata] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] +connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] +connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3] + +# interconnect (cpu) + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9361/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/s_axi] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_adc_dma/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_dac_dma/s_axi_aclk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/s_axi_aresetn] + +# memory interconnects share the same clock (fclk2) + +set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] +set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N] + +connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source + +# interconnect (mem/dac) + +connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] +connect_bd_intf_net -intf_net axi_ad9361_dac_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_dac_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi] +connect_bd_intf_net -intf_net axi_ad9361_dac_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_dac_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aclk] +connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn] + +# ila (adc) + +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc] +set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc +set_property -dict [list CONFIG.C_PROBE1_WIDTH {48}] $ila_adc +set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc + +connect_bd_net -net axi_ad9361_clk [get_bd_pins ila_adc/clk] +connect_bd_net -net axi_ad9361_adc_mon_valid [get_bd_pins axi_ad9361/adc_mon_valid] [get_bd_pins ila_0/probe0] +connect_bd_net -net axi_ad9361_adc_mon_data [get_bd_pins axi_ad9361/adc_mon_data] [get_bd_pins ila_0/probe1] + +# address map + +create_bd_addr_seg -range 0x00010000 -offset 0x79020000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9361/s_axi/axi_lite] SEG_data_ad9361 +create_bd_addr_seg -range 0x00010000 -offset 0x7C400000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9361_dac_dma/s_axi/axi_lite] SEG_data_ad9361_dac_dma +create_bd_addr_seg -range 0x00010000 -offset 0x7C420000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9361_adc_dma/s_axi/axi_lite] SEG_data_ad9361_adc_dma + +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm diff --git a/projects/fmcomms2/zc706/system_bd.tcl b/projects/fmcomms2/zc706/system_bd.tcl new file mode 100755 index 000000000..0028343e5 --- /dev/null +++ b/projects/fmcomms2/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/fmcomms2_bd.tcl + diff --git a/projects/fmcomms2/zc706/system_constr.xdc b/projects/fmcomms2/zc706/system_constr.xdc new file mode 100755 index 000000000..fa4b42a62 --- /dev/null +++ b/projects/fmcomms2/zc706/system_constr.xdc @@ -0,0 +1,69 @@ + +# constraints +# ad9361 + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N + +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N + +# clocks + +create_clock -name rx_clk -period 8.00 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] + +set_clock_groups -asynchronous -group {ad9361_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + diff --git a/projects/fmcomms2/zc706/system_project.tcl b/projects/fmcomms2/zc706/system_project.tcl new file mode 100755 index 000000000..fc5724d59 --- /dev/null +++ b/projects/fmcomms2/zc706/system_project.tcl @@ -0,0 +1,15 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create fmcomms2_zc706 +adi_project_files fmcomms2_zc706 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run fmcomms2_zc706 + + diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v new file mode 100755 index 000000000..abb4e5179 --- /dev/null +++ b/projects/fmcomms2/zc706/system_top.v @@ -0,0 +1,287 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + inout gpio_txnrx; + inout gpio_enable; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [48:0] gpio_i; + wire [48:0] gpio_o; + wire [48:0] gpio_t; + + // instantiations + + IOBUF i_iobuf_gpio_txnrx ( + .I (gpio_o[48]), + .O (gpio_i[48]), + .T (gpio_t[48]), + .IO (gpio_txnrx)); + + IOBUF i_iobuf_gpio_enable ( + .I (gpio_o[47]), + .O (gpio_i[47]), + .T (gpio_t[47]), + .IO (gpio_enable)); + + IOBUF i_iobuf_gpio_resetb ( + .I (gpio_o[46]), + .O (gpio_i[46]), + .T (gpio_t[46]), + .IO (gpio_resetb)); + + IOBUF i_iobuf_gpio_sync ( + .I (gpio_o[45]), + .O (gpio_i[45]), + .T (gpio_t[45]), + .IO (gpio_sync)); + + IOBUF i_iobuf_gpio_en_agc ( + .I (gpio_o[44]), + .O (gpio_i[44]), + .T (gpio_t[44]), + .IO (gpio_en_agc)); + + genvar n; + generate + for (n = 0; n <= 3; n = n + 1) begin: g_iobuf_gpio_ctl + IOBUF i_iobuf_gpio_ctl ( + .I (gpio_o[40+n]), + .O (gpio_i[40+n]), + .T (gpio_t[40+n]), + .IO (gpio_ctl[n])); + end + for (n = 0; n <= 7; n = n + 1) begin: g_iobuf_gpio_status + IOBUF i_iobuf_gpio_status ( + .I (gpio_o[32+n]), + .O (gpio_i[32+n]), + .T (gpio_t[32+n]), + .IO (gpio_status[n])); + end + for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_miso_i (spi_miso), + .spi_mosi_i (1'b0), + .spi_mosi_o (spi_mosi), + .spi_sclk_i (1'b0), + .spi_sclk_o (spi_clk), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p)); + +endmodule + +// *************************************************************************** +// ***************************************************************************