fmcomms2/a10gx: Remove project
Istvan Csomortani
parent
3c47d00a96
commit
669e0a01d0
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@ -1,159 +0,0 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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ifeq ($(NIOS2_MMU),)
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NIOS2_MMU := 1
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endif
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export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU)
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M_DEPS += system_top.v
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M_DEPS += system_qsys.tcl
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.sdc
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M_DEPS += ../common/fmcomms2_qsys.tcl
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M_DEPS += ../../scripts/adi_tquest.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../common/altera/sys_gen.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
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M_DEPS += ../../../library/altera/common/ad_cmos_out_core_c5.v
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M_DEPS += ../../../library/altera/common/ad_dcfilter.v
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M_DEPS += ../../../library/altera/common/ad_mul.v
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M_DEPS += ../../../library/altera/common/ad_serdes_in_core_c5.v
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M_DEPS += ../../../library/altera/common/ad_serdes_out_core_c5.v
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M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
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M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
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M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
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M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
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M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_cmos_if.v
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M_DEPS += ../../../library/axi_ad9361/altera/axi_ad9361_lvds_if.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_constr.sdc
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_hw.tcl
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_channel.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_rx_pnmon.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tdd_if.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361_tx_channel.v
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M_DEPS += ../../../library/axi_dmac/2d_transfer.v
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M_DEPS += ../../../library/axi_dmac/address_generator.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
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M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
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M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
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M_DEPS += ../../../library/axi_dmac/data_mover.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
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M_DEPS += ../../../library/axi_dmac/inc_id.h
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M_DEPS += ../../../library/axi_dmac/request_arb.v
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M_DEPS += ../../../library/axi_dmac/request_generator.v
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M_DEPS += ../../../library/axi_dmac/resp.h
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M_DEPS += ../../../library/axi_dmac/response_generator.v
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M_DEPS += ../../../library/axi_dmac/response_handler.v
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M_DEPS += ../../../library/axi_dmac/splitter.v
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M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
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M_DEPS += ../../../library/common/ad_addsub.v
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M_DEPS += ../../../library/common/ad_datafmt.v
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M_DEPS += ../../../library/common/ad_dds.v
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M_DEPS += ../../../library/common/ad_dds_1.v
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M_DEPS += ../../../library/common/ad_dds_sine.v
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M_DEPS += ../../../library/common/ad_iqcor.v
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M_DEPS += ../../../library/common/ad_mem.v
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M_DEPS += ../../../library/common/ad_pnmon.v
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M_DEPS += ../../../library/common/ad_rst.v
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M_DEPS += ../../../library/common/ad_tdd_control.v
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M_DEPS += ../../../library/common/sync_bits.v
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M_DEPS += ../../../library/common/sync_gray.v
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M_DEPS += ../../../library/common/up_adc_channel.v
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M_DEPS += ../../../library/common/up_adc_common.v
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M_DEPS += ../../../library/common/up_axi.v
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M_DEPS += ../../../library/common/up_clock_mon.v
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M_DEPS += ../../../library/common/up_dac_channel.v
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M_DEPS += ../../../library/common/up_dac_common.v
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M_DEPS += ../../../library/common/up_delay_cntrl.v
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M_DEPS += ../../../library/common/up_tdd_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_status.v
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M_DEPS += ../../../library/scripts/adi_env.tcl
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M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
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M_DEPS += ../../../library/util_axis_fifo/address_gray.v
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M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
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M_DEPS += ../../../library/util_axis_fifo/address_sync.v
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M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
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M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
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M_DEPS += ../../../library/util_cpack/util_cpack.v
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M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
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M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
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M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
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M_DEPS += ../../../library/util_upack/util_upack.v
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M_DEPS += ../../../library/util_upack/util_upack_dmx.v
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M_DEPS += ../../../library/util_upack/util_upack_dsf.v
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M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
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M_DEPS += ../../../library/util_wfifo/util_wfifo.v
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M_DEPS += ../../../library/util_wfifo/util_wfifo_constr.sdc
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M_DEPS += ../../../library/util_wfifo/util_wfifo_hw.tcl
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M_ALTERA := quartus_sh --64bit -t
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M_FLIST += *.log
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M_FLIST += *_INFO.txt
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M_FLIST += *_dump.txt
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M_FLIST += db
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M_FLIST += *.asm.rpt
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M_FLIST += *.done
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M_FLIST += *.eda.rpt
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M_FLIST += *.fit.*
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M_FLIST += *.map.*
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M_FLIST += *.sta.*
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M_FLIST += *.qsf
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M_FLIST += *.qpf
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M_FLIST += *.qws
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M_FLIST += *.sof
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M_FLIST += *.cdf
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M_FLIST += *.sld
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M_FLIST += *.qdf
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M_FLIST += hc_output
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M_FLIST += system_bd
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M_FLIST += hps_isw_handoff
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M_FLIST += hps_sdram_*.csv
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M_FLIST += *ddr3_*.csv
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M_FLIST += incremental_db
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M_FLIST += reconfig_mif
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M_FLIST += *.sopcinfo
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M_FLIST += *.jdi
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M_FLIST += *.pin
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M_FLIST += *_summary.csv
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M_FLIST += *.dpf
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.PHONY: all clean clean-all
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all: fmcomms2_a10gx.sof
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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fmcomms2_a10gx.sof: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_ALTERA) system_project.tcl >> fmcomms2_a10gx_quartus.log 2>&1
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####################################################################################
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####################################################################################
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@ -1,17 +0,0 @@
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "4.000 ns" -name rx_clk_250mhz [get_ports {rx_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
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i_system_bd|sys_ddr3_cntrl_phy_clk_0 \
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i_system_bd|sys_ddr3_cntrl_phy_clk_1 \
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i_system_bd|sys_ddr3_cntrl_phy_clk_2 \
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i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \
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i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
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i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
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i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
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@ -1,119 +0,0 @@
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load_package flow
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source ../../scripts/adi_env.tcl
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project_new fmcomms2_a10gx -overwrite
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source "../../common/a10gx/a10gx_system_assign.tcl"
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set_global_assignment -name VERILOG_FILE system_top.v
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set_global_assignment -name QSYS_FILE system_bd.qsys
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set_global_assignment -name SDC_FILE system_constr.sdc
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set_global_assignment -name TOP_LEVEL_ENTITY system_top
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# lane interface
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set_location_assignment PIN_AV15 -to rx_clk_in ; ## G6 FMC_LPC_LA00_CC_P (3B)
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set_location_assignment PIN_AU15 -to "rx_clk_in(n)" ; ## G7 FMC_LPC_LA00_CC_N (3B)
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set_location_assignment PIN_AV19 -to rx_frame_in ; ## D20 FMC_LPC_LA17_CC_P (3B) ## D8 FMC_LPC_LA01_CC_P (3C) PIN_AT10
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set_location_assignment PIN_AW19 -to "rx_frame_in(n)" ; ## D21 FMC_LPC_LA17_CC_N (3B) ## D9 FMC_LPC_LA01_CC_N (3C) PIN_AR11
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set_location_assignment PIN_AR22 -to rx_data_in[0] ; ## H7 FMC_LPC_LA02_P (3B)
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set_location_assignment PIN_AT22 -to "rx_data_in[0](n)" ; ## H8 FMC_LPC_LA02_N (3B)
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set_location_assignment PIN_AR20 -to rx_data_in[1] ; ## G9 FMC_LPC_LA03_P (3B)
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set_location_assignment PIN_AR19 -to "rx_data_in[1](n)" ; ## G10 FMC_LPC_LA03_N (3B)
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set_location_assignment PIN_AN20 -to rx_data_in[2] ; ## H10 FMC_LPC_LA04_P (3B)
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set_location_assignment PIN_AP19 -to "rx_data_in[2](n)" ; ## H11 FMC_LPC_LA04_N (3B)
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set_location_assignment PIN_AU21 -to rx_data_in[3] ; ## C22 FMC_LPC_LA18_CC_P (3B) ## D11 FMC_LPC_LA05_P (3C) PIN_AV11
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set_location_assignment PIN_AV21 -to "rx_data_in[3](n)" ; ## C23 FMC_LPC_LA18_CC_N (3B) ## D12 FMC_LPC_LA05_N (3C) PIN_AW11
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set_location_assignment PIN_AV14 -to rx_data_in[4] ; ## C10 FMC_LPC_LA06_P (3B)
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set_location_assignment PIN_AW14 -to "rx_data_in[4](n)" ; ## C11 FMC_LPC_LA06_N (3B)
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set_location_assignment PIN_AT17 -to rx_data_in[5] ; ## H13 FMC_LPC_LA07_P (3B)
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set_location_assignment PIN_AU17 -to "rx_data_in[5](n)" ; ## H14 FMC_LPC_LA07_N (3B)
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set_location_assignment PIN_AP18 -to tx_clk_out ; ## G12 FMC_LPC_LA08_P (3B)
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set_location_assignment PIN_AN19 -to "tx_clk_out(n)" ; ## G13 FMC_LPC_LA08_N (3B)
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set_location_assignment PIN_AV20 -to tx_frame_out ; ## H37 FMC_LPC_LA32_P (3B) ## D14 FMC_LPC_LA09_P (3C) PIN_AW13
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set_location_assignment PIN_AU20 -to "tx_frame_out(n)" ; ## H38 FMC_LPC_LA32_N (3B) ## D15 FMC_LPC_LA09_N (3C) PIN_AV13
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set_location_assignment PIN_AT14 -to tx_data_out[0] ; ## H16 FMC_LPC_LA11_P (3B)
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set_location_assignment PIN_AR14 -to "tx_data_out[0](n)" ; ## H17 FMC_LPC_LA11_N (3B)
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set_location_assignment PIN_AR16 -to tx_data_out[1] ; ## G15 FMC_LPC_LA12_P (3B)
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set_location_assignment PIN_AP16 -to "tx_data_out[1](n)" ; ## G16 FMC_LPC_LA12_N (3B)
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set_location_assignment PIN_AR17 -to tx_data_out[2] ; ## D17 FMC_LPC_LA13_P (3B)
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set_location_assignment PIN_AP17 -to "tx_data_out[2](n)" ; ## D18 FMC_LPC_LA13_N (3B)
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set_location_assignment PIN_AR15 -to tx_data_out[3] ; ## C14 FMC_LPC_LA10_P (3B)
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set_location_assignment PIN_AT15 -to "tx_data_out[3](n)" ; ## C15 FMC_LPC_LA10_N (3B)
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set_location_assignment PIN_AW18 -to tx_data_out[4] ; ## C18 FMC_LPC_LA14_P (3B)
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set_location_assignment PIN_AV18 -to "tx_data_out[4](n)" ; ## C19 FMC_LPC_LA14_N (3B)
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set_location_assignment PIN_AY17 -to tx_data_out[5] ; ## G36 FMC_LPC_LA33_P (3B) ## H19 FMC_LPC_LA15_P (3C) PIN_AR9
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set_location_assignment PIN_AW17 -to "tx_data_out[5](n)" ; ## G37 FMC_LPC_LA33_N (3B) ## H20 FMC_LPC_LA15_N (3C) PIN_AT9
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set_instance_assignment -name IO_STANDARD LVDS -to rx_clk_in
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set_instance_assignment -name IO_STANDARD LVDS -to rx_frame_in
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[0]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[1]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[2]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[3]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[4]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_data_in[5]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_clk_out
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set_instance_assignment -name IO_STANDARD LVDS -to tx_frame_out
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[0]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[1]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[2]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[3]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[4]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_data_out[5]
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set_location_assignment PIN_AT13 -to enable ; ## G18 FMC_LPC_LA16_P
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set_location_assignment PIN_AU13 -to txnrx ; ## G19 FMC_LPC_LA16_N
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set_instance_assignment -name IO_STANDARD "1.8 V" -to enable
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set_instance_assignment -name IO_STANDARD "1.8 V" -to txnrx
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# gpio
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set_location_assignment PIN_AU8 -to gpio_status[0] ; ## G21 FMC_LPC_LA20_P
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set_location_assignment PIN_AT8 -to gpio_status[1] ; ## G22 FMC_LPC_LA20_N
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set_location_assignment PIN_AY10 -to gpio_status[2] ; ## H25 FMC_LPC_LA21_P
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set_location_assignment PIN_AY11 -to gpio_status[3] ; ## H26 FMC_LPC_LA21_N
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set_location_assignment PIN_AW12 -to gpio_status[4] ; ## G24 FMC_LPC_LA22_P
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set_location_assignment PIN_AY12 -to gpio_status[5] ; ## G25 FMC_LPC_LA22_N
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set_location_assignment PIN_AU18 -to gpio_status[6] ; ## D23 FMC_LPC_LA23_P
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set_location_assignment PIN_AT18 -to gpio_status[7] ; ## D24 FMC_LPC_LA23_N
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set_location_assignment PIN_BB15 -to gpio_ctl[0] ; ## H28 FMC_LPC_LA24_P
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set_location_assignment PIN_BC15 -to gpio_ctl[1] ; ## H29 FMC_LPC_LA24_N
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set_location_assignment PIN_AY15 -to gpio_ctl[2] ; ## G27 FMC_LPC_LA25_P
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set_location_assignment PIN_AY14 -to gpio_ctl[3] ; ## G28 FMC_LPC_LA25_N
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set_location_assignment PIN_AU11 -to gpio_en_agc ; ## H22 FMC_LPC_LA19_P
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set_location_assignment PIN_AU12 -to gpio_sync ; ## H23 FMC_LPC_LA19_N
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set_location_assignment PIN_AY16 -to gpio_resetb ; ## H31 FMC_LPC_LA28_P
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[0]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[1]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[3]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[4]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[5]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[6]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_status[7]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[0]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[1]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[2]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_ctl[3]
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_en_agc
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_sync
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set_instance_assignment -name IO_STANDARD "1.8 V" -to gpio_resetb
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||||
# spi
|
||||
|
||||
set_location_assignment PIN_AT19 -to spi_csn ; ## D26 FMC_LPC_LA26_P
|
||||
set_location_assignment PIN_AT20 -to spi_clk ; ## D27 FMC_LPC_LA26_N
|
||||
set_location_assignment PIN_AP21 -to spi_mosi ; ## C26 FMC_LPC_LA27_P
|
||||
set_location_assignment PIN_AR21 -to spi_miso ; ## C27 FMC_LPC_LA27_N
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
|
||||
|
||||
execute_flow -compile
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
|
||||
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
|
||||
source ../common/fmcomms2_qsys.tcl
|
||||
|
||||
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// Each core or library found in this collection may have its own licensing terms.
|
||||
// The user should keep this in in mind while exploring these cores.
|
||||
//
|
||||
// Redistribution and use in source and binary forms,
|
||||
// with or without modification of this file, are permitted under the terms of either
|
||||
// (at the option of the user):
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory, or at:
|
||||
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
// clock and resets
|
||||
|
||||
input sys_clk,
|
||||
input sys_resetn,
|
||||
|
||||
// ddr3
|
||||
|
||||
output ddr3_clk_p,
|
||||
output ddr3_clk_n,
|
||||
output [ 14:0] ddr3_a,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_cke,
|
||||
output ddr3_cs_n,
|
||||
output ddr3_odt,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_we_n,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_cas_n,
|
||||
inout [ 7:0] ddr3_dqs_p,
|
||||
inout [ 7:0] ddr3_dqs_n,
|
||||
inout [ 63:0] ddr3_dq,
|
||||
output [ 7:0] ddr3_dm,
|
||||
input ddr3_rzq,
|
||||
input ddr3_ref_clk,
|
||||
|
||||
// ethernet
|
||||
|
||||
input eth_ref_clk,
|
||||
input eth_rxd,
|
||||
output eth_txd,
|
||||
output eth_mdc,
|
||||
inout eth_mdio,
|
||||
output eth_resetn,
|
||||
input eth_intn,
|
||||
|
||||
// board gpio
|
||||
|
||||
input [ 10:0] gpio_bd_i,
|
||||
output [ 15:0] gpio_bd_o,
|
||||
|
||||
// ad9361-interface
|
||||
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [ 5:0] rx_data_in,
|
||||
output tx_clk_out,
|
||||
output tx_frame_out,
|
||||
output [ 5:0] tx_data_out,
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
output gpio_resetb,
|
||||
output gpio_sync,
|
||||
output gpio_en_agc,
|
||||
output [ 3:0] gpio_ctl,
|
||||
input [ 7:0] gpio_status,
|
||||
|
||||
output spi_csn,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
|
||||
// conections
|
||||
|
||||
assign gpio_resetb = gpio_o[46];
|
||||
assign gpio_sync = gpio_o[45];
|
||||
assign gpio_en_agc = gpio_o[44];
|
||||
assign gpio_ctl = gpio_o[43:40];
|
||||
assign gpio_i[39:32] = gpio_status;
|
||||
|
||||
assign gpio_bd_o = gpio_o[15:0];
|
||||
|
||||
assign gpio_i[31:27] = gpio_o[31:27];
|
||||
assign gpio_i[15: 0] = gpio_o[15:0];
|
||||
assign gpio_i[26:16] = gpio_bd_i;
|
||||
|
||||
// instantiations
|
||||
|
||||
system_bd i_system_bd (
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_rst_reset_n (sys_resetn),
|
||||
|
||||
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
|
||||
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
|
||||
.sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
|
||||
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
|
||||
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
|
||||
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
|
||||
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
|
||||
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
|
||||
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
|
||||
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
|
||||
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
|
||||
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
|
||||
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
|
||||
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
|
||||
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
|
||||
.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
|
||||
.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
|
||||
|
||||
.sys_ethernet_mdio_mdc (eth_mdc),
|
||||
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
|
||||
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
|
||||
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
|
||||
.sys_ethernet_ref_clk_clk (eth_ref_clk),
|
||||
.sys_ethernet_reset_reset (eth_reset),
|
||||
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
|
||||
.sys_ethernet_sgmii_txp_0 (eth_txd),
|
||||
|
||||
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.sys_gpio_in_export (gpio_i[63:32]),
|
||||
.sys_gpio_out_export (gpio_o[63:32]),
|
||||
|
||||
.axi_ad9361_device_if_enable (enable),
|
||||
.axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
|
||||
.axi_ad9361_device_if_rx_clk_in_n (1'b0),
|
||||
.axi_ad9361_device_if_rx_data_in_p (rx_data_in),
|
||||
.axi_ad9361_device_if_rx_data_in_n (6'd0),
|
||||
.axi_ad9361_device_if_rx_frame_in_p (rx_frame_in),
|
||||
.axi_ad9361_device_if_rx_frame_in_n (1'b0),
|
||||
.axi_ad9361_device_if_tx_clk_out_p (tx_clk_out),
|
||||
.axi_ad9361_device_if_tx_clk_out_n (1'b0),
|
||||
.axi_ad9361_device_if_tx_data_out_p (tx_data_out),
|
||||
.axi_ad9361_device_if_tx_data_out_n (6'd0),
|
||||
.axi_ad9361_device_if_tx_frame_out_p (tx_frame_out),
|
||||
.axi_ad9361_device_if_tx_frame_out_n (1'b0),
|
||||
.axi_ad9361_device_if_txnrx (txnrx),
|
||||
|
||||
.delay_clk_clk (1'b0),
|
||||
|
||||
.up_enable_up_enable (gpio_o[47]),
|
||||
.up_txnrx_up_txnrx (gpio_o[48]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue