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common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion 

Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.

To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-20 16:05:03 +02:00
parent 4f5f15e36e
commit 669a2da735
1 changed files with 8 additions and 8 deletions
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16
projects/common/a10soc/a10soc_system_qsys.tcl
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@ -116,11 +116,17 @@ set_interface_property sys_hps_rstn EXPORT_OF sys_hps.f2h_cold_reset_req
add_interface sys_hps_out_rstn reset source
set_interface_property sys_hps_out_rstn EXPORT_OF sys_hps.h2f_reset
add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
add_connection sys_hps.h2f_user0_clock sys_hps.f2sdram0_clock
add_connection sys_clk.clk_reset sys_hps.f2sdram0_reset
add_interface sys_hps_io conduit end
set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io
# common dma interfaces
add_instance sys_dma_clk clock_source
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
add_connection sys_dma_clk.clk sys_hps.f2sdram0_clock
add_connection sys_dma_clk.clk_reset sys_hps.f2sdram0_reset
# ddr4 interface
add_instance sys_hps_ddr4_cntrl altera_emif_a10_hps
@ -187,12 +193,6 @@ proc ad_dma_interconnect {m_port} {
set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0}
}
# common dma interfaces
add_instance sys_dma_clk clock_source
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
# gpio-bd
add_instance sys_gpio_bd altera_avalon_pio