From 66823682b63c1037abdc3fc1dd4d4e63d3cfbc1a Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Fri, 11 Jan 2019 10:54:16 +0200 Subject: [PATCH] Add FPGA info parameters flow Common basic steps: - Include/create infrastructure: * Intel: - require quartus::device package - set_module_property VALIDATION_CALLBACK info_param_validate * Xilinx - add bd.tcl, containing init{} procedure. The init procedure will be called when the IP will be instantiated into the block design. - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl - create GUI files - add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params) - add/propagate the info parameters through the IP verilog files axi_clkgen util_adxcvr ad_ip_jesd204_tpl_adc ad_ip_jesd204_tpl_dac axi_ad5766 axi_ad6676 axi_ad9122 axi_ad9144 axi_ad9152 axi_ad9162 axi_ad9250 axi_ad9265 axi_ad9680 axi_ad9361 axi_ad9371 axi_adrv9009 axi_ad9739a axi_ad9434 axi_ad9467 axi_ad9684 axi_ad9963 axi_ad9625 axi_ad9671 axi_hdmi_tx axi_fmcadc5_sync --- library/altera/axi_adxcvr/axi_adxcvr.v | 12 +++ library/altera/axi_adxcvr/axi_adxcvr_hw.tcl | 11 +++ library/altera/axi_adxcvr/axi_adxcvr_up.v | 10 ++- library/axi_ad5766/axi_ad5766.v | 8 ++ library/axi_ad5766/axi_ad5766_ip.tcl | 8 +- library/axi_ad5766/bd/bd.tcl | 16 ++++ library/axi_ad6676/axi_ad6676.v | 10 ++- library/axi_ad6676/axi_ad6676_ip.tcl | 8 +- library/axi_ad6676/bd/bd.tcl | 16 ++++ library/axi_ad9122/axi_ad9122.v | 11 ++- library/axi_ad9122/axi_ad9122_channel.v | 2 +- library/axi_ad9122/axi_ad9122_core.v | 8 ++ library/axi_ad9122/axi_ad9122_hw.tcl | 17 ++-- library/axi_ad9122/axi_ad9122_if.v | 10 +-- library/axi_ad9122/axi_ad9122_ip.tcl | 9 ++- library/axi_ad9122/bd/bd.tcl | 16 ++++ library/axi_ad9144/axi_ad9144.v | 8 ++ library/axi_ad9144/axi_ad9144_hw.tcl | 4 + library/axi_ad9144/axi_ad9144_ip.tcl | 8 +- library/axi_ad9144/bd/bd.tcl | 16 ++++ library/axi_ad9152/axi_ad9152.v | 8 ++ library/axi_ad9152/axi_ad9152_hw.tcl | 5 ++ library/axi_ad9152/axi_ad9152_ip.tcl | 8 +- library/axi_ad9152/bd/bd.tcl | 16 ++++ library/axi_ad9162/axi_ad9162.v | 8 ++ library/axi_ad9162/axi_ad9162_core.v | 8 ++ library/axi_ad9162/axi_ad9162_ip.tcl | 8 +- library/axi_ad9162/bd/bd.tcl | 16 ++++ library/axi_ad9250/axi_ad9250.v | 10 ++- library/axi_ad9250/axi_ad9250_hw.tcl | 5 ++ library/axi_ad9250/axi_ad9250_ip.tcl | 8 +- library/axi_ad9250/bd/bd.tcl | 16 ++++ library/axi_ad9265/axi_ad9265.v | 13 +++- library/axi_ad9265/axi_ad9265_if.v | 9 +-- library/axi_ad9265/axi_ad9265_ip.tcl | 8 +- library/axi_ad9265/bd/bd.tcl | 16 ++++ .../axi_ad9361/altera/axi_ad9361_cmos_if.v | 2 +- .../axi_ad9361/altera/axi_ad9361_lvds_if.v | 10 +-- library/axi_ad9361/axi_ad9361.v | 17 +++- library/axi_ad9361/axi_ad9361_hw.tcl | 18 +++-- library/axi_ad9361/axi_ad9361_ip.tcl | 8 +- library/axi_ad9361/axi_ad9361_rx.v | 8 ++ library/axi_ad9361/axi_ad9361_tx.v | 8 ++ library/axi_ad9361/bd/bd.tcl | 16 ++++ .../axi_ad9361/xilinx/axi_ad9361_cmos_if.v | 19 +++-- .../axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 19 +++-- library/axi_ad9371/axi_ad9371.v | 16 ++++ library/axi_ad9371/axi_ad9371_hw.tcl | 5 ++ library/axi_ad9371/axi_ad9371_ip.tcl | 8 +- library/axi_ad9371/axi_ad9371_rx.v | 12 ++- library/axi_ad9371/axi_ad9371_rx_os.v | 16 +++- library/axi_ad9371/axi_ad9371_tx.v | 12 ++- library/axi_ad9371/bd/bd.tcl | 16 ++++ library/axi_ad9434/axi_ad9434.v | 17 ++-- library/axi_ad9434/axi_ad9434_core.v | 10 ++- library/axi_ad9434/axi_ad9434_if.v | 8 +- library/axi_ad9434/axi_ad9434_ip.tcl | 8 +- library/axi_ad9434/bd/bd.tcl | 16 ++++ library/axi_ad9467/axi_ad9467.v | 13 +++- library/axi_ad9467/axi_ad9467_if.v | 9 +-- library/axi_ad9467/axi_ad9467_ip.tcl | 8 +- library/axi_ad9467/bd/bd.tcl | 16 ++++ library/axi_ad9625/axi_ad9625.v | 10 ++- library/axi_ad9625/axi_ad9625_ip.tcl | 8 +- library/axi_ad9625/bd/bd.tcl | 50 ++++++++++++ library/axi_ad9671/axi_ad9671.v | 12 ++- library/axi_ad9671/axi_ad9671_hw.tcl | 5 ++ library/axi_ad9671/axi_ad9671_ip.tcl | 8 +- library/axi_ad9671/bd/bd.tcl | 50 ++++++++++++ library/axi_ad9680/axi_ad9680.v | 10 ++- library/axi_ad9680/axi_ad9680_hw.tcl | 5 ++ library/axi_ad9680/axi_ad9680_ip.tcl | 8 +- library/axi_ad9680/bd/bd.tcl | 16 ++++ library/axi_ad9684/axi_ad9684.v | 13 +++- library/axi_ad9684/axi_ad9684_hw.tcl | 20 +++-- library/axi_ad9684/axi_ad9684_if.v | 8 +- library/axi_ad9684/axi_ad9684_ip.tcl | 8 +- library/axi_ad9684/bd/bd.tcl | 16 ++++ library/axi_ad9739a/axi_ad9739a.v | 11 ++- library/axi_ad9739a/axi_ad9739a_core.v | 12 ++- library/axi_ad9739a/axi_ad9739a_if.v | 8 +- library/axi_ad9739a/axi_ad9739a_ip.tcl | 8 +- library/axi_ad9739a/bd/bd.tcl | 16 ++++ library/axi_ad9963/axi_ad9963.v | 15 +++- library/axi_ad9963/axi_ad9963_if.v | 6 +- library/axi_ad9963/axi_ad9963_ip.tcl | 8 +- library/axi_ad9963/axi_ad9963_rx.v | 10 ++- library/axi_ad9963/axi_ad9963_tx.v | 8 ++ library/axi_ad9963/bd/bd.tcl | 16 ++++ library/axi_adrv9009/axi_adrv9009.v | 16 ++++ library/axi_adrv9009/axi_adrv9009_hw.tcl | 5 ++ library/axi_adrv9009/axi_adrv9009_ip.tcl | 8 +- library/axi_adrv9009/axi_adrv9009_rx.v | 8 ++ library/axi_adrv9009/axi_adrv9009_rx_os.v | 8 ++ library/axi_adrv9009/axi_adrv9009_tx.v | 8 ++ library/axi_adrv9009/bd/bd.tcl | 16 ++++ library/axi_clkgen/axi_clkgen.v | 15 +++- library/axi_clkgen/axi_clkgen_ip.tcl | 7 +- library/axi_clkgen/bd/bd.tcl | 17 +++- library/axi_fmcadc5_sync/axi_fmcadc5_sync.v | 11 ++- .../axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl | 8 +- library/axi_fmcadc5_sync/bd/bd.tcl | 16 ++++ library/axi_hdmi_tx/axi_hdmi_tx.v | 14 ++-- library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl | 17 ++-- library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl | 9 ++- library/axi_hdmi_tx/bd/bd.tcl | 50 ++++++++++++ library/common/up_adc_common.v | 19 +++-- library/common/up_clkgen.v | 9 ++- library/common/up_dac_common.v | 19 +++-- .../ad_ip_jesd204_tpl_adc.v | 8 ++ .../ad_ip_jesd204_tpl_adc_regmap.v | 8 ++ .../ad_ip_jesd204_tpl_dac.v | 8 ++ .../ad_ip_jesd204_tpl_dac_ip.tcl | 2 + .../ad_ip_jesd204_tpl_dac_regmap.v | 8 ++ library/util_adcfifo/util_adcfifo.v | 4 +- library/util_adcfifo/util_adcfifo_hw.tcl | 2 +- library/xilinx/axi_adxcvr/Makefile | 1 + library/xilinx/axi_adxcvr/axi_adxcvr.v | 10 +++ library/xilinx/axi_adxcvr/axi_adxcvr_es.v | 26 ++++--- library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl | 10 ++- library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 9 ++- library/xilinx/axi_adxcvr/bd/bd.tcl | 20 +++++ library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v | 2 +- library/xilinx/common/ad_data_clk.v | 7 +- library/xilinx/common/ad_data_in.v | 28 +++---- library/xilinx/common/ad_data_out.v | 26 +++---- library/xilinx/common/ad_mmcm_drp.v | 78 +++++++++++++++++-- library/xilinx/common/ad_serdes_clk.v | 4 +- library/xilinx/common/ad_serdes_in.v | 8 +- library/xilinx/common/ad_serdes_out.v | 8 +- library/xilinx/util_adxcvr/Makefile | 1 + library/xilinx/util_adxcvr/bd/bd.tcl | 12 +++ library/xilinx/util_adxcvr/util_adxcvr.v | 2 +- library/xilinx/util_adxcvr/util_adxcvr_ip.tcl | 10 ++- library/xilinx/util_adxcvr/util_adxcvr_xch.v | 22 +++--- library/xilinx/util_adxcvr/util_adxcvr_xcm.v | 10 ++- 136 files changed, 1416 insertions(+), 248 deletions(-) create mode 100644 library/axi_ad5766/bd/bd.tcl create mode 100644 library/axi_ad6676/bd/bd.tcl create mode 100644 library/axi_ad9122/bd/bd.tcl create mode 100644 library/axi_ad9144/bd/bd.tcl create mode 100644 library/axi_ad9152/bd/bd.tcl create mode 100644 library/axi_ad9162/bd/bd.tcl create mode 100644 library/axi_ad9250/bd/bd.tcl create mode 100644 library/axi_ad9265/bd/bd.tcl create mode 100644 library/axi_ad9361/bd/bd.tcl create mode 100644 library/axi_ad9371/bd/bd.tcl create mode 100644 library/axi_ad9434/bd/bd.tcl create mode 100644 library/axi_ad9467/bd/bd.tcl create mode 100644 library/axi_ad9625/bd/bd.tcl create mode 100644 library/axi_ad9671/bd/bd.tcl create mode 100644 library/axi_ad9680/bd/bd.tcl create mode 100644 library/axi_ad9684/bd/bd.tcl create mode 100644 library/axi_ad9739a/bd/bd.tcl create mode 100644 library/axi_ad9963/bd/bd.tcl create mode 100644 library/axi_adrv9009/bd/bd.tcl create mode 100644 library/axi_fmcadc5_sync/bd/bd.tcl create mode 100644 library/axi_hdmi_tx/bd/bd.tcl create mode 100644 library/xilinx/axi_adxcvr/bd/bd.tcl create mode 100644 library/xilinx/util_adxcvr/bd/bd.tcl diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v index 089f00428..d16557a0e 100644 --- a/library/altera/axi_adxcvr/axi_adxcvr.v +++ b/library/altera/axi_adxcvr/axi_adxcvr.v @@ -40,6 +40,12 @@ module axi_adxcvr #( // parameters parameter integer ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, + parameter integer XCVR_TYPE = 0, parameter integer TX_OR_RX_N = 0, parameter integer NUM_OF_LANES = 4) ( @@ -93,6 +99,12 @@ module axi_adxcvr #( axi_adxcvr_up #( .ID (ID), + .XCVR_TYPE (XCVR_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .FPGA_VOLTAGE (FPGA_VOLTAGE), .TX_OR_RX_N (TX_OR_RX_N), .NUM_OF_LANES (NUM_OF_LANES)) i_up ( diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl index f5acbea8e..8f2e36c3e 100644 --- a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl @@ -1,5 +1,6 @@ package require qsys +package require quartus::device source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl @@ -10,6 +11,7 @@ set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_adxcvr set_module_property ELABORATION_CALLBACK p_axi_adxcvr +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -39,6 +41,15 @@ set_parameter_property NUM_OF_LANES TYPE INTEGER set_parameter_property NUM_OF_LANES UNITS None set_parameter_property NUM_OF_LANES HDL_PARAMETER true +adi_add_auto_fpga_spec_params + +adi_add_device_spec_param XCVR_TYPE +adi_add_device_spec_param FPGA_VOLTAGE +set_parameter_property FPGA_VOLTAGE DISPLAY_UNITS mV +set_parameter_property FPGA_VOLTAGE_MANUAL DISPLAY_UNITS mV +adi_add_indep_spec_params_overwrite XCVR_TYPE +adi_add_indep_spec_params_overwrite FPGA_VOLTAGE + # axi4 slave interface ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v index e0cd73794..b60db61ee 100644 --- a/library/altera/axi_adxcvr/axi_adxcvr_up.v +++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v @@ -40,6 +40,12 @@ module axi_adxcvr_up #( // parameters parameter integer ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, + parameter integer XCVR_TYPE = 0, parameter integer TX_OR_RX_N = 0, parameter integer NUM_OF_LANES = 4) ( @@ -136,7 +142,8 @@ module axi_adxcvr_up #( // Specific to Altera - assign up_rparam_s[31:24] = 8'd0; + assign up_rparam_s[31:28] = 8'd0; + assign up_rparam_s[27:24] = XCVR_TYPE[3:0]; // Specific to Xilinx @@ -168,6 +175,7 @@ module axi_adxcvr_up #( 10'h005: up_rdata_d <= {31'd0, up_status_int}; 10'h006: up_rdata_d <= up_status_32_s; 10'h009: up_rdata_d <= up_rparam_s; + 10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV default: up_rdata_d <= 32'd0; endcase end else begin diff --git a/library/axi_ad5766/axi_ad5766.v b/library/axi_ad5766/axi_ad5766.v index cf2f89076..e5169943f 100644 --- a/library/axi_ad5766/axi_ad5766.v +++ b/library/axi_ad5766/axi_ad5766.v @@ -37,6 +37,10 @@ module axi_ad5766 #( + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter ASYNC_SPI_CLK = 0, parameter CMD_MEM_ADDRESS_WIDTH = 4, parameter SDO_MEM_ADDRESS_WIDTH = 4)( @@ -343,6 +347,10 @@ module axi_ad5766 #( up_dac_common #( .COMMON_ID (0), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .CLK_EDGE_SEL (0), .DRP_DISABLE (6'h00), diff --git a/library/axi_ad5766/axi_ad5766_ip.tcl b/library/axi_ad5766/axi_ad5766_ip.tcl index 4cc205557..f40f23008 100644 --- a/library/axi_ad5766/axi_ad5766_ip.tcl +++ b/library/axi_ad5766/axi_ad5766_ip.tcl @@ -13,10 +13,13 @@ adi_ip_files axi_ad5766 [list \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/util_pulse_gen.v" \ "up_ad5766_sequencer.v" \ - "axi_ad5766.v" ] + "axi_ad5766.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad5766 +adi_ip_bd axi_ad5766 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + adi_ip_add_core_dependencies { \ analog.com:user:util_cdc:1.0 \ } @@ -54,5 +57,8 @@ adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" adi_add_bus_clock "dma_clk" "dma_fifo_tx" +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad5766/bd/bd.tcl b/library/axi_ad5766/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad5766/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v index 69b2d7905..7fe0ff23f 100644 --- a/library/axi_ad6676/axi_ad6676.v +++ b/library/axi_ad6676/axi_ad6676.v @@ -38,7 +38,11 @@ module axi_ad6676 #( parameter ID = 0, - parameter NUM_LANES = 2) ( + parameter NUM_LANES = 2, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0) ( // jesd interface // rx_clk is (line-rate/40) @@ -88,6 +92,10 @@ module axi_ad6676 #( ad_ip_jesd204_tpl_adc #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_LANES (NUM_LANES), .NUM_CHANNELS (2), .SAMPLES_PER_FRAME (1), diff --git a/library/axi_ad6676/axi_ad6676_ip.tcl b/library/axi_ad6676/axi_ad6676_ip.tcl index 5c8deca42..bcce0f814 100644 --- a/library/axi_ad6676/axi_ad6676_ip.tcl +++ b/library/axi_ad6676/axi_ad6676_ip.tcl @@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad6676 adi_ip_files axi_ad6676 [list \ - "axi_ad6676.v" ] + "axi_ad6676.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad6676 +adi_ip_bd axi_ad6676 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + adi_ip_add_core_dependencies { \ analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ } @@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad6676/bd/bd.tcl b/library/axi_ad6676/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad6676/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index fd739bf91..1b7c2de7e 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -38,7 +38,10 @@ module axi_ad9122 #( parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter SERDES_OR_DDR_N = 1, parameter MMCM_OR_BUFIO_N = 1, parameter MMCM_CLKIN_PERIOD = 1.667, @@ -154,7 +157,7 @@ module axi_ad9122 #( // device interface axi_ad9122_if #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .SERDES_OR_DDR_N (SERDES_OR_DDR_N), .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N), .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), @@ -206,6 +209,10 @@ module axi_ad9122 #( axi_ad9122_core #( .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), diff --git a/library/axi_ad9122/axi_ad9122_channel.v b/library/axi_ad9122/axi_ad9122_channel.v index 6706348b7..73b8f9282 100644 --- a/library/axi_ad9122/axi_ad9122_channel.v +++ b/library/axi_ad9122/axi_ad9122_channel.v @@ -113,9 +113,9 @@ module axi_ad9122_channel #( .CLK_RATIO (4)) i_dds ( .clk (dac_clk), - .rst (dac_rst), .dac_dds_format (dac_dds_format), .dac_data_sync (dac_data_sync), + .dac_valid (1'b1), .tone_1_scale (dac_dds_scale_1_s), .tone_2_scale (dac_dds_scale_2_s), .tone_1_init_offset (dac_dds_init_1_s), diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index 9941f768d..6cd8e95c5 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -38,6 +38,10 @@ module axi_ad9122_core #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16, @@ -210,6 +214,10 @@ module axi_ad9122_core #( up_dac_common #( .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .CLK_EDGE_SEL (0), .COMMON_ID (6'h10), diff --git a/library/axi_ad9122/axi_ad9122_hw.tcl b/library/axi_ad9122/axi_ad9122_hw.tcl index e0e3139d9..25691307a 100644 --- a/library/axi_ad9122/axi_ad9122_hw.tcl +++ b/library/axi_ad9122/axi_ad9122_hw.tcl @@ -1,9 +1,12 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl ad_ip_create axi_ad9122 {AXI AD9122 Interface} +set_module_property VALIDATION_CALLBACK info_param_validate ad_ip_files axi_ad9122 [list \ $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \ @@ -40,12 +43,14 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true -add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE -set_parameter_property DEVICE_TYPE TYPE INTEGER -set_parameter_property DEVICE_TYPE UNITS None -set_parameter_property DEVICE_TYPE HDL_PARAMETER true +add_parameter FPGA_TECHNOLOGY INTEGER 0 +set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0 +set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY +set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER +set_parameter_property FPGA_TECHNOLOGY UNITS None +set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true + +adi_add_auto_fpga_spec_params # axi4 slave diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index 01465549c..b3fef7ed9 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -39,7 +39,7 @@ module axi_ad9122_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter SERDES_OR_DDR_N = 1, parameter MMCM_OR_BUFIO_N = 1, parameter MMCM_CLKIN_PERIOD = 1.667, @@ -128,7 +128,7 @@ module axi_ad9122_if #( // dac data output serdes(s) & buffers ad_serdes_out #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .DDR_OR_SDR_N (SERDES_OR_DDR_N), .DATA_WIDTH (16)) i_serdes_out_data ( @@ -151,7 +151,7 @@ module axi_ad9122_if #( // dac frame output serdes & buffer ad_serdes_out #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .DDR_OR_SDR_N (SERDES_OR_DDR_N), .DATA_WIDTH (1)) i_serdes_out_frame ( @@ -174,7 +174,7 @@ module axi_ad9122_if #( // dac clock output serdes & buffer ad_serdes_out #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .DDR_OR_SDR_N (SERDES_OR_DDR_N), .DATA_WIDTH (1)) i_serdes_out_clk ( @@ -199,7 +199,7 @@ module axi_ad9122_if #( ad_serdes_clk #( .DDR_OR_SDR_N (SERDES_OR_DDR_N), .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), .MMCM_VCO_DIV (MMCM_VCO_DIV), .MMCM_VCO_MUL (MMCM_VCO_MUL), diff --git a/library/axi_ad9122/axi_ad9122_ip.tcl b/library/axi_ad9122/axi_ad9122_ip.tcl index f1eb5a2bf..8e521be06 100644 --- a/library/axi_ad9122/axi_ad9122_ip.tcl +++ b/library/axi_ad9122/axi_ad9122_ip.tcl @@ -30,10 +30,13 @@ adi_ip_files axi_ad9122 [list \ "axi_ad9122_core.v" \ "axi_ad9122_if.v" \ "axi_ad9122_constr.xdc" \ - "axi_ad9122.v" ] + "axi_ad9122.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9122 +adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] @@ -43,5 +46,9 @@ ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::cur ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9122/bd/bd.tcl b/library/axi_ad9122/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9122/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v index 0775331b1..bb71fa183 100644 --- a/library/axi_ad9144/axi_ad9144.v +++ b/library/axi_ad9144/axi_ad9144.v @@ -38,6 +38,10 @@ module axi_ad9144 #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter QUAD_OR_DUAL_N = 1, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 20, @@ -130,6 +134,10 @@ module axi_ad9144 #( ad_ip_jesd204_tpl_dac #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_LANES (NUM_CHANNELS * 2), .NUM_CHANNELS (NUM_CHANNELS), .CONVERTER_RESOLUTION (16), diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index 23a7dbcaf..a569eb684 100644 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -1,6 +1,7 @@ package require qsys +package require quartus::device source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -10,6 +11,7 @@ set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_ad9144 set_module_property ELABORATION_CALLBACK p_axi_ad9144 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -61,6 +63,8 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER set_parameter_property QUAD_OR_DUAL_N UNITS None set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl index 39fb0e1d0..c320fb4f7 100644 --- a/library/axi_ad9144/axi_ad9144_ip.tcl +++ b/library/axi_ad9144/axi_ad9144_ip.tcl @@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9144 adi_ip_files axi_ad9144 [list \ - "axi_ad9144.v" ] + "axi_ad9144.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9144 +adi_ip_bd axi_ad9144 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + adi_ip_add_core_dependencies { \ analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ } @@ -25,5 +28,8 @@ set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9144/bd/bd.tcl b/library/axi_ad9144/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9144/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 259ffe02d..3d7645cb7 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -38,6 +38,10 @@ module axi_ad9152 #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16, @@ -90,6 +94,10 @@ module axi_ad9152 #( ad_ip_jesd204_tpl_dac #( .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_LANES(4), .NUM_CHANNELS(2), .CONVERTER_RESOLUTION (16), diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index 41fd94bbc..ac07322f2 100644 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9152 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_ad9152 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -53,6 +56,8 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 diff --git a/library/axi_ad9152/axi_ad9152_ip.tcl b/library/axi_ad9152/axi_ad9152_ip.tcl index 43bda11da..46b91c6ed 100644 --- a/library/axi_ad9152/axi_ad9152_ip.tcl +++ b/library/axi_ad9152/axi_ad9152_ip.tcl @@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9152 adi_ip_files axi_ad9152 [list \ - "axi_ad9152.v" ] + "axi_ad9152.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9152 +adi_ip_bd axi_ad9152 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + adi_ip_add_core_dependencies { \ analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \ } @@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9152/bd/bd.tcl b/library/axi_ad9152/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9152/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v index 547fb9bfe..4ac798746 100644 --- a/library/axi_ad9162/axi_ad9162.v +++ b/library/axi_ad9162/axi_ad9162.v @@ -38,6 +38,10 @@ module axi_ad9162 #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16, @@ -123,6 +127,10 @@ module axi_ad9162 #( axi_ad9162_core #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v index f6d0569fa..6426636ed 100644 --- a/library/axi_ad9162/axi_ad9162_core.v +++ b/library/axi_ad9162/axi_ad9162_core.v @@ -38,6 +38,10 @@ module axi_ad9162_core #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16, @@ -129,6 +133,10 @@ module axi_ad9162_core #( up_dac_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .CLK_EDGE_SEL (1'b0), .COMMON_ID (6'h10), diff --git a/library/axi_ad9162/axi_ad9162_ip.tcl b/library/axi_ad9162/axi_ad9162_ip.tcl index f8f0337d9..d828b67d1 100644 --- a/library/axi_ad9162/axi_ad9162_ip.tcl +++ b/library/axi_ad9162/axi_ad9162_ip.tcl @@ -25,13 +25,19 @@ adi_ip_files axi_ad9162 [list \ "axi_ad9162_channel.v" \ "axi_ad9162_core.v" \ "axi_ad9162_if.v" \ - "axi_ad9162.v" ] + "axi_ad9162.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9162 +adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9162/bd/bd.tcl b/library/axi_ad9162/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9162/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index d2113ada2..c4c70b0e6 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -36,7 +36,11 @@ `timescale 1ns/100ps module axi_ad9250 #( - parameter ID = 0 + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0 ) ( // jesd interface @@ -87,6 +91,10 @@ module axi_ad9250 #( ad_ip_jesd204_tpl_adc #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_LANES (2), .NUM_CHANNELS (2), .SAMPLES_PER_FRAME (1), diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl index 7917899e6..360690d55 100644 --- a/library/axi_ad9250/axi_ad9250_hw.tcl +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9250 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_ad9250 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -48,6 +51,8 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_ad9250/axi_ad9250_ip.tcl b/library/axi_ad9250/axi_ad9250_ip.tcl index 0267c6a5a..73e513e1b 100644 --- a/library/axi_ad9250/axi_ad9250_ip.tcl +++ b/library/axi_ad9250/axi_ad9250_ip.tcl @@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9250 adi_ip_files axi_ad9250 [list \ - "axi_ad9250.v" ] + "axi_ad9250.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9250 +adi_ip_bd axi_ad9250 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + adi_ip_add_core_dependencies { \ analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ } @@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9250/bd/bd.tcl b/library/axi_ad9250/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9250/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index d775ed88d..f1dadb242 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -38,7 +38,10 @@ module axi_ad9265 #( parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter ADC_DATAPATH_DISABLE = 0, parameter IO_DELAY_GROUP = "adc_if_delay_group") ( @@ -180,7 +183,7 @@ module axi_ad9265 #( // main (device interface) axi_ad9265_if #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_if ( .adc_clk_in_p (adc_clk_in_p), @@ -224,7 +227,11 @@ module axi_ad9265 #( // common processor control up_adc_common #( - .ID(ID), + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .COMMON_ID (6'h00), .DRP_DISABLE (6'h00), diff --git a/library/axi_ad9265/axi_ad9265_if.v b/library/axi_ad9265/axi_ad9265_if.v index 67d6ca4ef..c7350d4d7 100644 --- a/library/axi_ad9265/axi_ad9265_if.v +++ b/library/axi_ad9265/axi_ad9265_if.v @@ -39,7 +39,7 @@ module axi_ad9265_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter IO_DELAY_GROUP = "adc_if_delay_group") ( // adc interface (clk, data, over-range) @@ -98,7 +98,7 @@ module axi_ad9265_if #( generate for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if ad_data_in #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_data ( @@ -120,7 +120,7 @@ module axi_ad9265_if #( // over-range interface ad_data_in #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (1), .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_or ( @@ -139,8 +139,7 @@ module axi_ad9265_if #( // clock - ad_data_clk #( - .DEVICE_TYPE (DEVICE_TYPE)) + ad_data_clk i_adc_clk ( .rst (1'b0), .locked (), diff --git a/library/axi_ad9265/axi_ad9265_ip.tcl b/library/axi_ad9265/axi_ad9265_ip.tcl index 406d45bac..61fad14e6 100644 --- a/library/axi_ad9265/axi_ad9265_ip.tcl +++ b/library/axi_ad9265/axi_ad9265_ip.tcl @@ -25,10 +25,13 @@ adi_ip_files axi_ad9265 [list \ "axi_ad9265_pnmon.v" \ "axi_ad9265_if.v" \ "axi_ad9265_channel.v" \ - "axi_ad9265.v"] + "axi_ad9265.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9265 +adi_ip_bd axi_ad9265 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] @@ -37,4 +40,7 @@ ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::curr ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9265/bd/bd.tcl b/library/axi_ad9265/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9265/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9361/altera/axi_ad9361_cmos_if.v b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v index 50cbf475f..c598bec12 100644 --- a/library/axi_ad9361/altera/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/altera/axi_ad9361_cmos_if.v @@ -37,7 +37,7 @@ module axi_ad9361_cmos_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DAC_IODELAY_ENABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v index 6df11dfa3..f3e3ee36e 100644 --- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v @@ -37,7 +37,7 @@ module axi_ad9361_lvds_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DAC_IODELAY_ENABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( @@ -178,8 +178,8 @@ module axi_ad9361_lvds_if #( // local parameters - localparam ARRIA10 = 0; - localparam CYCLONE5 = 1; + localparam CYCLONE5 = 'h10; + localparam ARRIA10 = 'h12; // unused interface signals @@ -431,7 +431,7 @@ module axi_ad9361_lvds_if #( end generate - if (DEVICE_TYPE == CYCLONE5) begin + if (FPGA_TECHNOLOGY == CYCLONE5) begin axi_ad9361_lvds_if_c5 i_axi_ad9361_lvds_if_c5 ( .rx_clk_in_p (rx_clk_in_p), .rx_clk_in_n (rx_clk_in_n), @@ -467,7 +467,7 @@ module axi_ad9361_lvds_if #( endgenerate generate - if (DEVICE_TYPE == ARRIA10) begin + if (FPGA_TECHNOLOGY == ARRIA10) begin axi_ad9361_lvds_if_10 i_axi_ad9361_lvds_if_10 ( .rx_clk_in_p (rx_clk_in_p), .rx_clk_in_n (rx_clk_in_n), diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index fac7dab0d..240e53542 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -41,7 +41,10 @@ module axi_ad9361 #( parameter ID = 0, parameter MODE_1R1T = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter TDD_DISABLE = 0, parameter PPS_RECEIVER_ENABLE = 0, parameter CMOS_OR_LVDS_N = 0, @@ -324,7 +327,7 @@ module axi_ad9361 #( assign tx_data_out_n = 6'h3f; axi_ad9361_cmos_if #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_dev_if ( @@ -385,7 +388,7 @@ module axi_ad9361 #( assign up_dac_drdata_s[79:50] = 30'd0; axi_ad9361_lvds_if #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_dev_if ( @@ -566,6 +569,10 @@ module axi_ad9361 #( axi_ad9361_rx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .MODE_1R1T (MODE_1R1T), .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), .PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE), @@ -631,6 +638,10 @@ module axi_ad9361 #( axi_ad9361_tx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .MODE_1R1T (MODE_1R1T), .CLK_EDGE_SEL (DAC_CLK_EDGE_SEL), .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index d493bd4f5..c0ec7a893 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -1,9 +1,13 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab +set_module_property VALIDATION_CALLBACK info_param_validate + ad_ip_files axi_ad9361 [list\ $ad_hdl_dir/library/altera/common/ad_mul.v \ $ad_hdl_dir/library/altera/common/ad_dcfilter.v \ @@ -50,10 +54,8 @@ ad_ip_files axi_ad9361 [list\ # parameters -ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} ad_ip_parameter ID INTEGER 0 ad_ip_parameter MODE_1R1T INTEGER 0 -ad_ip_parameter DEVICE_TYPE INTEGER 0 ad_ip_parameter TDD_DISABLE INTEGER 0 ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0 ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0 @@ -68,6 +70,8 @@ ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0 ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0 ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group} +adi_add_auto_fpga_spec_params + # interfaces ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn @@ -165,27 +169,27 @@ ad_alt_intf signal up_adc_gpio_out output 32 proc axi_ad9361_elab {} { - set m_device_family [get_parameter_value "DEVICE_FAMILY"] + set m_fpga_technology [get_parameter_value "FPGA_TECHNOLOGY"] set m_cmos_or_lvds_n [get_parameter_value "CMOS_OR_LVDS_N"] - if {$m_device_family eq "Arria 10"} { + if {$m_fpga_technology eq "Arria 10"} { add_hdl_instance axi_ad9361_serdes_clk alt_serdes - set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} $m_device_family + set_instance_parameter_value axi_ad9361_serdes_clk {FPGA_TECHNOLOGY} $m_fpga_technology set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK} set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0} add_hdl_instance axi_ad9361_serdes_in alt_serdes - set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} $m_device_family + set_instance_parameter_value axi_ad9361_serdes_in {FPGA_TECHNOLOGY} $m_fpga_technology set_instance_parameter_value axi_ad9361_serdes_in {MODE} {IN} set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4} set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0} add_hdl_instance axi_ad9361_serdes_out alt_serdes - set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} $m_device_family + set_instance_parameter_value axi_ad9361_serdes_out {FPGA_TECHNOLOGY} $m_fpga_technology set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT} set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1} set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4} diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index 35ceed1b5..2448c3ff4 100644 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -48,11 +48,14 @@ adi_ip_files axi_ad9361 [list \ "axi_ad9361_tx.v" \ "axi_ad9361_tdd.v" \ "axi_ad9361_tdd_if.v" \ - "axi_ad9361.v" ] + "axi_ad9361.v" \ + "bd/bd.tcl"] adi_ip_properties axi_ad9361 adi_ip_ttcl axi_ad9361 "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" +adi_ip_bd axi_ad9361 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] @@ -99,5 +102,8 @@ set_property value "ACTIVE_HIGH" $reset_polarity ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index 6446c9e3d..eef678174 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -41,6 +41,10 @@ module axi_ad9361_rx #( // parameters parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter MODE_1R1T = 0, parameter CMOS_OR_LVDS_N = 0, parameter PPS_RECEIVER_ENABLE = 0, @@ -333,6 +337,10 @@ module axi_ad9361_rx #( up_adc_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (CONFIG), .DRP_DISABLE (1), .USERPORTS_DISABLE (USERPORTS_DISABLE), diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index 83959c23b..434db47f8 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -40,6 +40,10 @@ module axi_ad9361_tx #( // parameters parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter MODE_1R1T = 0, parameter CLK_EDGE_SEL = 0, parameter CMOS_OR_LVDS_N = 0, @@ -354,6 +358,10 @@ module axi_ad9361_tx #( up_dac_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (CONFIG), .CLK_EDGE_SEL (CLK_EDGE_SEL), .DRP_DISABLE (1), diff --git a/library/axi_ad9361/bd/bd.tcl b/library/axi_ad9361/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9361/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v index 34e33896c..7d2d9c4db 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v @@ -37,7 +37,7 @@ module axi_ad9361_cmos_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DAC_IODELAY_ENABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( @@ -366,7 +366,7 @@ module axi_ad9361_cmos_if #( for (i = 0; i < 12; i = i + 1) begin: g_rx_data ad_data_in #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_data ( @@ -389,7 +389,7 @@ module axi_ad9361_cmos_if #( ad_data_in #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (1), .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_frame ( @@ -412,7 +412,7 @@ module axi_ad9361_cmos_if #( for (i = 0; i < 12; i = i + 1) begin: g_tx_data ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -436,7 +436,7 @@ module axi_ad9361_cmos_if #( ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -458,7 +458,7 @@ module axi_ad9361_cmos_if #( ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -480,7 +480,7 @@ module axi_ad9361_cmos_if #( ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -502,7 +502,7 @@ module axi_ad9361_cmos_if #( ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -523,8 +523,7 @@ module axi_ad9361_cmos_if #( // device clock interface (receive clock) ad_data_clk #( - .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE)) + .SINGLE_ENDED (1)) i_clk ( .rst (1'd0), .locked (), diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index adc8b30ec..83524fcf2 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -37,7 +37,7 @@ module axi_ad9361_lvds_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DAC_IODELAY_ENABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( @@ -472,7 +472,7 @@ module axi_ad9361_lvds_if #( generate for (i = 0; i < 6; i = i + 1) begin: g_rx_data ad_data_in #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_data ( @@ -494,7 +494,7 @@ module axi_ad9361_lvds_if #( // receive frame interface, ibuf -> idelay -> iddr ad_data_in #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (1), .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_frame ( @@ -516,7 +516,7 @@ module axi_ad9361_lvds_if #( generate for (i = 0; i < 6; i = i + 1) begin: g_tx_data ad_data_out #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -539,7 +539,7 @@ module axi_ad9361_lvds_if #( // transmit frame interface, oddr -> obuf ad_data_out #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -560,7 +560,7 @@ module axi_ad9361_lvds_if #( // transmit clock interface, oddr -> obuf ad_data_out #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -582,7 +582,7 @@ module axi_ad9361_lvds_if #( ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -604,7 +604,7 @@ module axi_ad9361_lvds_if #( ad_data_out #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (DAC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -624,8 +624,7 @@ module axi_ad9361_lvds_if #( // device clock interface (receive clock) - ad_data_clk #( - .DEVICE_TYPE (DEVICE_TYPE)) + ad_data_clk i_clk ( .rst (1'd0), .locked (), diff --git a/library/axi_ad9371/axi_ad9371.v b/library/axi_ad9371/axi_ad9371.v index 3d3fbc471..c08fdba07 100644 --- a/library/axi_ad9371/axi_ad9371.v +++ b/library/axi_ad9371/axi_ad9371.v @@ -38,6 +38,10 @@ module axi_ad9371 #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 20, parameter DAC_DDS_CORDIC_PHASE_DW = 18, @@ -203,6 +207,10 @@ module axi_ad9371 #( axi_ad9371_rx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_rx ( .adc_rst (adc_rst), @@ -236,6 +244,10 @@ module axi_ad9371 #( axi_ad9371_rx_os #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) i_rx_os ( .adc_os_rst (adc_os_rst), @@ -264,6 +276,10 @@ module axi_ad9371 #( axi_ad9371_tx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl index 08e19383b..06f4d2566 100644 --- a/library/axi_ad9371/axi_ad9371_hw.tcl +++ b/library/axi_ad9371/axi_ad9371_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9371 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_ad9371 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -69,6 +72,8 @@ set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER set_parameter_property ADC_DATAPATH_DISABLE UNITS None set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_ad9371/axi_ad9371_ip.tcl b/library/axi_ad9371/axi_ad9371_ip.tcl index 3b8b0b270..73d881d4a 100644 --- a/library/axi_ad9371/axi_ad9371_ip.tcl +++ b/library/axi_ad9371/axi_ad9371_ip.tcl @@ -35,15 +35,21 @@ adi_ip_files axi_ad9371 [list \ "axi_ad9371_rx_os.v" \ "axi_ad9371_tx_channel.v" \ "axi_ad9371_tx.v" \ - "axi_ad9371.v" ] + "axi_ad9371.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9371 +adi_ip_bd axi_ad9371 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9371/axi_ad9371_rx.v b/library/axi_ad9371/axi_ad9371_rx.v index b56913f67..c9089a57e 100644 --- a/library/axi_ad9371/axi_ad9371_rx.v +++ b/library/axi_ad9371/axi_ad9371_rx.v @@ -37,8 +37,12 @@ module axi_ad9371_rx #( - parameter DATAPATH_DISABLE = 0, - parameter ID = 0) ( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DATAPATH_DISABLE = 0) ( // adc interface @@ -255,6 +259,10 @@ module axi_ad9371_rx #( up_adc_common #( .COMMON_ID ('h00), .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .DRP_DISABLE (0), .USERPORTS_DISABLE (0), diff --git a/library/axi_ad9371/axi_ad9371_rx_os.v b/library/axi_ad9371/axi_ad9371_rx_os.v index 95861703b..b75066cf2 100644 --- a/library/axi_ad9371/axi_ad9371_rx_os.v +++ b/library/axi_ad9371/axi_ad9371_rx_os.v @@ -37,8 +37,12 @@ module axi_ad9371_rx_os #( - parameter DATAPATH_DISABLE = 0, - parameter ID = 0) ( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DATAPATH_DISABLE = 0) ( // adc interface @@ -176,8 +180,12 @@ module axi_ad9371_rx_os #( up_adc_common #( .COMMON_ID ('h20), - .ID (ID)) - i_up_adc_common ( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_os_clk), .adc_rst (adc_os_rst), diff --git a/library/axi_ad9371/axi_ad9371_tx.v b/library/axi_ad9371/axi_ad9371_tx.v index 310b1fbe6..ed8373317 100644 --- a/library/axi_ad9371/axi_ad9371_tx.v +++ b/library/axi_ad9371/axi_ad9371_tx.v @@ -38,6 +38,10 @@ module axi_ad9371_tx #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16, @@ -255,7 +259,13 @@ module axi_ad9371_tx #( // dac common processor interface - up_dac_common #(.ID (ID)) i_up_dac_common ( + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_clk), .dac_rst (dac_rst), diff --git a/library/axi_ad9371/bd/bd.tcl b/library/axi_ad9371/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9371/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v index 5d65b829f..69f5c203f 100644 --- a/library/axi_ad9434/axi_ad9434.v +++ b/library/axi_ad9434/axi_ad9434.v @@ -39,8 +39,10 @@ module axi_ad9434 #( parameter ID = 0, - // set to 0 for Xilinx 7 Series or 1 for 6 Series - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface @@ -128,7 +130,7 @@ module axi_ad9434 #( assign up_rstn = s_axi_aresetn; axi_ad9434_if #( - .DEVICE_TYPE(DEVICE_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .IO_DELAY_GROUP(IO_DELAY_GROUP)) i_if( .adc_clk_in_p(adc_clk_in_p), @@ -160,8 +162,13 @@ module axi_ad9434 #( .up_drp_locked(up_drp_locked_s)); // common processor control - axi_ad9434_core #(.ID(ID)) - i_core ( + axi_ad9434_core #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_core ( .adc_clk(adc_clk), .adc_data(adc_data_if_s), .adc_or(adc_or_if_s), diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v index 88e4c8159..182edc429 100644 --- a/library/axi_ad9434/axi_ad9434_core.v +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -37,7 +37,11 @@ module axi_ad9434_core #( - parameter ID = 0) ( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0) ( // device interface @@ -148,6 +152,10 @@ module axi_ad9434_core #( up_adc_common #( .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG(0), .COMMON_ID(0), .DRP_DISABLE(0), diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v index 4509152d4..5dbd05f66 100644 --- a/library/axi_ad9434/axi_ad9434_if.v +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -37,7 +37,7 @@ module axi_ad9434_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // device interface @@ -100,7 +100,7 @@ module axi_ad9434_if #( // data interface ad_serdes_in #( - .DEVICE_TYPE(DEVICE_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .IODELAY_CTRL(0), .IODELAY_GROUP(IO_DELAY_GROUP), .DDR_OR_SDR_N(SDR), @@ -133,7 +133,7 @@ module axi_ad9434_if #( // over-range interface ad_serdes_in #( - .DEVICE_TYPE(DEVICE_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .IODELAY_CTRL(1), .IODELAY_GROUP(IO_DELAY_GROUP), .DDR_OR_SDR_N(SDR), @@ -166,7 +166,7 @@ module axi_ad9434_if #( // clock input buffers and MMCM_OR_BUFR_N ad_serdes_clk #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .CLKIN_DS_OR_SE_N (1), .MMCM_OR_BUFR_N (1), .MMCM_CLKIN_PERIOD (2), diff --git a/library/axi_ad9434/axi_ad9434_ip.tcl b/library/axi_ad9434/axi_ad9434_ip.tcl index ddf9aa84b..25daab980 100644 --- a/library/axi_ad9434/axi_ad9434_ip.tcl +++ b/library/axi_ad9434/axi_ad9434_ip.tcl @@ -26,14 +26,20 @@ adi_ip_files axi_ad9434 [list \ "axi_ad9434_pnmon.v" \ "axi_ad9434_core.v" \ "axi_ad9434_constr.xdc" \ - "axi_ad9434.v" ] + "axi_ad9434.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9434 +adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9434/bd/bd.tcl b/library/axi_ad9434/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9434/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index e1df6d0c6..20f6c5939 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -38,7 +38,10 @@ module axi_ad9467#( parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // physical interface @@ -144,7 +147,7 @@ module axi_ad9467#( // main (device interface) axi_ad9467_if #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_if ( .adc_clk_in_p (adc_clk_in_p), @@ -211,7 +214,11 @@ module axi_ad9467#( // common processor control up_adc_common #( - .ID(ID), + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .COMMON_ID (6'h00), .DRP_DISABLE (6'h00), diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v index ad81cca51..76beca06c 100644 --- a/library/axi_ad9467/axi_ad9467_if.v +++ b/library/axi_ad9467/axi_ad9467_if.v @@ -38,7 +38,7 @@ module axi_ad9467_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( // adc interface (clk, data, over-range) @@ -128,7 +128,7 @@ module axi_ad9467_if #( generate for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if ad_data_in #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_data ( @@ -150,7 +150,7 @@ module axi_ad9467_if #( // over-range interface ad_data_in #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_CTRL (1), .IODELAY_GROUP (IO_DELAY_GROUP)) i_adc_or ( @@ -169,8 +169,7 @@ module axi_ad9467_if #( // clock - ad_data_clk #( - .DEVICE_TYPE (DEVICE_TYPE)) + ad_data_clk i_adc_clk ( .rst (1'b0), .locked (), diff --git a/library/axi_ad9467/axi_ad9467_ip.tcl b/library/axi_ad9467/axi_ad9467_ip.tcl index b8761a329..28c80de60 100644 --- a/library/axi_ad9467/axi_ad9467_ip.tcl +++ b/library/axi_ad9467/axi_ad9467_ip.tcl @@ -24,10 +24,13 @@ adi_ip_files axi_ad9467 [list \ "axi_ad9467_pnmon.v" \ "axi_ad9467_if.v" \ "axi_ad9467_channel.v" \ - "axi_ad9467.v"] + "axi_ad9467.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9467 +adi_ip_bd axi_ad9467 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] @@ -35,4 +38,7 @@ ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9467/bd/bd.tcl b/library/axi_ad9467/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9467/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9625/axi_ad9625.v b/library/axi_ad9625/axi_ad9625.v index caa114f7d..e495c80e2 100644 --- a/library/axi_ad9625/axi_ad9625.v +++ b/library/axi_ad9625/axi_ad9625.v @@ -37,7 +37,11 @@ module axi_ad9625 #( - parameter ID = 0) ( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0) ( // jesd interface // rx_clk is (line-rate/40) @@ -180,6 +184,10 @@ module axi_ad9625 #( up_adc_common #( .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG(0), .COMMON_ID(6'h0), .DRP_DISABLE(1), diff --git a/library/axi_ad9625/axi_ad9625_ip.tcl b/library/axi_ad9625/axi_ad9625_ip.tcl index 8f4f9d4b3..5be6b5af2 100644 --- a/library/axi_ad9625/axi_ad9625_ip.tcl +++ b/library/axi_ad9625/axi_ad9625_ip.tcl @@ -23,10 +23,13 @@ adi_ip_files axi_ad9625 [list \ "axi_ad9625_pnmon.v" \ "axi_ad9625_channel.v" \ "axi_ad9625_if.v" \ - "axi_ad9625.v" ] + "axi_ad9625.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9625 +adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] @@ -36,5 +39,8 @@ ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_co ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9625/bd/bd.tcl b/library/axi_ad9625/bd/bd.tcl new file mode 100644 index 000000000..b90113ec1 --- /dev/null +++ b/library/axi_ad9625/bd/bd.tcl @@ -0,0 +1,50 @@ +## *************************************************************************** +## *************************************************************************** +## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +## +## In this HDL repository, there are many different and unique modules, consisting +## of various HDL (Verilog or VHDL) components. The individual modules are +## developed independently, and may be accompanied by separate and unique license +## terms. +## +## The user should read each of these license terms, and understand the +## freedoms and responsibilities that he or she has by using this source/core. +## +## This core is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +## A PARTICULAR PURPOSE. +## +## Redistribution and use of source or resulting binaries, with or without modification +## of this file, are permitted under one of the following two license terms: +## +## 1. The GNU General Public License version 2 as published by the +## Free Software Foundation, which can be found in the top level directory +## of this repository (LICENSE_GPL2), and also online at: +## +## +## OR +## +## 2. An ADI specific BSD license, which can be found in the top level directory +## of this repository (LICENSE_ADIBSD), and also on-line at: +## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +## This will allow to generate bit files and not release the source code, +## as long as it attaches to an ADI device. +## +## *************************************************************************** +## *************************************************************************** + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index cb6bb8a2b..93fb747f9 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -38,6 +38,10 @@ module axi_ad9671 #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter QUAD_OR_DUAL_N = 1) ( // jesd interface @@ -220,7 +224,13 @@ module axi_ad9671 #( // common processor control - up_adc_common #(.ID (ID)) i_up_adc_common ( + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_adc_common ( .mmcm_rst (), .adc_clk (adc_clk), .adc_rst (adc_rst), diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl index c39dd0a43..d6c2d4f71 100644 --- a/library/axi_ad9671/axi_ad9671_hw.tcl +++ b/library/axi_ad9671/axi_ad9671_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9671 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_ad9671 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -50,6 +53,8 @@ set_parameter_property QUAD_OR_DUAL_N TYPE INTEGER set_parameter_property QUAD_OR_DUAL_N UNITS None set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_ad9671/axi_ad9671_ip.tcl b/library/axi_ad9671/axi_ad9671_ip.tcl index ddd663144..1ffb567f3 100644 --- a/library/axi_ad9671/axi_ad9671_ip.tcl +++ b/library/axi_ad9671/axi_ad9671_ip.tcl @@ -23,14 +23,20 @@ adi_ip_files axi_ad9671 [list \ "axi_ad9671_pnmon.v" \ "axi_ad9671_channel.v" \ "axi_ad9671_if.v" \ - "axi_ad9671.v" ] + "axi_ad9671.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9671 +adi_ip_bd axi_ad9371 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9671/bd/bd.tcl b/library/axi_ad9671/bd/bd.tcl new file mode 100644 index 000000000..b90113ec1 --- /dev/null +++ b/library/axi_ad9671/bd/bd.tcl @@ -0,0 +1,50 @@ +## *************************************************************************** +## *************************************************************************** +## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +## +## In this HDL repository, there are many different and unique modules, consisting +## of various HDL (Verilog or VHDL) components. The individual modules are +## developed independently, and may be accompanied by separate and unique license +## terms. +## +## The user should read each of these license terms, and understand the +## freedoms and responsibilities that he or she has by using this source/core. +## +## This core is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +## A PARTICULAR PURPOSE. +## +## Redistribution and use of source or resulting binaries, with or without modification +## of this file, are permitted under one of the following two license terms: +## +## 1. The GNU General Public License version 2 as published by the +## Free Software Foundation, which can be found in the top level directory +## of this repository (LICENSE_GPL2), and also online at: +## +## +## OR +## +## 2. An ADI specific BSD license, which can be found in the top level directory +## of this repository (LICENSE_ADIBSD), and also on-line at: +## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +## This will allow to generate bit files and not release the source code, +## as long as it attaches to an ADI device. +## +## *************************************************************************** +## *************************************************************************** + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 5b0b1236c..8e17791d9 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -37,7 +37,11 @@ module axi_ad9680 #( - parameter ID = 0) ( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0) ( // jesd interface // rx_clk is (line-rate/40) @@ -87,6 +91,10 @@ module axi_ad9680 #( ad_ip_jesd204_tpl_adc #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_LANES (4), .NUM_CHANNELS (2), .SAMPLES_PER_FRAME (1), diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl index cc0d740ee..64b24109d 100644 --- a/library/axi_ad9680/axi_ad9680_hw.tcl +++ b/library/axi_ad9680/axi_ad9680_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI AD9680 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_ad9680 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -48,6 +51,8 @@ set_parameter_property ID TYPE INTEGER set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_ad9680/axi_ad9680_ip.tcl b/library/axi_ad9680/axi_ad9680_ip.tcl index 24503bdc4..823d0cc42 100644 --- a/library/axi_ad9680/axi_ad9680_ip.tcl +++ b/library/axi_ad9680/axi_ad9680_ip.tcl @@ -5,10 +5,13 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_ad9680 adi_ip_files axi_ad9680 [list \ - "axi_ad9680.v" ] + "axi_ad9680.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9680 +adi_ip_bd axi_ad9680 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + adi_ip_add_core_dependencies { \ analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \ } @@ -19,4 +22,7 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9680/bd/bd.tcl b/library/axi_ad9680/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9680/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9684/axi_ad9684.v b/library/axi_ad9684/axi_ad9684.v index 776b49dac..bb8de7093 100644 --- a/library/axi_ad9684/axi_ad9684.v +++ b/library/axi_ad9684/axi_ad9684.v @@ -38,7 +38,10 @@ module axi_ad9684 #( parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter OR_STATUS = 1) ( @@ -163,7 +166,7 @@ module axi_ad9684 #( // device interface instance axi_ad9684_if #( - .DEVICE_TYPE(DEVICE_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .IO_DELAY_GROUP(IO_DELAY_GROUP), .OR_STATUS (OR_STATUS)) i_ad9684_if ( @@ -204,7 +207,11 @@ module axi_ad9684 #( assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1]; up_adc_common #( - .ID(ID), + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (0), .COMMON_ID (6'h00), .DRP_DISABLE (6'h00), diff --git a/library/axi_ad9684/axi_ad9684_hw.tcl b/library/axi_ad9684/axi_ad9684_hw.tcl index 3b8655ac9..c01ba73ed 100644 --- a/library/axi_ad9684/axi_ad9684_hw.tcl +++ b/library/axi_ad9684/axi_ad9684_hw.tcl @@ -1,9 +1,13 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab +set_module_property VALIDATION_CALLBACK info_param_validate + ad_ip_files axi_ad9684 [list \ $ad_hdl_dir/library/common/ad_rst.v \ $ad_hdl_dir/library/common/ad_datafmt.v \ @@ -36,13 +40,13 @@ set_parameter_property ID DESCRIPTION "Instance ID" set_parameter_property ID UNITS None set_parameter_property ID HDL_PARAMETER true -add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE -set_parameter_property DEVICE_TYPE TYPE INTEGER -set_parameter_property DEVICE_TYPE DESCRIPTION "Specify the FPGA device type" -set_parameter_property DEVICE_TYPE UNITS None -set_parameter_property DEVICE_TYPE HDL_PARAMETER true +add_parameter FPGA_TECHNOLOGY INTEGER 0 +set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0 +set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY +set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER +set_parameter_property FPGA_TECHNOLOGY DESCRIPTION "Specify the FPGA device type" +set_parameter_property FPGA_TECHNOLOGY UNITS None +set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true add_parameter OR_STATUS INTEGER 1 set_parameter_property OR_STATUS DEFAULT_VALUE 1 @@ -52,6 +56,8 @@ set_parameter_property OR_STATUS DESCRIPTION "This parameter enables the OVER RA set_parameter_property OR_STATUS UNITS None set_parameter_property OR_STATUS HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_ad9684/axi_ad9684_if.v b/library/axi_ad9684/axi_ad9684_if.v index fde09f9ba..b74520e4b 100644 --- a/library/axi_ad9684/axi_ad9684_if.v +++ b/library/axi_ad9684/axi_ad9684_if.v @@ -37,7 +37,7 @@ module axi_ad9684_if #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter OR_STATUS = 0) ( @@ -106,7 +106,7 @@ module axi_ad9684_if #( // data interface ad_serdes_in #( - .DEVICE_TYPE(DEVICE_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .IODELAY_CTRL(1), .IODELAY_GROUP(IO_DELAY_GROUP), .DDR_OR_SDR_N(DDR_OR_SDR_N), @@ -139,7 +139,7 @@ module axi_ad9684_if #( generate if (OR_STATUS == 1) begin ad_serdes_in #( - .DEVICE_TYPE(DEVICE_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), .IODELAY_CTRL(0), .IODELAY_GROUP(IO_DELAY_GROUP), .DDR_OR_SDR_N(DDR_OR_SDR_N), @@ -183,7 +183,7 @@ module axi_ad9684_if #( // clock input buffers and MMCM_OR_BUFR_N ad_serdes_clk #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .MMCM_CLKIN_PERIOD (2), .MMCM_VCO_DIV (6), .MMCM_VCO_MUL (12), diff --git a/library/axi_ad9684/axi_ad9684_ip.tcl b/library/axi_ad9684/axi_ad9684_ip.tcl index a466ea03c..f909ee9c4 100644 --- a/library/axi_ad9684/axi_ad9684_ip.tcl +++ b/library/axi_ad9684/axi_ad9684_ip.tcl @@ -27,10 +27,13 @@ adi_ip_files axi_ad9684 [list \ "axi_ad9684_if.v" \ "axi_ad9684_channel.v" \ "axi_ad9684_constr.xdc" \ - "axi_ad9684.v"] + "axi_ad9684.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9684 +adi_ip_bd axi_ad9684 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] @@ -39,4 +42,7 @@ ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9684/bd/bd.tcl b/library/axi_ad9684/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9684/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9739a/axi_ad9739a.v b/library/axi_ad9739a/axi_ad9739a.v index b62bcc209..621360b7c 100644 --- a/library/axi_ad9739a/axi_ad9739a.v +++ b/library/axi_ad9739a/axi_ad9739a.v @@ -38,7 +38,10 @@ module axi_ad9739a #( parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter SERDES_OR_DDR_N = 1, parameter MMCM_OR_BUFIO_N = 1, parameter DAC_DDS_TYPE = 2, @@ -132,7 +135,7 @@ module axi_ad9739a #( // device interface - axi_ad9739a_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if ( + axi_ad9739a_if #(.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_if ( .dac_clk_in_p (dac_clk_in_p), .dac_clk_in_n (dac_clk_in_n), .dac_clk_out_p (dac_clk_out_p), @@ -166,6 +169,10 @@ module axi_ad9739a #( axi_ad9739a_core #( .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), diff --git a/library/axi_ad9739a/axi_ad9739a_core.v b/library/axi_ad9739a/axi_ad9739a_core.v index d64799e88..e0e858d44 100644 --- a/library/axi_ad9739a/axi_ad9739a_core.v +++ b/library/axi_ad9739a/axi_ad9739a_core.v @@ -38,6 +38,10 @@ module axi_ad9739a_core #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 16, parameter DAC_DDS_CORDIC_PHASE_DW = 16, @@ -161,7 +165,13 @@ module axi_ad9739a_core #( // dac common processor interface - up_dac_common #(.ID(ID)) i_up_dac_common ( + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_dac_common ( .mmcm_rst (), .dac_clk (dac_div_clk), .dac_rst (dac_rst), diff --git a/library/axi_ad9739a/axi_ad9739a_if.v b/library/axi_ad9739a/axi_ad9739a_if.v index 77b0a3781..821451c68 100644 --- a/library/axi_ad9739a/axi_ad9739a_if.v +++ b/library/axi_ad9739a/axi_ad9739a_if.v @@ -39,7 +39,7 @@ module axi_ad9739a_if #( - parameter DEVICE_TYPE = 0) ( + parameter FPGA_TECHNOLOGY = 0) ( // dac interface @@ -102,7 +102,7 @@ module axi_ad9739a_if #( .DDR_OR_SDR_N(1), .DATA_WIDTH(14), .SERDES_FACTOR(8), - .DEVICE_TYPE (DEVICE_TYPE)) + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_serdes_out_data_a ( .rst (dac_rst), .clk (dac_clk), @@ -126,7 +126,7 @@ module axi_ad9739a_if #( .DDR_OR_SDR_N(1), .DATA_WIDTH(14), .SERDES_FACTOR(8), - .DEVICE_TYPE (DEVICE_TYPE)) + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_serdes_out_data_b ( .rst (dac_rst), .clk (dac_clk), @@ -150,7 +150,7 @@ module axi_ad9739a_if #( .DDR_OR_SDR_N(1), .DATA_WIDTH(1), .SERDES_FACTOR(8), - .DEVICE_TYPE (DEVICE_TYPE)) + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_serdes_out_clk ( .rst (dac_rst), .clk (dac_clk), diff --git a/library/axi_ad9739a/axi_ad9739a_ip.tcl b/library/axi_ad9739a/axi_ad9739a_ip.tcl index 836f10b58..bf8c9fbe4 100644 --- a/library/axi_ad9739a/axi_ad9739a_ip.tcl +++ b/library/axi_ad9739a/axi_ad9739a_ip.tcl @@ -27,11 +27,17 @@ adi_ip_files axi_ad9739a [list \ "axi_ad9739a_channel.v" \ "axi_ad9739a_core.v" \ "axi_ad9739a_if.v" \ - "axi_ad9739a.v" ] + "axi_ad9739a.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9739a +adi_ip_bd axi_ad9739a "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9739a/bd/bd.tcl b/library/axi_ad9739a/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9739a/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v index 5a9f040ac..57c83b7c2 100644 --- a/library/axi_ad9963/axi_ad9963.v +++ b/library/axi_ad9963/axi_ad9963.v @@ -40,7 +40,10 @@ module axi_ad9963 #( // parameters parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter ADC_IODELAY_ENABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group", parameter IODELAY_ENABLE = 0, @@ -177,7 +180,7 @@ module axi_ad9963 #( // device interface axi_ad9963_if #( - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IO_DELAY_GROUP (IO_DELAY_GROUP)) i_dev_if ( @@ -210,6 +213,10 @@ module axi_ad9963 #( axi_ad9963_rx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE), @@ -251,6 +258,10 @@ module axi_ad9963 #( axi_ad9963_tx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DAC_DDS_TYPE (DAC_DDS_TYPE), .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v index 7ddf8e029..7af6de605 100644 --- a/library/axi_ad9963/axi_ad9963_if.v +++ b/library/axi_ad9963/axi_ad9963_if.v @@ -39,7 +39,7 @@ module axi_ad9963_if #( // this parameter controls the buffer type based on the target device. - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter ADC_IODELAY_ENABLE = 0, parameter IO_DELAY_GROUP = "dev_if_delay_group") ( @@ -153,7 +153,7 @@ module axi_ad9963_if #( for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data ad_data_in #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IODELAY_CTRL (0), .IODELAY_GROUP (IO_DELAY_GROUP)) @@ -177,7 +177,7 @@ module axi_ad9963_if #( ad_data_in #( .SINGLE_ENDED (1), - .DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .IODELAY_ENABLE (ADC_IODELAY_ENABLE), .IODELAY_CTRL (1), .IODELAY_GROUP (IO_DELAY_GROUP)) diff --git a/library/axi_ad9963/axi_ad9963_ip.tcl b/library/axi_ad9963/axi_ad9963_ip.tcl index 999655840..938f4f85a 100644 --- a/library/axi_ad9963/axi_ad9963_ip.tcl +++ b/library/axi_ad9963/axi_ad9963_ip.tcl @@ -38,10 +38,13 @@ adi_ip_files axi_ad9963 [list \ "axi_ad9963_rx.v" \ "axi_ad9963_tx_channel.v" \ "axi_ad9963_tx.v" \ - "axi_ad9963.v" ] + "axi_ad9963.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_ad9963 +adi_ip_bd axi_ad9963 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] @@ -59,5 +62,8 @@ ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_c ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v index bfec84dc3..ba055727a 100644 --- a/library/axi_ad9963/axi_ad9963_rx.v +++ b/library/axi_ad9963/axi_ad9963_rx.v @@ -45,7 +45,11 @@ module axi_ad9963_rx #( parameter IQCORRECTION_DISABLE = 0, parameter SCALECORRECTION_ONLY = 1, parameter IODELAY_ENABLE = 0, - parameter ID = 0) ( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0) ( // adc interface @@ -209,6 +213,10 @@ module axi_ad9963_rx #( up_adc_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG (CONFIG), .COMMON_ID(6'h00), .DRP_DISABLE (1), diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v index c0e926baa..131c340be 100644 --- a/library/axi_ad9963/axi_ad9963_tx.v +++ b/library/axi_ad9963/axi_ad9963_tx.v @@ -40,6 +40,10 @@ module axi_ad9963_tx #( // parameters parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DAC_DDS_TYPE = 1, parameter DAC_DDS_CORDIC_DW = 14, parameter DAC_DDS_CORDIC_PHASE_DW = 13, @@ -186,6 +190,10 @@ module axi_ad9963_tx #( up_dac_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG(0), .CLK_EDGE_SEL(0), .COMMON_ID(6'h10), diff --git a/library/axi_ad9963/bd/bd.tcl b/library/axi_ad9963/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_ad9963/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_adrv9009/axi_adrv9009.v b/library/axi_adrv9009/axi_adrv9009.v index 86a172061..4ec157ff3 100644 --- a/library/axi_adrv9009/axi_adrv9009.v +++ b/library/axi_adrv9009/axi_adrv9009.v @@ -38,6 +38,10 @@ module axi_adrv9009 #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter ADC_DATAPATH_DISABLE = 0, parameter ADC_DATAFORMAT_DISABLE = 0, parameter ADC_DCFILTER_DISABLE = 0, @@ -230,6 +234,10 @@ module axi_adrv9009 #( axi_adrv9009_rx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)) @@ -265,6 +273,10 @@ module axi_adrv9009 #( axi_adrv9009_rx_os #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT)) @@ -302,6 +314,10 @@ module axi_adrv9009 #( axi_adrv9009_tx #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DDS_DISABLE (DAC_DDS_DISABLE_INT), .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT), .DAC_DDS_TYPE (DAC_DDS_TYPE), diff --git a/library/axi_adrv9009/axi_adrv9009_hw.tcl b/library/axi_adrv9009/axi_adrv9009_hw.tcl index fc2f96d0f..151e2fccc 100644 --- a/library/axi_adrv9009/axi_adrv9009_hw.tcl +++ b/library/axi_adrv9009/axi_adrv9009_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI adrv9009 Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_adrv9009 +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -132,6 +135,8 @@ set_parameter_property DAC_IQCORRECTION_DISABLE TYPE INTEGER set_parameter_property DAC_IQCORRECTION_DISABLE UNITS None set_parameter_property DAC_IQCORRECTION_DISABLE HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_adrv9009/axi_adrv9009_ip.tcl b/library/axi_adrv9009/axi_adrv9009_ip.tcl index 93559fe95..600917ec5 100644 --- a/library/axi_adrv9009/axi_adrv9009_ip.tcl +++ b/library/axi_adrv9009/axi_adrv9009_ip.tcl @@ -35,10 +35,13 @@ adi_ip_files axi_adrv9009 [list \ "axi_adrv9009_rx_os.v" \ "axi_adrv9009_tx_channel.v" \ "axi_adrv9009_tx.v" \ - "axi_adrv9009.v" ] + "axi_adrv9009.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_adrv9009 +adi_ip_bd axi_adrv9009 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] @@ -50,5 +53,8 @@ ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_c ipx::infer_bus_interface adc_os_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_adrv9009/axi_adrv9009_rx.v b/library/axi_adrv9009/axi_adrv9009_rx.v index 618d8756d..a548243bc 100644 --- a/library/axi_adrv9009/axi_adrv9009_rx.v +++ b/library/axi_adrv9009/axi_adrv9009_rx.v @@ -38,6 +38,10 @@ module axi_adrv9009_rx #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DATAFORMAT_DISABLE = 0, parameter DCFILTER_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0) ( @@ -272,6 +276,10 @@ module axi_adrv9009_rx #( up_adc_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .COMMON_ID (6'h00), .CONFIG(CONFIG), .DRP_DISABLE(1), diff --git a/library/axi_adrv9009/axi_adrv9009_rx_os.v b/library/axi_adrv9009/axi_adrv9009_rx_os.v index 8e3f0e75b..359a05055 100644 --- a/library/axi_adrv9009/axi_adrv9009_rx_os.v +++ b/library/axi_adrv9009/axi_adrv9009_rx_os.v @@ -38,6 +38,10 @@ module axi_adrv9009_rx_os #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DATAFORMAT_DISABLE = 0, parameter DCFILTER_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0) ( @@ -262,6 +266,10 @@ module axi_adrv9009_rx_os #( up_adc_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .COMMON_ID ('h20), .CONFIG (CONFIG), .DRP_DISABLE (1), diff --git a/library/axi_adrv9009/axi_adrv9009_tx.v b/library/axi_adrv9009/axi_adrv9009_tx.v index 1e0180525..73950d2b9 100644 --- a/library/axi_adrv9009/axi_adrv9009_tx.v +++ b/library/axi_adrv9009/axi_adrv9009_tx.v @@ -38,6 +38,10 @@ module axi_adrv9009_tx #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter DISABLE = 0, parameter DDS_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0, @@ -269,6 +273,10 @@ module axi_adrv9009_tx #( up_dac_common #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .CONFIG(CONFIG), .CLK_EDGE_SEL(0), .COMMON_ID(6'h10), diff --git a/library/axi_adrv9009/bd/bd.tcl b/library/axi_adrv9009/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_adrv9009/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index 582495e7d..97d7c623c 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -39,7 +39,11 @@ module axi_clkgen #( parameter ID = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter FPGA_VOLTAGE = 0, parameter CLKSEL_EN = 0, parameter real CLKIN_PERIOD = 5.000, parameter real CLKIN2_PERIOD = 5.000, @@ -147,7 +151,12 @@ module axi_clkgen #( // processor interface up_clkgen #( - .ID(ID) + .ID(ID), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .FPGA_VOLTAGE(FPGA_VOLTAGE) ) i_up_clkgen ( .mmcm_rst (mmcm_rst), .clk_sel (up_clk_sel_s), @@ -182,7 +191,7 @@ module axi_clkgen #( // mmcm instantiations ad_mmcm_drp #( - .MMCM_DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .MMCM_CLKIN_PERIOD (CLKIN_PERIOD), .MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD), .MMCM_VCO_DIV (VCO_DIV), diff --git a/library/axi_clkgen/axi_clkgen_ip.tcl b/library/axi_clkgen/axi_clkgen_ip.tcl index f6ab698fd..7adcc6def 100644 --- a/library/axi_clkgen/axi_clkgen_ip.tcl +++ b/library/axi_clkgen/axi_clkgen_ip.tcl @@ -9,11 +9,13 @@ adi_ip_files axi_clkgen [list \ "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ "$ad_hdl_dir/library/common/up_clkgen.v" \ + "$ad_hdl_dir/library/scripts/common_bd.tcl" \ + "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ "bd/bd.tcl" \ "axi_clkgen.v" ] adi_ip_properties axi_clkgen -adi_ip_bd axi_clkgen "bd/bd.tcl" +adi_ip_bd axi_clkgen "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] @@ -41,6 +43,9 @@ set_property -dict [list \ widget {checkBox} \ ] $param +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc] set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc] set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc] diff --git a/library/axi_clkgen/bd/bd.tcl b/library/axi_clkgen/bd/bd.tcl index 4e92dab38..b35131c77 100644 --- a/library/axi_clkgen/bd/bd.tcl +++ b/library/axi_clkgen/bd/bd.tcl @@ -1,8 +1,23 @@ + proc init {cellpath otherInfo} { set ip [get_bd_cells $cellpath] bd::mark_propagate_override $ip \ - "CLKIN_PERIOD CLKIN2_PERIOD" + "CLKIN_PERIOD \ + CLKIN2_PERIOD \ + FPGA_VOLTAGE" + + bd::mark_propagate_only $ip \ + "FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE \ + FPGA_VOLTAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath } proc axi_clkgen_get_infer_period {ip param clk_name} { diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v index d7905e8a4..6d642d1d3 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync.v @@ -38,7 +38,13 @@ `timescale 1ns/100ps -module axi_fmcadc5_sync #(parameter integer ID = 0) ( +module axi_fmcadc5_sync #( + + parameter integer ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0) ( // receive interface @@ -575,6 +581,7 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( 14'h0001: up_rdata <= ID; 14'h0002: up_rdata <= up_scratch; 14'h0003: up_rdata <= up_timer; + 14'h0007: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] 14'h0010: up_rdata <= {31'd0, up_spi_req}; 14'h0011: up_rdata <= {31'd0, up_spi_gnt}; 14'h0012: up_rdata <= {24'd0, up_spi_csn}; @@ -757,7 +764,7 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) ( assign rx_sysref = rx_sysref_i; ad_data_out #( - .DEVICE_TYPE (0), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .SINGLE_ENDED (0), .IODELAY_ENABLE (1), .IODELAY_CTRL (1), diff --git a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl index 3293d843a..c4dbd02d2 100644 --- a/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl +++ b/library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl @@ -10,14 +10,20 @@ adi_ip_files axi_fmcadc5_sync [list \ "$ad_hdl_dir/library/common/up_axi.v" \ "axi_fmcadc5_sync_constr.xdc" \ "axi_fmcadc5_sync_calcor.v" \ - "axi_fmcadc5_sync.v" ] + "axi_fmcadc5_sync.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_fmcadc5_sync +adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface delay_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_fmcadc5_sync/bd/bd.tcl b/library/axi_fmcadc5_sync/bd/bd.tcl new file mode 100644 index 000000000..d4f012dd5 --- /dev/null +++ b/library/axi_fmcadc5_sync/bd/bd.tcl @@ -0,0 +1,16 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/axi_hdmi_tx/axi_hdmi_tx.v b/library/axi_hdmi_tx/axi_hdmi_tx.v index 6eb756996..ab49a0daa 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx.v @@ -39,7 +39,7 @@ module axi_hdmi_tx #( parameter ID = 0, parameter CR_CB_N = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter INTERFACE = "16_BIT", parameter OUT_CLK_POLARITY = 0) ( @@ -105,9 +105,9 @@ module axi_hdmi_tx #( /* 0 = Launch on rising edge, 1 = Launch on falling edge */ localparam EMBEDDED_SYNC = (INTERFACE == "16_BIT_EMBEDDED_SYNC") ? 1 : 0; - localparam XILINX_7SERIES = 0; - localparam XILINX_ULTRASCALE = 1; - localparam ALTERA_5SERIES = 16; + localparam XILINX_7SERIES = 1; + localparam XILINX_ULTRASCALE = 2; + localparam ALTERA_5SERIES = 101; // reset and clocks @@ -302,7 +302,7 @@ module axi_hdmi_tx #( // hdmi output clock generate - if (DEVICE_TYPE == XILINX_ULTRASCALE) begin + if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE) begin ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr ( .SR (1'b0), .D1 (~OUT_CLK_POLARITY), @@ -310,7 +310,7 @@ module axi_hdmi_tx #( .C (hdmi_clk), .Q (hdmi_out_clk)); end - if (DEVICE_TYPE == ALTERA_5SERIES) begin + if (FPGA_TECHNOLOGY == ALTERA_5SERIES) begin altddio_out #(.WIDTH(1)) i_clk_oddr ( .aclr (1'b0), .aset (1'b0), @@ -324,7 +324,7 @@ module axi_hdmi_tx #( .oe_out (), .dataout (hdmi_out_clk)); end - if (DEVICE_TYPE == XILINX_7SERIES) begin + if (FPGA_TECHNOLOGY == XILINX_7SERIES) begin ODDR #(.INIT(1'b0)) i_clk_oddr ( .R (1'b0), .S (1'b0), diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl index 08d41aa29..4071a47bd 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl +++ b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl @@ -1,6 +1,8 @@ package require qsys +package require quartus::device + source ../scripts/adi_env.tcl source ../scripts/adi_ip_alt.tcl @@ -9,6 +11,7 @@ set_module_property DESCRIPTION "AXI HDMI Transmit Interface" set_module_property VERSION 1.0 set_module_property GROUP "Analog Devices" set_module_property DISPLAY_NAME axi_hdmi_tx +set_module_property VALIDATION_CALLBACK info_param_validate # files @@ -51,12 +54,12 @@ set_parameter_property CR_CB_N TYPE INTEGER set_parameter_property CR_CB_N UNITS None set_parameter_property CR_CB_N HDL_PARAMETER true -add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 16 -set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE -set_parameter_property DEVICE_TYPE TYPE INTEGER -set_parameter_property DEVICE_TYPE UNITS None -set_parameter_property DEVICE_TYPE HDL_PARAMETER true +add_parameter FPGA_TECHNOLOGY INTEGER 0 +set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 16 +set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY +set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER +set_parameter_property FPGA_TECHNOLOGY UNITS None +set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true add_parameter EMBEDDED_SYNC INTEGER 0 set_parameter_property EMBEDDED_SYNC DEFAULT_VALUE 0 @@ -65,6 +68,8 @@ set_parameter_property EMBEDDED_SYNC TYPE INTEGER set_parameter_property EMBEDDED_SYNC UNITS None set_parameter_property EMBEDDED_SYNC HDL_PARAMETER true +adi_add_auto_fpga_spec_params + # axi4 slave ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl index 09c18e22b..ae975f823 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl +++ b/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl @@ -24,10 +24,13 @@ adi_ip_files axi_hdmi_tx [list \ "axi_hdmi_tx_vdma.v" \ "axi_hdmi_tx_es.v" \ "axi_hdmi_tx_core.v" \ - "axi_hdmi_tx.v" ] + "axi_hdmi_tx.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_hdmi_tx +adi_ip_bd axi_ad9122 "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]] @@ -66,5 +69,9 @@ ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_ ipx::associate_bus_interfaces -busif s_axis -clock vdma_clk [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/axi_hdmi_tx/bd/bd.tcl b/library/axi_hdmi_tx/bd/bd.tcl new file mode 100644 index 000000000..b90113ec1 --- /dev/null +++ b/library/axi_hdmi_tx/bd/bd.tcl @@ -0,0 +1,50 @@ +## *************************************************************************** +## *************************************************************************** +## Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved. +## +## In this HDL repository, there are many different and unique modules, consisting +## of various HDL (Verilog or VHDL) components. The individual modules are +## developed independently, and may be accompanied by separate and unique license +## terms. +## +## The user should read each of these license terms, and understand the +## freedoms and responsibilities that he or she has by using this source/core. +## +## This core is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +## A PARTICULAR PURPOSE. +## +## Redistribution and use of source or resulting binaries, with or without modification +## of this file, are permitted under one of the following two license terms: +## +## 1. The GNU General Public License version 2 as published by the +## Free Software Foundation, which can be found in the top level directory +## of this repository (LICENSE_GPL2), and also online at: +## +## +## OR +## +## 2. An ADI specific BSD license, which can be found in the top level directory +## of this repository (LICENSE_ADIBSD), and also on-line at: +## https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +## This will allow to generate bit files and not release the source code, +## as long as it attaches to an ADI device. +## +## *************************************************************************** +## *************************************************************************** + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index aaccfdd7f..f556a1ba8 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -39,13 +39,17 @@ module up_adc_common #( // parameters - parameter ID = 0, - parameter CONFIG = 0, - parameter COMMON_ID = 6'h00, - parameter DRP_DISABLE = 0, - parameter USERPORTS_DISABLE = 0, - parameter GPIO_DISABLE = 0, - parameter START_CODE_DISABLE = 0) ( + parameter ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter CONFIG = 0, + parameter COMMON_ID = 6'h00, + parameter DRP_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter GPIO_DISABLE = 0, + parameter START_CODE_DISABLE = 0) ( // clock reset @@ -373,6 +377,7 @@ module up_adc_common #( 7'h02: up_rdata_int <= up_scratch; 7'h03: up_rdata_int <= CONFIG; 7'h04: up_rdata_int <= {31'b0, up_pps_irq_mask}; + 7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] 7'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn}; 7'h11: up_rdata_int <= {27'd0, up_adc_sref_sync, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; diff --git a/library/common/up_clkgen.v b/library/common/up_clkgen.v index 0837c526f..43f0ef873 100644 --- a/library/common/up_clkgen.v +++ b/library/common/up_clkgen.v @@ -37,7 +37,12 @@ module up_clkgen #( - parameter ID = 0) ( + parameter ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0) ( // mmcm reset @@ -161,11 +166,13 @@ module up_clkgen #( 8'h00: up_rdata <= PCORE_VERSION; 8'h01: up_rdata <= ID; 8'h02: up_rdata <= up_scratch; + 8'h07: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h11: up_rdata <= {31'd0, up_clk_sel}; 8'h17: up_rdata <= {31'd0, up_drp_locked}; 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; 8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold}; + 8'h50: up_rdata <= {16'd0, FPGA_VOLTAGE}; // mV default: up_rdata <= 0; endcase end else begin diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index b1c886ca3..1e3bc4535 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -39,13 +39,17 @@ module up_dac_common #( // parameters - parameter ID = 0, - parameter CONFIG = 0, - parameter CLK_EDGE_SEL = 1'b0, - parameter COMMON_ID = 6'h10, - parameter DRP_DISABLE = 0, - parameter USERPORTS_DISABLE = 0, - parameter GPIO_DISABLE = 0) ( + parameter ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter CONFIG = 0, + parameter CLK_EDGE_SEL = 1'b0, + parameter COMMON_ID = 6'h10, + parameter DRP_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter GPIO_DISABLE = 0) ( // mmcm reset @@ -376,6 +380,7 @@ module up_dac_common #( 7'h01: up_rdata_int <= ID; 7'h02: up_rdata_int <= up_scratch; 7'h03: up_rdata_int <= CONFIG; + 7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] 7'h10: up_rdata_int <= {29'd0, up_dac_clk_enb, up_mmcm_resetn, up_resetn}; 7'h11: up_rdata_int <= {31'd0, up_dac_sync}; 7'h12: up_rdata_int <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v index 27cfa77bd..26b40f912 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v @@ -25,6 +25,10 @@ module ad_ip_jesd204_tpl_adc #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter NUM_LANES = 1, parameter NUM_CHANNELS = 4, parameter SAMPLES_PER_FRAME = 1, @@ -98,6 +102,10 @@ module ad_ip_jesd204_tpl_adc #( // regmap ad_ip_jesd204_tpl_adc_regmap #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_CHANNELS (NUM_CHANNELS), .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .NUM_PROFILES(1) diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index 9cf294226..1a831c13a 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -25,6 +25,10 @@ module ad_ip_jesd204_tpl_adc_regmap #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter NUM_CHANNELS = 1, parameter DATA_PATH_WIDTH = 1, parameter NUM_PROFILES = 1 // Number of supported JESD profiles @@ -194,6 +198,10 @@ module ad_ip_jesd204_tpl_adc_regmap #( up_adc_common #( .COMMON_ID (6'h0), .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DRP_DISABLE (1), .USERPORTS_DISABLE (1), .GPIO_DISABLE (1), diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v index 8b1cfa025..4c28529c3 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v @@ -25,6 +25,10 @@ module ad_ip_jesd204_tpl_dac #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter NUM_LANES = 4, parameter NUM_CHANNELS = 2, parameter SAMPLES_PER_FRAME = 1, @@ -106,6 +110,10 @@ module ad_ip_jesd204_tpl_dac #( ad_ip_jesd204_tpl_dac_regmap #( .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .NUM_CHANNELS (NUM_CHANNELS), .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .NUM_PROFILES(1) diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl index a1f549108..a968ca195 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl @@ -60,6 +60,8 @@ set cc [ipx::current_core] set_property display_name "JESD204 Transport Layer for DACs" $cc set_property description "JESD204 Transport Layer for DACs" $cc +# ADD missing stuff ####################################################### + adi_add_bus "link" "master" \ "xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis:1.0" \ diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v index 81dbee4f2..6c8bd40e8 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -25,6 +25,10 @@ module ad_ip_jesd204_tpl_dac_regmap #( parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, parameter NUM_CHANNELS = 2, parameter DATA_PATH_WIDTH = 16, parameter NUM_PROFILES = 1 // Number of supported JESD profiles @@ -176,6 +180,10 @@ module ad_ip_jesd204_tpl_dac_regmap #( up_dac_common #( .COMMON_ID(6'h0), .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), .DRP_DISABLE (1), .USERPORTS_DISABLE (1), .GPIO_DISABLE (1) diff --git a/library/util_adcfifo/util_adcfifo.v b/library/util_adcfifo/util_adcfifo.v index 9dcc801ff..4306dd6f6 100644 --- a/library/util_adcfifo/util_adcfifo.v +++ b/library/util_adcfifo/util_adcfifo.v @@ -37,7 +37,7 @@ module util_adcfifo #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter ADC_DATA_WIDTH = 256, parameter DMA_DATA_WIDTH = 64, parameter DMA_READY_ENABLE = 1, @@ -200,7 +200,7 @@ module util_adcfifo #( // instantiations generate - if (DEVICE_TYPE == 1) begin + if (FPGA_TECHNOLOGY == 1) begin alt_mem_asym i_mem_asym ( .mem_i_wrclock (adc_clk), .mem_i_wren (adc_wr_int), diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl index 74d1b4fe3..23c4c7d26 100644 --- a/library/util_adcfifo/util_adcfifo_hw.tcl +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -17,7 +17,7 @@ ad_ip_files util_adcfifo [list\ # parameters ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} -ad_ip_parameter DEVICE_TYPE INTEGER 1 +ad_ip_parameter FPGA_TECHNOLOGY INTEGER 1 ad_ip_parameter ADC_DATA_WIDTH INTEGER 256 ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 ad_ip_parameter DMA_READY_ENABLE INTEGER 1 diff --git a/library/xilinx/axi_adxcvr/Makefile b/library/xilinx/axi_adxcvr/Makefile index c0d3b255f..b63d1880f 100644 --- a/library/xilinx/axi_adxcvr/Makefile +++ b/library/xilinx/axi_adxcvr/Makefile @@ -12,6 +12,7 @@ XILINX_DEPS += axi_adxcvr_ip.tcl XILINX_DEPS += axi_adxcvr_mdrp.v XILINX_DEPS += axi_adxcvr_mstatus.v XILINX_DEPS += axi_adxcvr_up.v +XILINX_DEPS += bd/bd.tcl XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v index dc57a60c9..4381a3700 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v @@ -43,6 +43,11 @@ module axi_adxcvr #( parameter integer ID = 0, parameter integer NUM_OF_LANES = 8, parameter integer XCVR_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, parameter integer TX_OR_RX_N = 0, parameter integer QPLL_ENABLE = 1, parameter LPM_OR_DFE_N = 1, @@ -1855,6 +1860,11 @@ module axi_adxcvr #( .ID (ID), .NUM_OF_LANES (NUM_OF_LANES), .XCVR_TYPE (XCVR_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .FPGA_VOLTAGE(FPGA_VOLTAGE), .TX_OR_RX_N (TX_OR_RX_N), .QPLL_ENABLE (QPLL_ENABLE), .LPM_OR_DFE_N (LPM_OR_DFE_N), diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v index f201bd4f0..eec19c9f2 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_es.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_es.v @@ -88,14 +88,20 @@ module axi_adxcvr_es ( parameter integer XCVR_TYPE = 0; parameter integer TX_OR_RX_N = 0; + // local parameters + + localparam GTXE2 = 2; + localparam GTHE3 = 5; + localparam GTHE4 = 8; + // addresses - localparam [11:0] ES_DRP_CTRL_ADDR = (XCVR_TYPE == 0) ? 12'h03d : (XCVR_TYPE == 1) ? 12'h03c : 12'h03c; - localparam [11:0] ES_DRP_HOFFSET_ADDR = (XCVR_TYPE == 0) ? 12'h03c : (XCVR_TYPE == 1) ? 12'h04f : 12'h04f; - localparam [11:0] ES_DRP_VOFFSET_ADDR = (XCVR_TYPE == 0) ? 12'h03b : (XCVR_TYPE == 1) ? 12'h097 : 12'h097; - localparam [11:0] ES_DRP_STATUS_ADDR = (XCVR_TYPE == 0) ? 12'h151 : (XCVR_TYPE == 1) ? 12'h153 : 12'h253; - localparam [11:0] ES_DRP_SCNT_ADDR = (XCVR_TYPE == 0) ? 12'h150 : (XCVR_TYPE == 1) ? 12'h152 : 12'h252; - localparam [11:0] ES_DRP_ECNT_ADDR = (XCVR_TYPE == 0) ? 12'h14f : (XCVR_TYPE == 1) ? 12'h151 : 12'h251; + localparam [11:0] ES_DRP_CTRL_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03d : (XCVR_TYPE == GTHE3) ? 12'h03c : 12'h03c; + localparam [11:0] ES_DRP_HOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03c : (XCVR_TYPE == GTHE3) ? 12'h04f : 12'h04f; + localparam [11:0] ES_DRP_VOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03b : (XCVR_TYPE == GTHE3) ? 12'h097 : 12'h097; + localparam [11:0] ES_DRP_STATUS_ADDR = (XCVR_TYPE == GTXE2) ? 12'h151 : (XCVR_TYPE == GTHE3) ? 12'h153 : 12'h253; + localparam [11:0] ES_DRP_SCNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h150 : (XCVR_TYPE == GTHE3) ? 12'h152 : 12'h252; + localparam [11:0] ES_DRP_ECNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h14f : (XCVR_TYPE == GTHE3) ? 12'h151 : 12'h251; // fsm-states @@ -483,7 +489,7 @@ module axi_adxcvr_es ( up_enb <= 1'b1; up_addr <= ES_DRP_HOFFSET_ADDR; up_wr <= 1'b1; - if (XCVR_TYPE != 0) begin + if (XCVR_TYPE != GTXE2) begin up_data <= {up_hindex, up_hdata[3:0]}; end else begin up_data <= {up_hdata[15:12], up_hindex}; @@ -499,7 +505,7 @@ module axi_adxcvr_es ( up_enb <= 1'b1; up_addr <= ES_DRP_VOFFSET_ADDR; up_wr <= 1'b1; - if (XCVR_TYPE != 0) begin + if (XCVR_TYPE != GTXE2) begin up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange}; end else begin up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s}; @@ -515,7 +521,7 @@ module axi_adxcvr_es ( up_enb <= 1'b1; up_addr <= ES_DRP_CTRL_ADDR; up_wr <= 1'b1; - if (XCVR_TYPE != 0) begin + if (XCVR_TYPE != GTXE2) begin up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale}; end else begin up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1}; @@ -531,7 +537,7 @@ module axi_adxcvr_es ( up_enb <= 1'b1; up_addr <= ES_DRP_CTRL_ADDR; up_wr <= 1'b1; - if (XCVR_TYPE != 0) begin + if (XCVR_TYPE != GTXE2) begin up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale}; end else begin up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0}; diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl index 4c1333e84..94ea5a532 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl @@ -6,15 +6,20 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create axi_adxcvr adi_ip_files axi_adxcvr [list \ "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/scripts/common_bd.tcl" \ + "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ "axi_adxcvr_es.v" \ "axi_adxcvr_up.v" \ "axi_adxcvr_mdrp.v" \ "axi_adxcvr_mstatus.v" \ - "axi_adxcvr.v" ] + "axi_adxcvr.v" \ + "bd/bd.tcl" ] adi_ip_properties axi_adxcvr adi_ip_infer_mm_interfaces axi_adxcvr +adi_ip_bd axi_adxcvr "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] set_property master_address_space_ref m_axi \ @@ -221,5 +226,8 @@ set_property enablement_dependency \ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \ [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v index 7e3e7f165..254713a98 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v @@ -42,6 +42,11 @@ module axi_adxcvr_up #( parameter integer ID = 0, parameter integer NUM_OF_LANES = 8, parameter integer XCVR_TYPE = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, parameter integer TX_OR_RX_N = 0, parameter integer QPLL_ENABLE = 1, parameter LPM_OR_DFE_N = 1, @@ -120,7 +125,7 @@ module axi_adxcvr_up #( // parameters - localparam [31:0] VERSION = 32'h00100161; + localparam [31:0] VERSION = 32'h00110161; // internal registers @@ -503,6 +508,7 @@ module axi_adxcvr_up #( 10'h004: up_rdata_d <= {31'd0, up_resetn}; 10'h005: up_rdata_d <= {31'd0, up_status_int}; 10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt}; + 10'h007: up_rdata_d <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] 10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel}; 10'h009: up_rdata_d <= up_rparam_s; 10'h010: up_rdata_d <= {24'd0, up_icm_sel}; @@ -523,6 +529,7 @@ module axi_adxcvr_up #( 10'h030: up_rdata_d <= up_tx_diffctrl; 10'h031: up_rdata_d <= up_tx_postcursor; 10'h032: up_rdata_d <= up_tx_precursor; + 10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV default: up_rdata_d <= 32'd0; endcase end else begin diff --git a/library/xilinx/axi_adxcvr/bd/bd.tcl b/library/xilinx/axi_adxcvr/bd/bd.tcl new file mode 100644 index 000000000..0b66fc291 --- /dev/null +++ b/library/xilinx/axi_adxcvr/bd/bd.tcl @@ -0,0 +1,20 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip " \ + XCVR_TYPE \ + FPGA_VOLTAGE" + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v index 1254d7631..25752dcd0 100644 --- a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v @@ -241,7 +241,7 @@ module axi_xcvrlb_1 ( .d_data_status ({rx_pn_err_s, rx_pn_oos_s})); util_adxcvr_xch #( - .XCVR_TYPE (0), + .XCVR_TYPE (2), .CPLL_FBDIV (2), .CPLL_FBDIV_4_5 (5), .TX_OUT_DIV (1), diff --git a/library/xilinx/common/ad_data_clk.v b/library/xilinx/common/ad_data_clk.v index 420270918..6eea5cbd4 100644 --- a/library/xilinx/common/ad_data_clk.v +++ b/library/xilinx/common/ad_data_clk.v @@ -37,8 +37,7 @@ module ad_data_clk #( - parameter SINGLE_ENDED = 0, - parameter DEVICE_TYPE = 0) ( + parameter SINGLE_ENDED = 0) ( input rst, output locked, @@ -47,10 +46,6 @@ module ad_data_clk #( input clk_in_n, output clk); - localparam VIRTEX7 = 0; - localparam ULTRASCALE_PLUS = 2; - localparam ULTRASCALE = 3; - // internal signals wire clk_ibuf_s; diff --git a/library/xilinx/common/ad_data_in.v b/library/xilinx/common/ad_data_in.v index a07af2668..7cb21c1e0 100644 --- a/library/xilinx/common/ad_data_in.v +++ b/library/xilinx/common/ad_data_in.v @@ -40,7 +40,7 @@ module ad_data_in #( // parameters parameter SINGLE_ENDED = 0, - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter IODELAY_ENABLE = 1, parameter IODELAY_CTRL = 0, parameter IODELAY_GROUP = "dev_if_delay_group") ( @@ -69,17 +69,17 @@ module ad_data_in #( // internal parameters localparam NONE = -1; - localparam VIRTEX7 = 0; - localparam ULTRASCALE_PLUS = 2; - localparam ULTRASCALE = 3; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0; - localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" : - (DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; - localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE; - localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" : - (DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + localparam IODELAY_FPGA_TECHNOLOGY = (IODELAY_ENABLE == 1) ? FPGA_TECHNOLOGY : NONE; + localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; // internal signals @@ -119,7 +119,7 @@ module ad_data_in #( // idelay generate - if (IODELAY_DEVICE_TYPE == VIRTEX7) begin + if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYE2 #( .CINVCTRL_SEL ("FALSE"), @@ -147,7 +147,7 @@ module ad_data_in #( endgenerate generate - if ((IODELAY_DEVICE_TYPE == ULTRASCALE) || (IODELAY_DEVICE_TYPE == ULTRASCALE_PLUS)) begin + if ((IODELAY_FPGA_TECHNOLOGY == ULTRASCALE) || (IODELAY_FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin assign up_drdata = up_drdata_s[8:4]; (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYE3 #( @@ -175,7 +175,7 @@ module ad_data_in #( endgenerate generate - if (IODELAY_DEVICE_TYPE == NONE) begin + if (IODELAY_FPGA_TECHNOLOGY == NONE) begin assign rx_data_idelay_s = rx_data_ibuf_s; assign up_drdata = 5'd0; end @@ -184,7 +184,7 @@ module ad_data_in #( // iddr generate - if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin + if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr ( .R (1'b0), .C (rx_clk), @@ -196,7 +196,7 @@ module ad_data_in #( endgenerate generate - if (DEVICE_TYPE == VIRTEX7) begin + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr ( .CE (1'b1), .R (1'b0), diff --git a/library/xilinx/common/ad_data_out.v b/library/xilinx/common/ad_data_out.v index e292cabd6..db5ef5bd9 100644 --- a/library/xilinx/common/ad_data_out.v +++ b/library/xilinx/common/ad_data_out.v @@ -37,7 +37,7 @@ module ad_data_out #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter SINGLE_ENDED = 0, parameter IODELAY_ENABLE = 0, parameter IODELAY_CTRL = 0, @@ -65,17 +65,17 @@ module ad_data_out #( output delay_locked); localparam NONE = -1; - localparam VIRTEX7 = 0; - localparam ULTRASCALE_PLUS = 2; - localparam ULTRASCALE = 3; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0; - localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" : - (DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; - localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE; - localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS_ES1" : - (DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + localparam IODELAY_FPGA_TECHNOLOGY = (IODELAY_ENABLE == 1) ? FPGA_TECHNOLOGY : NONE; + localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS_ES1" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; // internal signals @@ -99,7 +99,7 @@ module ad_data_out #( // transmit data interface, oddr -> odelay -> obuf generate - if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin + if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin ODDRE1 i_tx_data_oddr ( .SR (1'b0), .C (tx_clk), @@ -110,7 +110,7 @@ module ad_data_out #( endgenerate generate - if (DEVICE_TYPE == VIRTEX7) begin + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin ODDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_tx_data_oddr ( .CE (1'b1), .R (1'b0), @@ -125,7 +125,7 @@ module ad_data_out #( // odelay generate - if (IODELAY_DEVICE_TYPE == VIRTEX7) begin + if (IODELAY_FPGA_TECHNOLOGY == SEVEN_SERIES) begin (* IODELAY_GROUP = IODELAY_GROUP *) ODELAYE2 #( .CINVCTRL_SEL ("FALSE"), @@ -153,7 +153,7 @@ module ad_data_out #( endgenerate generate - if (IODELAY_DEVICE_TYPE == NONE) begin + if (IODELAY_FPGA_TECHNOLOGY == NONE) begin assign up_drdata = 5'd0; assign tx_data_odelay_s = tx_data_oddr_s; end diff --git a/library/xilinx/common/ad_mmcm_drp.v b/library/xilinx/common/ad_mmcm_drp.v index 0fc9a702a..4ca57235c 100644 --- a/library/xilinx/common/ad_mmcm_drp.v +++ b/library/xilinx/common/ad_mmcm_drp.v @@ -38,7 +38,7 @@ module ad_mmcm_drp #( - parameter MMCM_DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter MMCM_CLKIN_PERIOD = 1.667, parameter MMCM_CLKIN2_PERIOD = 1.667, parameter MMCM_VCO_DIV = 6, @@ -72,8 +72,9 @@ module ad_mmcm_drp #( output reg up_drp_ready, output reg up_drp_locked); - localparam MMCM_DEVICE_7SERIES = 0; - localparam MMCM_DEVICE_ULTRASCALE = 2; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; // internal registers @@ -110,7 +111,7 @@ module ad_mmcm_drp #( // instantiations generate - if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin MMCME2_ADV #( .BANDWIDTH ("OPTIMIZED"), .CLKOUT4_CASCADE ("FALSE"), @@ -175,7 +176,7 @@ module ad_mmcm_drp #( BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); - end else if (MMCM_DEVICE_TYPE == MMCM_DEVICE_ULTRASCALE) begin + end else if (FPGA_TECHNOLOGY == ULTRASCALE) begin MMCME3_ADV #( .BANDWIDTH ("OPTIMIZED"), .CLKOUT4_CASCADE ("FALSE"), @@ -243,6 +244,73 @@ module ad_mmcm_drp #( BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); + end else if (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin + MMCME4_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("AUTO"), + .STARTUP_WAIT ("FALSE"), + + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD) + ) i_mmcme4 ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .CDDCREQ (1'b0), + .CDDCDONE (), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s)); + BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0)); + BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1)); + BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2)); + end endgenerate diff --git a/library/xilinx/common/ad_serdes_clk.v b/library/xilinx/common/ad_serdes_clk.v index 537429981..c21e68de8 100644 --- a/library/xilinx/common/ad_serdes_clk.v +++ b/library/xilinx/common/ad_serdes_clk.v @@ -38,7 +38,7 @@ module ad_serdes_clk #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DDR_OR_SDR_N = 1, parameter CLKIN_DS_OR_SE_N = 1, parameter SERDES_FACTOR = 8, @@ -102,7 +102,7 @@ module ad_serdes_clk #( generate if (MMCM_OR_BUFR_N == 1) begin ad_mmcm_drp #( - .MMCM_DEVICE_TYPE (DEVICE_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD), .MMCM_VCO_DIV (MMCM_VCO_DIV), diff --git a/library/xilinx/common/ad_serdes_in.v b/library/xilinx/common/ad_serdes_in.v index aa585b8b1..a88810a39 100644 --- a/library/xilinx/common/ad_serdes_in.v +++ b/library/xilinx/common/ad_serdes_in.v @@ -37,7 +37,7 @@ module ad_serdes_in #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DDR_OR_SDR_N = 0, parameter SERDES_FACTOR = 8, parameter DATA_WIDTH = 16, @@ -79,7 +79,9 @@ module ad_serdes_in #( input delay_rst, output delay_locked); - localparam DEVICE_7SERIES = 0; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR"; // internal signals @@ -106,7 +108,7 @@ module ad_serdes_in #( // received data interface: ibuf -> idelay -> iserdes genvar l_inst; - generate if (DEVICE_TYPE == DEVICE_7SERIES) begin + generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data IBUFDS i_ibuf ( diff --git a/library/xilinx/common/ad_serdes_out.v b/library/xilinx/common/ad_serdes_out.v index 354deb7cd..a5937e618 100644 --- a/library/xilinx/common/ad_serdes_out.v +++ b/library/xilinx/common/ad_serdes_out.v @@ -38,7 +38,7 @@ module ad_serdes_out #( - parameter DEVICE_TYPE = 0, + parameter FPGA_TECHNOLOGY = 0, parameter DDR_OR_SDR_N = 1, parameter SERDES_FACTOR = 8, parameter DATA_WIDTH = 16) ( @@ -64,7 +64,9 @@ module ad_serdes_out #( output [(DATA_WIDTH-1):0] data_out_p, output [(DATA_WIDTH-1):0] data_out_n); - localparam DEVICE_7SERIES = 0; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR"; // internal signals @@ -81,7 +83,7 @@ module ad_serdes_out #( generate for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data - if (DEVICE_TYPE == DEVICE_7SERIES) begin + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin OSERDESE2 #( .DATA_RATE_OQ (DR_OQ_DDR), .DATA_RATE_TQ ("SDR"), diff --git a/library/xilinx/util_adxcvr/Makefile b/library/xilinx/util_adxcvr/Makefile index 9a528bdd7..f56ecb0d5 100644 --- a/library/xilinx/util_adxcvr/Makefile +++ b/library/xilinx/util_adxcvr/Makefile @@ -5,6 +5,7 @@ LIBRARY_NAME := util_adxcvr +XILINX_DEPS += bd/bd.tcl XILINX_DEPS += util_adxcvr.v XILINX_DEPS += util_adxcvr_constr.xdc XILINX_DEPS += util_adxcvr_ip.tcl diff --git a/library/xilinx/util_adxcvr/bd/bd.tcl b/library/xilinx/util_adxcvr/bd/bd.tcl new file mode 100644 index 000000000..4db6ffb9d --- /dev/null +++ b/library/xilinx/util_adxcvr/bd/bd.tcl @@ -0,0 +1,12 @@ + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip "XCVR_TYPE" + + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + source ${ip_path}../../scripts/common_bd.tcl + + adi_auto_assign_device_spec $cellpath +} + diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index ae001e938..0e03253c5 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -38,7 +38,7 @@ module util_adxcvr #( - // gtxe2(0), gthe3(1), gthe4(2) + // gtxe2(2), gthe3(5), gthe4(8) parameter integer XCVR_TYPE = 0, diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl index 1fd5c783b..e54e595c3 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl +++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl @@ -5,13 +5,18 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl adi_ip_create util_adxcvr adi_ip_files util_adxcvr [list \ + "$ad_hdl_dir/library/scripts/common_bd.tcl" \ + "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ "util_adxcvr_constr.xdc" \ "util_adxcvr_xcm.v" \ "util_adxcvr_xch.v" \ - "util_adxcvr.v" ] + "util_adxcvr.v" \ + "bd/bd.tcl"] adi_ip_properties_lite util_adxcvr +adi_ip_bd util_adxcvr "bd/bd.tcl $ad_hdl_dir/library/scripts/common_bd.tcl" + ipx::remove_all_bus_interface [ipx::current_core] ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] @@ -805,5 +810,8 @@ set_property enablement_dependency \ [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \ [ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]] +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + ipx::save_core [ipx::current_core] diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index 5c66d4e3b..411c88a1c 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -136,6 +136,10 @@ module util_adxcvr_xch #( output [15:0] up_tx_rdata, output up_tx_ready); + localparam GTXE2_TRANSCEIVERS = 2; + localparam GTHE3_TRANSCEIVERS = 5; + localparam GTHE4_TRANSCEIVERS = 8; + // internal registers reg [15:0] up_es_rdata_int = 'd0; @@ -291,14 +295,14 @@ module util_adxcvr_xch #( // instantiations generate - if (XCVR_TYPE == 0) begin + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk)); BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk)); end endgenerate generate - if (XCVR_TYPE == 0) begin + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin assign rx_sys_clk_sel_s = up_rx_sys_clk_sel; assign tx_sys_clk_sel_s = up_tx_sys_clk_sel; assign rx_pll_clk_sel_s = 2'd0; @@ -307,7 +311,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 0) begin + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin GTXE2_CHANNEL #( .ALIGN_COMMA_DOUBLE ("FALSE"), .ALIGN_COMMA_ENABLE (10'b1111111111), @@ -751,7 +755,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 1) begin + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin BUFG_GT i_rx_bufg ( .CE (1'b1), .CEMASK (1'b0), @@ -773,7 +777,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 1) begin + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]}; assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]}; assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; @@ -782,7 +786,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 1) begin + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin GTHE3_CHANNEL #( .ACJTAG_DEBUG_MODE (1'b0), .ACJTAG_MODE (1'b0), @@ -1506,7 +1510,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 2) begin + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin BUFG_GT i_rx_bufg ( .CE (1'b1), .CEMASK (1'b0), @@ -1528,7 +1532,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 2) begin + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]}; assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]}; assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; @@ -1537,7 +1541,7 @@ module util_adxcvr_xch #( endgenerate generate - if (XCVR_TYPE == 2) begin + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin GTHE4_CHANNEL #( .ACJTAG_DEBUG_MODE (1'b0), .ACJTAG_MODE (1'b0), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v index 45e07f2d7..a89ff5d4b 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -75,6 +75,10 @@ module util_adxcvr_xcm #( output [15:0] up_cm_rdata, output up_cm_ready); + localparam GTXE2_TRANSCEIVERS = 2; + localparam GTHE3_TRANSCEIVERS = 5; + localparam GTHE4_TRANSCEIVERS = 8; + // internal registers reg up_enb_int = 'd0; @@ -136,7 +140,7 @@ module util_adxcvr_xcm #( // instantiations generate - if (XCVR_TYPE == 0) begin + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin assign qpll1_locked = 1'b0; assign qpll1_clk = 1'b0; assign qpll1_ref_clk = 1'b0; @@ -203,7 +207,7 @@ module util_adxcvr_xcm #( endgenerate generate - if (XCVR_TYPE == 1) begin + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin GTHE3_COMMON #( .BIAS_CFG0 (16'h0000), .BIAS_CFG1 (16'h0000), @@ -349,7 +353,7 @@ module util_adxcvr_xcm #( endgenerate generate - if (XCVR_TYPE == 2) begin + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin GTHE4_COMMON #( .AEN_QPLL0_FBDIV (1'b1), .AEN_QPLL1_FBDIV (1'b1),