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ad7405 : Initial commit 

This project is an inital version of the ADuM7701 (CMOS) or AD7405 (LVDS)
reference board.
main
Istvan Csomortani 2018-01-08 16:13:02 +00:00 committed by István Csomortáni
parent 554feaa1af
commit 6668accc96
14 changed files with 867 additions and 0 deletions
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2
library/Makefile
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@ -94,6 +94,7 @@ clean:
$(MAKE) -C util_cic clean
$(MAKE) -C util_clkdiv clean
$(MAKE) -C util_dacfifo clean
$(MAKE) -C util_dec256sinc24b clean
$(MAKE) -C util_delay clean
$(MAKE) -C util_extract clean
$(MAKE) -C util_fir_dec clean
@ -204,6 +205,7 @@ lib:
$(MAKE) -C util_cic
$(MAKE) -C util_clkdiv
$(MAKE) -C util_dacfifo
$(MAKE) -C util_dec256sinc24b
$(MAKE) -C util_delay
$(MAKE) -C util_extract
$(MAKE) -C util_fir_dec

197
library/common/util_dec256sinc24b.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_dec256sinc24b (
input clk, /* used to clk filter */
input reset, /* used to reset filter */
input data_in, /* input data to be filtered */
output reg [15:0] data_out, /* filtered output */
output reg data_en,
input [15:0] dec_rate);
/* Data is read on positive clk edge */
reg [36:0] data_int = 37'h0;
reg [36:0] acc1 = 37'h0;
reg [36:0] acc2 = 37'h0;
reg [36:0] acc3 = 37'h0;
reg [36:0] acc3_d = 37'h0;
reg [36:0] diff1 = 37'h0;
reg [36:0] diff2 = 37'h0;
reg [36:0] diff3 = 37'h0;
reg [36:0] diff1_d = 37'h0;
reg [36:0] diff2_d = 37'h0;
reg [15:0] word_count = 16'h0;
reg word_clk = 1'b0;
reg enable = 1'b0;
/* Perform the Sinc action */
always @(data_in) begin
if (data_in==0)
data_int <= 37'd0;
else /* change 0 to a -1 for twos complement */
data_int <= 37'd1;
end
/* Accumulator (Integrator) Perform the accumulation (IIR) at the speed of
* the modulator. Z = one sample delay MCLKOUT = modulators conversion
* bit rate */
always @(negedge clk) begin
if (reset == 1'b0) begin
/* initialize acc registers on reset */
acc1 <= 37'd0;
acc2 <= 37'd0;
acc3 <= 37'd0;
end else begin
/* perform accumulation process */
acc1 <= acc1 + data_int;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
end
/* decimation stage (MCLKOUT/WORD_CLK) */
always @(posedge clk) begin
if (reset == 1'b1) begin
word_count <= 16'd0;
end else begin
if (word_count == (dec_rate - 1))
word_count <= 16'd0;
else
word_count <= word_count + 16'b1;
end
end
always @(posedge clk) begin
if (reset == 1'b0) begin
word_clk <= 1'b0;
end else begin
if (word_count == (dec_rate/2 - 1))
word_clk <= 1'b1;
else if (word_count == (dec_rate - 1))
word_clk <= 1'b0;
end
end
/* Differentiator (including decimation stage)
* Perform the differentiation stage (FIR) at a lower speed.
* Z = one sample delay WORD_CLK = output word rate */
always @(posedge word_clk) begin
if (reset == 1'b1) begin
acc3_d <= 37'd0;
diff1_d <= 37'd0;
diff2_d <= 37'd0;
diff1 <= 37'd0;
diff2 <= 37'd0;
diff3 <= 37'd0;
end else begin
diff1 <= acc3 - acc3_d;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
end
/* Clock the Sinc output into an output register
* WORD_CLK = output word rate */
always @(posedge word_clk) begin
case (dec_rate)
16'd32: begin
data_out <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
end
16'd64: begin
data_out <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2];
end
16'd128: begin
data_out <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5];
end
16'd256: begin
data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8];
end
16'd512: begin
data_out <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11];
end
16'd1024: begin
data_out <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14];
end
16'd2048: begin
data_out <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17];
end
16'd4096: begin
data_out <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20];
end
default:begin
data_out <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8];
end
endcase
end
/* Synchronize Data Output */
always @(posedge clk) begin
if (reset == 1'b1) begin
data_en <= 1'b0;
enable <= 1'b1;
end else begin
if ((word_count == (dec_rate/2 - 1)) && (enable == 1'b1)) begin
data_en <= 1'b1;
enable <= 1'b0;
end else if ((word_count == (dec_rate - 1)) && (enable == 1'b0)) begin
data_en <= 1'b0;
enable <= 1'b1;
end else
data_en <= 1'b0;
end
end
endmodule

12
library/util_dec256sinc24b/Makefile Normal file
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@ -0,0 +1,12 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_dec256sinc24b
GENERIC_DEPS += ../common/util_dec256sinc24b.v
XILINX_DEPS += util_dec256sinc24b_ip.tcl
include ../scripts/library.mk

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library/util_dec256sinc24b/util_dec256sinc24b_ip.tcl Normal file
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@ -0,0 +1,16 @@
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_dec256sinc24b
adi_ip_files util_dec256sinc24b [list \
"$ad_hdl_dir/library/common/util_dec256sinc24b.v"]
adi_ip_properties_lite util_dec256sinc24b
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]

6
projects/ad7405_fmc/Makefile Normal file
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@ -0,0 +1,6 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

12
projects/ad7405_fmc/README.MD Normal file
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@ -0,0 +1,12 @@
# HDL Reference Design for EVAL-AD7405 and EVAL-ADuM7701
## Product page
http://www.analog.com/en/products/analog-to-digital-converters/integrated-special-purpose-converters/isolated-ad-converters/ad7405.html
## Supported parts
* AD7405
* ADuM7701

48
projects/ad7405_fmc/common/ad7405_bd.tcl Normal file
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@ -0,0 +1,48 @@
create_bd_port -dir O adc_clk
create_bd_port -dir I adc_data
create_bd_port -dir I -from 15 -to 0 filter_decimation_ratio
create_bd_port -dir I filter_reset
ad_ip_instance util_dec256sinc24b sync3
# ADC's DMA
ad_ip_instance axi_dmac axi_ad7405_dma
ad_ip_parameter axi_ad7405_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad7405_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7405_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7405_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad7405_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad7405_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad7405_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad7405_dma CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter axi_ad7405_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# MCLK generation
ad_ip_instance axi_clkgen axi_adc_clkgen
ad_ip_parameter axi_adc_clkgen CONFIG.VCO_DIV $clkgen_vco_div
ad_ip_parameter axi_adc_clkgen CONFIG.VCO_MUL $clkgen_vco_mul
ad_ip_parameter axi_adc_clkgen CONFIG.CLK0_DIV [expr ($sys_cpu_clk_freq * $clkgen_vco_mul) / ($clkgen_vco_div * $ext_clk_rate)]
ad_connect adc_clk axi_adc_clkgen/clk_0
ad_connect sys_cpu_clk axi_adc_clkgen/clk
ad_connect sync3/clk axi_adc_clkgen/clk_0
ad_connect axi_ad7405_dma/fifo_wr_clk axi_adc_clkgen/clk_0
ad_connect filter_reset sync3/reset
ad_connect adc_data sync3/data_in
ad_connect sync3/data_out axi_ad7405_dma/fifo_wr_din
ad_connect sync3/data_en axi_ad7405_dma/fifo_wr_en
ad_connect filter_decimation_ratio sync3/dec_rate
ad_cpu_interconnect 0x44a30000 axi_ad7405_dma
ad_cpu_interconnect 0x44a40000 axi_adc_clkgen
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad7405_dma/m_dest_axi
ad_cpu_interrupt "ps-13" "mb-13" axi_ad7405_dma/irq

23
projects/ad7405_fmc/zed/Makefile Normal file
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@ -0,0 +1,23 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad7405_fmc_zed
M_DEPS += system_constr_singlended.xdc
M_DEPS += system_constr_differential.xdc
M_DEPS += ../common/ad7405_bd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += util_dec256sinc24b
LIB_DEPS += util_i2c_mixer
include ../../scripts/project-xilinx.mk

20
projects/ad7405_fmc/zed/system_bd.tcl Normal file
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@ -0,0 +1,20 @@
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
# System clock is 100 MHz for this base design
set sys_cpu_clk_freq 100
# ADC external clock generator configurations, the reference clock is the
# system clock
# NOTE: For '7 Series' FPGAs the FVCO must be between 600 MHz and 12000 MHz
set clkgen_vco_div 5
set clkgen_vco_mul 50
# specify the external clock rate in MHz (MCLKIN)
set ext_clk_rate 25
source ../common/ad7405_bd.tcl

6
projects/ad7405_fmc/zed/system_constr_differential.xdc Normal file
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@ -0,0 +1,6 @@
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports adc_clk_p] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports adc_clk_n] ; ## FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports adc_data_p] ; ## FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports adc_data_n] ; ## FMC_LPC_LA01_CC_N

4
projects/ad7405_fmc/zed/system_constr_singlended.xdc Normal file
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@ -0,0 +1,4 @@
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports adc_clk] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports adc_data] ; ## FMC_LPC_LA00_CC_N

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projects/ad7405_fmc/zed/system_project.tcl Normal file
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@ -0,0 +1,44 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
##--------------------------------------------------------------
# IMPORTANT: Set AD7405/ADuM7701 operation and interface mode
#
# adc_port_type - Defines the type of the data line: single
# ended (ADuM7701) or differential (AD7405)
#
# LEGEND: single ended - 0
# differential - 1
#
# NOTE : This switch is a 'hardware' switch. Please reimplement the
# design if the variable has been changed.
#
##--------------------------------------------------------------
set adc_port_type 0
adi_project_xilinx ad7405_fmc_zed
if { $adc_port_type == 0 } {
adi_project_files ad7405_fmc_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top_singlended.v" \
"system_constr_singlended.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
} elseif { $adc_port_type == 1 } {
adi_project_files ad7405_fmc_zed [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top_differential.v" \
"system_constr_differential.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
} else {
return -code error [format "ERROR: Invalid data line type! Define as \'0\' (single ended) or \'1\' (differential) ..."]
}
adi_project_run ad7405_fmc_zed

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projects/ad7405_fmc/zed/system_top_differential.v Normal file
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@ -0,0 +1,245 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
output adc_clk_p,
output adc_clk_n,
input adc_data_p,
input adc_data_n);
// internal signals
wire adc_clk_s;
wire adc_data_s;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [15:0] decimation_ratio;
wire filter_reset;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
OBUFDS i_adc_clk_obuf (
.O (adc_clk_p),
.OB (adc_clk_n),
.I (adc_clk_s));
IBUFDS i_adc_data_ibuf (
.I (adc_data_p),
.IB (adc_data_n),
.O (adc_data_s));
assign gpio_i[63:49] = 15'b0;
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_filter_reset (
.dio_t(gpio_t[48]),
.dio_i(gpio_o[48]),
.dio_o(gpio_i[48]),
.dio_p(filter_reset));
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf_dec_ratio (
.dio_t(gpio_t[47:32]),
.dio_i(gpio_o[47:32]),
.dio_o(gpio_i[47:32]),
.dio_p(decimation_ratio));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.adc_clk (adc_clk_s),
.adc_data (adc_data_s),
.filter_decimation_ratio (decimation_ratio),
.filter_reset (filter_reset),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output spdif,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
output adc_clk,
input adc_data);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [15:0] decimation_ratio;
wire filter_reset;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
assign gpio_i[63:49] = 15'b0;
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_filter_reset (
.dio_t(gpio_t[48]),
.dio_i(gpio_o[48]),
.dio_o(gpio_i[48]),
.dio_p(filter_reset));
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf_dec_ratio (
.dio_t(gpio_t[47:32]),
.dio_i(gpio_o[47:32]),
.dio_o(gpio_i[47:32]),
.dio_p(decimation_ratio));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.adc_clk (adc_clk),
.adc_data (adc_data),
.filter_decimation_ratio (decimation_ratio),
.filter_reset (filter_reset),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************