zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

util_dacfifo: Define constraints for bypass

main
Istvan Csomortani 2017-03-07 16:14:46 +02:00
parent 191669ad28
commit 660dddf1e8
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
library/util_dacfifo/util_dacfifo_constr.xdc
View File

@ -4,6 +4,7 @@ set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_waddr_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_lastaddr_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_lastaddr_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_xfer_out*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_xfer_out*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_bypass*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_bypass*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_bypass*}]
set_false_path -from [get_cells -hier -filter {name =~ *dac_raddr_g* && IS_SEQUENTIAL}] \ set_false_path -from [get_cells -hier -filter {name =~ *dac_raddr_g* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dma_raddr_m1* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dma_raddr_m1* && IS_SEQUENTIAL}]
@ -15,3 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_fifo* && IS
-to [get_cells -hier -filter {name =~ *dac_xfer_out_fifo_m1* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_xfer_out_fifo_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_bypass* && IS_SEQUENTIAL}] \ set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_bypass* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_xfer_out_bypass_m1* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dac_xfer_out_bypass_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dac_bypass_m1* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *dma_bypass_m1* && IS_SEQUENTIAL}]