From 660dddf1e81ee8bcf3ac9c0c13e36b9212103fa7 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 7 Mar 2017 16:14:46 +0200 Subject: [PATCH] util_dacfifo: Define constraints for bypass --- library/util_dacfifo/util_dacfifo_constr.xdc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/library/util_dacfifo/util_dacfifo_constr.xdc b/library/util_dacfifo/util_dacfifo_constr.xdc index bc18e26b8..7a806922c 100644 --- a/library/util_dacfifo/util_dacfifo_constr.xdc +++ b/library/util_dacfifo/util_dacfifo_constr.xdc @@ -4,6 +4,7 @@ set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_waddr_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_lastaddr_m*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_xfer_out*}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dma_bypass*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dac_bypass*}] set_false_path -from [get_cells -hier -filter {name =~ *dac_raddr_g* && IS_SEQUENTIAL}] \ -to [get_cells -hier -filter {name =~ *dma_raddr_m1* && IS_SEQUENTIAL}] @@ -15,3 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_fifo* && IS -to [get_cells -hier -filter {name =~ *dac_xfer_out_fifo_m1* && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *dma_xfer_out_bypass* && IS_SEQUENTIAL}] \ -to [get_cells -hier -filter {name =~ *dac_xfer_out_bypass_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *dac_bypass_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *dma_bypass_m1* && IS_SEQUENTIAL}]