axi_logic_analyzer: Initial commit
parent
9c975211da
commit
6604cc7322
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += ../common/ad_rst.v
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M_DEPS += ../common/up_axi.v
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M_DEPS += ../common/up_xfer_cntrl.v
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M_DEPS += ../common/up_xfer_status.v
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M_DEPS += ../scripts/adi_env.tcl
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M_DEPS += ../scripts/adi_ip.tcl
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M_DEPS += axi_logic_analyzer.v
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M_DEPS += axi_logic_analyzer_constr.xdc
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M_DEPS += axi_logic_analyzer_ip.tcl
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M_DEPS += axi_logic_analyzer_reg.v
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M_DEPS += axi_logic_analyzer_trigger.v
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += component.xml
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.ip_user_files
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M_FLIST += *.srcs
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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.PHONY: all clean clean-all
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all: axi_logic_analyzer.xpr
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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axi_logic_analyzer.xpr: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) axi_logic_analyzer_ip.tcl >> axi_logic_analyzer_ip.log 2>&1
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####################################################################################
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####################################################################################
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@ -0,0 +1,297 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_logic_analyzer (
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input clk,
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output clk_out,
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input [15:0] data_i,
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output reg [15:0] data_o,
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output [15:0] data_t,
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input [ 1:0] trigger_i,
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output reg adc_valid,
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output reg [15:0] adc_data,
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input [15:0] dac_data,
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input dac_valid,
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output reg dac_read,
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output trigger_out,
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output [31:0] trigger_offset,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal registers
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reg [15:0] data_m1 = 'd0;
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reg [15:0] data_r = 'd0;
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reg [ 1:0] trigger_m1 = 'd0;
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reg [ 1:0] trigger_m2 = 'd0;
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reg [31:0] downsampler_counter_la = 'd0;
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reg [31:0] upsampler_counter_pg = 'd0;
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reg sample_valid_la = 'd0;
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reg adc_valid_d1 = 'd0;
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reg adc_valid_d2 = 'd0;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [13:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [13:0] up_raddr;
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wire [31:0] divider_counter_la;
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wire [31:0] divider_counter_pg;
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wire [17:0] edge_detect_enable;
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wire [17:0] rise_edge_enable;
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wire [17:0] fall_edge_enable;
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wire [17:0] low_level_enable;
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wire [17:0] high_level_enable;
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wire [31:0] trigger_delay;
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wire trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR
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wire clock_select;
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wire [15:0] overwrite_enable;
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wire [15:0] overwrite_data;
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wire [15:0] io_selection;
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wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
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genvar i;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign trigger_offset = trigger_delay;
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generate
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for (i = 0 ; i < 16; i = i + 1) begin
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assign data_t[i] = od_pp_n[i] ? io_selection[i] & !data_o[i] : io_selection[i];
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always @(posedge clk) begin
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data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
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end
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end
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endgenerate
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BUFGMUX BUFGMUX_inst (
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.O (clk_out),
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.I0 (data_i[0]),
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.I1 (trigger_i[0]),
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.S (clock_select));
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// synchronization
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always @(posedge clk) begin
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data_m1 <= data_i;
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trigger_m1 <= trigger_i;
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trigger_m2 <= trigger_m1;
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end
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// transfer data at clock frequency
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// if capture is enabled
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always @(posedge clk) begin
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adc_valid_d1 <= adc_valid_d2;
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adc_valid <= adc_valid_d1;
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if (sample_valid_la == 1'b1) begin
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adc_data <= data_m1;
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adc_valid_d2 <= 1'b1;
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end else begin
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adc_valid_d2 <= 1'b0;
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end
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end
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// downsampler logic analyzer
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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sample_valid_la <= 1'b0;
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downsampler_counter_la <= 32'h0;
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end else begin
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if (downsampler_counter_la < divider_counter_la ) begin
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downsampler_counter_la <= downsampler_counter_la + 1;
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sample_valid_la <= 1'b0;
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end else begin
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downsampler_counter_la <= 32'h0;
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sample_valid_la <= 1'b1;
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end
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end
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end
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// upsampler pattern generator
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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upsampler_counter_pg <= 32'h0;
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dac_read <= 1'b0;
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end else begin
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dac_read <= 1'b0;
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if (upsampler_counter_pg < divider_counter_pg) begin
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upsampler_counter_pg <= upsampler_counter_pg + 1;
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end else begin
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upsampler_counter_pg <= 32'h0;
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dac_read <= 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (dac_valid == 1'b1) begin
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data_r <= dac_data;
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end
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end
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axi_logic_analyzer_trigger i_trigger (
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.clk (clk),
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.reset (reset),
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.data (adc_data),
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.trigger (trigger_m2),
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.edge_detect_enable (edge_detect_enable),
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.rise_edge_enable (rise_edge_enable),
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.fall_edge_enable (fall_edge_enable),
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.low_level_enable (low_level_enable),
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.high_level_enable (high_level_enable),
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.trigger_logic (trigger_logic),
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.trigger_out (trigger_out));
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axi_logic_analyzer_reg i_registers (
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.clk (clk),
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.reset (reset),
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.divider_counter_la (divider_counter_la),
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.divider_counter_pg (divider_counter_pg),
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.io_selection (io_selection),
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.edge_detect_enable (edge_detect_enable),
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.rise_edge_enable (rise_edge_enable),
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.fall_edge_enable (fall_edge_enable),
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.low_level_enable (low_level_enable),
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.high_level_enable (high_level_enable),
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.trigger_delay (trigger_delay),
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.trigger_logic (trigger_logic),
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.clock_select (clock_select),
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.overwrite_enable (overwrite_enable),
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.overwrite_data (overwrite_data),
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.input_data (adc_data),
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.od_pp_n (od_pp_n),
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// bus interface
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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// axi interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,30 @@
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set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
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set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
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-to [get_cells -hier -filter {name =~ *downsampler_counter_* && IS_SEQUENTIAL}]
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||||||
|
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
|
||||||
|
-to [get_cells -hier -filter {name =~ *data_r_reg* && IS_SEQUENTIAL}]
|
||||||
|
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
|
||||||
|
-to [get_cells -hier -filter {name =~ *dac_read_reg* && IS_SEQUENTIAL}]
|
||||||
|
|
||||||
|
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] \
|
||||||
|
-to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]
|
||||||
|
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] \
|
||||||
|
-to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg* && IS_SEQUENTIAL}]
|
||||||
|
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \
|
||||||
|
-to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg* && IS_SEQUENTIAL}]
|
||||||
|
|
||||||
|
set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}]
|
||||||
|
|
||||||
|
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}]
|
|
@ -0,0 +1,25 @@
|
||||||
|
# ip
|
||||||
|
|
||||||
|
source ../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
||||||
|
|
||||||
|
adi_ip_create axi_logic_analyzer
|
||||||
|
adi_ip_files axi_logic_analyzer [list \
|
||||||
|
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||||
|
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||||
|
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||||
|
"axi_logic_analyzer_constr.xdc" \
|
||||||
|
"axi_logic_analyzer_reg.v" \
|
||||||
|
"axi_logic_analyzer_trigger.v" \
|
||||||
|
"axi_logic_analyzer.v" ]
|
||||||
|
|
||||||
|
adi_ip_properties axi_logic_analyzer
|
||||||
|
adi_ip_constraints axi_logic_analyzer [list \
|
||||||
|
"axi_logic_analyzer_constr.xdc" ]
|
||||||
|
|
||||||
|
ipx::remove_bus_interface {clk} [ipx::current_core]
|
||||||
|
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
|
||||||
|
|
||||||
|
ipx::save_core [ipx::current_core]
|
||||||
|
|
|
@ -0,0 +1,264 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module axi_logic_analyzer_reg (
|
||||||
|
|
||||||
|
input clk,
|
||||||
|
output reset,
|
||||||
|
|
||||||
|
output [31:0] divider_counter_la,
|
||||||
|
output [31:0] divider_counter_pg,
|
||||||
|
output [15:0] io_selection,
|
||||||
|
|
||||||
|
output [17:0] edge_detect_enable,
|
||||||
|
output [17:0] rise_edge_enable,
|
||||||
|
output [17:0] fall_edge_enable,
|
||||||
|
output [17:0] low_level_enable,
|
||||||
|
output [17:0] high_level_enable,
|
||||||
|
output [31:0] trigger_delay,
|
||||||
|
output trigger_logic,
|
||||||
|
output clock_select,
|
||||||
|
output [15:0] overwrite_enable,
|
||||||
|
output [15:0] overwrite_data,
|
||||||
|
input [15:0] input_data,
|
||||||
|
output [15:0] od_pp_n,
|
||||||
|
|
||||||
|
// bus interface
|
||||||
|
|
||||||
|
input up_rstn,
|
||||||
|
input up_clk,
|
||||||
|
input up_wreq,
|
||||||
|
input [13:0] up_waddr,
|
||||||
|
input [31:0] up_wdata,
|
||||||
|
output reg up_wack,
|
||||||
|
input up_rreq,
|
||||||
|
input [13:0] up_raddr,
|
||||||
|
output reg [31:0] up_rdata,
|
||||||
|
output reg up_rack);
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire up_wreq_s;
|
||||||
|
wire up_rreq_s;
|
||||||
|
|
||||||
|
// internal registers
|
||||||
|
|
||||||
|
reg [31:0] up_version = 32'h00010000;
|
||||||
|
reg [31:0] up_scratch = 0;
|
||||||
|
reg [31:0] up_divider_counter_la = 0;
|
||||||
|
reg [31:0] up_divider_counter_pg = 0;
|
||||||
|
reg [15:0] up_io_selection = 16'h0;
|
||||||
|
|
||||||
|
reg [17:0] up_edge_detect_enable = 0;
|
||||||
|
reg [17:0] up_rise_edge_enable = 0;
|
||||||
|
reg [17:0] up_fall_edge_enable = 0;
|
||||||
|
reg [17:0] up_low_level_enable = 0;
|
||||||
|
reg [17:0] up_high_level_enable = 0;
|
||||||
|
reg [31:0] up_trigger_delay = 0;
|
||||||
|
reg up_trigger_logic = 0;
|
||||||
|
reg up_clock_select = 0;
|
||||||
|
reg [15:0] up_overwrite_enable = 0;
|
||||||
|
reg [15:0] up_overwrite_data = 0;
|
||||||
|
reg [15:0] up_od_pp_n = 0;
|
||||||
|
|
||||||
|
wire [15:0] up_input_data;
|
||||||
|
|
||||||
|
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
|
||||||
|
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
|
||||||
|
|
||||||
|
always @(negedge up_rstn or posedge up_clk) begin
|
||||||
|
if (up_rstn == 0) begin
|
||||||
|
up_wack <= 'd0;
|
||||||
|
up_scratch <= 'd0;
|
||||||
|
up_divider_counter_la <= 'd0;
|
||||||
|
up_divider_counter_pg <= 'd0;
|
||||||
|
up_edge_detect_enable <= 'd0;
|
||||||
|
up_rise_edge_enable <= 'd0;
|
||||||
|
up_fall_edge_enable <= 'd0;
|
||||||
|
up_low_level_enable <= 'd0;
|
||||||
|
up_high_level_enable <= 'd0;
|
||||||
|
up_trigger_delay <= 'd0;
|
||||||
|
up_trigger_logic <= 'd0;
|
||||||
|
up_clock_select <= 'd0;
|
||||||
|
up_overwrite_enable <= 'd0;
|
||||||
|
up_overwrite_data <= 'd0;
|
||||||
|
up_io_selection <= 16'h0;
|
||||||
|
up_od_pp_n <= 16'h0;
|
||||||
|
end else begin
|
||||||
|
up_wack <= up_wreq_s;
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
|
||||||
|
up_scratch <= up_wdata;
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
|
||||||
|
up_divider_counter_la <= up_wdata;
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
|
||||||
|
up_divider_counter_pg <= up_wdata;
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
|
||||||
|
up_io_selection <= up_wdata[15:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
|
||||||
|
up_edge_detect_enable <= up_wdata[17:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
|
||||||
|
up_rise_edge_enable <= up_wdata[17:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
|
||||||
|
up_fall_edge_enable <= up_wdata[17:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
|
||||||
|
up_low_level_enable <= up_wdata[17:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
|
||||||
|
up_high_level_enable <= up_wdata[17:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
|
||||||
|
up_trigger_delay <= up_wdata;
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
|
||||||
|
up_trigger_logic <= up_wdata[0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
|
||||||
|
up_clock_select <= up_wdata[0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
|
||||||
|
up_overwrite_enable <= up_wdata[15:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin
|
||||||
|
up_overwrite_data <= up_wdata[15:0];
|
||||||
|
end
|
||||||
|
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
|
||||||
|
up_od_pp_n <= up_wdata[15:0];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
// processor read interface
|
||||||
|
|
||||||
|
always @(negedge up_rstn or posedge up_clk) begin
|
||||||
|
if (up_rstn == 0) begin
|
||||||
|
up_rack <= 'd0;
|
||||||
|
up_rdata <= 'd0;
|
||||||
|
end else begin
|
||||||
|
up_rack <= up_rreq_s;
|
||||||
|
if (up_rreq_s == 1'b1) begin
|
||||||
|
case (up_raddr[4:0])
|
||||||
|
5'h0: up_rdata <= up_version;
|
||||||
|
5'h1: up_rdata <= up_scratch;
|
||||||
|
5'h2: up_rdata <= up_divider_counter_la;
|
||||||
|
5'h3: up_rdata <= up_divider_counter_pg;
|
||||||
|
5'h4: up_rdata <= {16'h0,up_io_selection};
|
||||||
|
5'h5: up_rdata <= {14'h0,up_edge_detect_enable};
|
||||||
|
5'h6: up_rdata <= {14'h0,up_rise_edge_enable};
|
||||||
|
5'h7: up_rdata <= {14'h0,up_fall_edge_enable};
|
||||||
|
5'h8: up_rdata <= {14'h0,up_low_level_enable};
|
||||||
|
5'h9: up_rdata <= {14'h0,up_high_level_enable};
|
||||||
|
5'ha: up_rdata <= up_trigger_delay;
|
||||||
|
5'hb: up_rdata <= {31'h0,up_trigger_logic};
|
||||||
|
5'hc: up_rdata <= {31'h0,up_clock_select};
|
||||||
|
5'hd: up_rdata <= {16'h0,up_overwrite_enable};
|
||||||
|
5'he: up_rdata <= {16'h0,up_overwrite_data};
|
||||||
|
5'hf: up_rdata <= {16'h0,up_input_data};
|
||||||
|
5'h10: up_rdata <= {16'h0,up_od_pp_n};
|
||||||
|
default: up_rdata <= 0;
|
||||||
|
endcase
|
||||||
|
end else begin
|
||||||
|
up_rdata <= 32'd0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset));
|
||||||
|
|
||||||
|
up_xfer_cntrl #(.DATA_WIDTH(252)) i_xfer_cntrl (
|
||||||
|
.up_rstn (up_rstn),
|
||||||
|
.up_clk (up_clk),
|
||||||
|
.up_data_cntrl ({ up_od_pp_n, // 16
|
||||||
|
up_overwrite_data, // 16
|
||||||
|
up_overwrite_enable, // 16
|
||||||
|
up_clock_select, // 1
|
||||||
|
up_trigger_logic, // 1
|
||||||
|
up_trigger_delay, // 32
|
||||||
|
up_high_level_enable, // 18
|
||||||
|
up_low_level_enable, // 18
|
||||||
|
up_fall_edge_enable, // 18
|
||||||
|
up_rise_edge_enable, // 18
|
||||||
|
up_edge_detect_enable, // 18
|
||||||
|
up_io_selection, // 16
|
||||||
|
up_divider_counter_pg, // 32
|
||||||
|
up_divider_counter_la}), // 32
|
||||||
|
|
||||||
|
.up_xfer_done (),
|
||||||
|
.d_rst (1'b0),
|
||||||
|
.d_clk (clk),
|
||||||
|
.d_data_cntrl ({ od_pp_n, // 16
|
||||||
|
overwrite_data, // 16
|
||||||
|
overwrite_enable, // 16
|
||||||
|
clock_select, // 1
|
||||||
|
trigger_logic, // 1
|
||||||
|
trigger_delay, // 32
|
||||||
|
high_level_enable, // 18
|
||||||
|
low_level_enable, // 18
|
||||||
|
fall_edge_enable, // 18
|
||||||
|
rise_edge_enable, // 18
|
||||||
|
edge_detect_enable, // 18
|
||||||
|
io_selection, // 16
|
||||||
|
divider_counter_pg, // 32
|
||||||
|
divider_counter_la})); // 32
|
||||||
|
|
||||||
|
up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
|
||||||
|
|
||||||
|
// up interface
|
||||||
|
|
||||||
|
.up_rstn(up_rstn),
|
||||||
|
.up_clk(up_clk),
|
||||||
|
.up_data_status(up_input_data),
|
||||||
|
|
||||||
|
// device interface
|
||||||
|
|
||||||
|
.d_rst(1'd0),
|
||||||
|
.d_clk(clk),
|
||||||
|
.d_data_status(input_data));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
|
@ -0,0 +1,114 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
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|
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||||||
|
module axi_logic_analyzer_trigger (
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|
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|
input clk,
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input reset,
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|
input [15:0] data,
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|
input [ 1:0] trigger,
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||||||
|
|
||||||
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input [17:0] edge_detect_enable,
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|
input [17:0] rise_edge_enable,
|
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|
input [17:0] fall_edge_enable,
|
||||||
|
input [17:0] low_level_enable,
|
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|
input [17:0] high_level_enable,
|
||||||
|
|
||||||
|
input trigger_logic,
|
||||||
|
|
||||||
|
output trigger_out);
|
||||||
|
|
||||||
|
reg [ 17:0] data_m1 = 'd0;
|
||||||
|
reg [ 17:0] low_level = 'd0;
|
||||||
|
reg [ 17:0] high_level = 'd0;
|
||||||
|
reg [ 17:0] edge_detect = 'd0;
|
||||||
|
reg [ 17:0] rise_edge = 'd0;
|
||||||
|
reg [ 17:0] fall_edge = 'd0;
|
||||||
|
reg [ 31:0] delay_count = 'd0;
|
||||||
|
|
||||||
|
reg trigger_active;
|
||||||
|
|
||||||
|
assign trigger_out = trigger_active;
|
||||||
|
|
||||||
|
// trigger logic:
|
||||||
|
// 0 OR
|
||||||
|
// 1 AND
|
||||||
|
|
||||||
|
always @(*) begin
|
||||||
|
case (trigger_logic)
|
||||||
|
0: trigger_active = | ((edge_detect & edge_detect_enable) |
|
||||||
|
(rise_edge & rise_edge_enable) |
|
||||||
|
(fall_edge & fall_edge_enable) |
|
||||||
|
(low_level & low_level_enable) |
|
||||||
|
(high_level & high_level_enable));
|
||||||
|
1: trigger_active = | (((edge_detect & edge_detect_enable) | !(|edge_detect_enable)) &
|
||||||
|
((rise_edge & rise_edge_enable) | !(|rise_edge_enable)) &
|
||||||
|
((fall_edge & fall_edge_enable) | !(|fall_edge_enable)) &
|
||||||
|
((low_level & low_level_enable) | !(|low_level_enable)) &
|
||||||
|
((high_level & high_level_enable) | !(|high_level_enable)));
|
||||||
|
default: trigger_active = 1'b1;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (reset == 1'b1) begin
|
||||||
|
data_m1 <= 'd0;
|
||||||
|
edge_detect <= 'd0;
|
||||||
|
rise_edge <= 'd0;
|
||||||
|
fall_edge <= 'd0;
|
||||||
|
low_level <= 'd0;
|
||||||
|
high_level <= 'd0;
|
||||||
|
end else begin
|
||||||
|
data_m1 <= {trigger, data} ;
|
||||||
|
edge_detect <= data_m1 ^ {trigger, data};
|
||||||
|
rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data};
|
||||||
|
fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data};
|
||||||
|
low_level <= ~{trigger, data};
|
||||||
|
high_level <= {trigger, data};
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
Loading…
Reference in New Issue